CN108923884B - PCS (personal communications System) evaluation system, PCS evaluation method, readable storage medium and terminal - Google Patents
PCS (personal communications System) evaluation system, PCS evaluation method, readable storage medium and terminal Download PDFInfo
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Abstract
The invention provides a PCS (personal communications System) evaluation system, which is applied to the field of PCS evaluation and comprises the following steps: the coding module is used for receiving an excitation code stream sent by the external excitation module; the scrambling module is used for scrambling the coded code stream; the processing module is used for carrying out error correction and other processing on the code stream after scrambling processing to obtain a processed code stream; the evaluation module is used for carrying out statistics on a first number obtained by carrying out statistics on 0 in the processed code stream, a second number obtained by carrying out statistics on 1 in the processed code stream, a third number obtained by carrying out statistics on continuous 0 and a fourth number obtained by carrying out statistics on continuous 1 in the processed code stream in a first time period, and carrying out evaluation on the direct current balance performance and the jump performance of the PCS system; and the output module is used for sending the evaluation result of the evaluation module to the outside. By applying the embodiment of the invention, the problem that the transmission capability of the PMA is reduced due to DC imbalance of the PCS and continuous 0 s and continuous 1 s, which is difficult to find in the early design stage in the prior art, is solved in a quantitative measurement and calculation mode.
Description
Technical Field
The present invention relates to the field of PCS evaluation technologies, and in particular, to a PCS evaluation system, a PCS evaluation method, a readable storage medium, and a terminal.
Background
The PCS (Physical Coding Sublayer) is located between the coordination Sublayer (via GMII) and the Physical medium access layer (PMA) Sublayer. In the PCS design of the Serdes serializer/deserializer, the problem of code stream DC balance and the problems of continuous 0 and continuous 1 need to be processed, the problem of DC balance is the problem of direct current jump, and the problems of continuous 0 and continuous 1 are the problem of jump performance.
In the prior art, a high-speed coding mode such as 64/66B is usually selected in a high-speed PCS design to improve transmission efficiency, but such coding does not ensure DC balance, where DC balance refers to whether 1 and 0 in a coded signal appear alternately, and if too many 1 or too many 0 appear continuously, the coding is unbalanced, and the imbalance in number caused by the consecutive 1 or the consecutive 0 causes a shift of a center potential in a differential pair eye diagram, so that a receiving end bit error rate is significantly increased.
Due to the continuous nonuniformity of continuous 1 or continuous 0 in number, even if a scrambler is added in the design, the number of continuous 0 and continuous 1 can be changed after the re-logic, so that the 0 and 1 jump variability in the PCS output code stream cannot be ensured, namely the requirement of PMA cannot be completely met, and the transmission performance of PMA can be reduced. Meanwhile, the traditional mode based on theoretical calculation evaluates the jump performance of the code stream, and the result is affected differently by different load data, so that the quantitative measurement and calculation are difficult.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, it is an object of the present invention to provide a PCS evaluation system, method, readable storage medium and terminal for solving the problem of the prior art that DC imbalance of PCS and consecutive 0 s and consecutive 1 s cause decrease of PMA transmission capability.
To achieve the above and other related objects, the present invention provides a PCS estimation system, wherein the PCS is a physical coding sublayer, the estimation system comprising: the device comprises a coding module, a scrambling module, a processing module, an evaluation module and an output module, wherein the coding module, the scrambling module, the processing module, the evaluation module and the output module are sequentially connected; the coding module is used for receiving an excitation code stream sent by an external excitation module and coding the excitation code stream; the scrambling module is used for scrambling the code stream output by the coding module; the processing module is used for carrying out error correction, bit width conversion and/or synchronous processing on the code stream after the scrambling processing to obtain a processed code stream; the evaluation module is configured to perform statistics on a first number obtained by performing statistics on 0 in the processed code stream pointer, a second number obtained by performing statistics on 1 in the processed code stream pointer, perform statistics on a third number obtained by performing statistics on consecutive 0 and a fourth number obtained by performing statistics on consecutive 1 in a second time period, perform evaluation on dc balance performance and hopping performance of the PCS system according to the first number, the second number, the third number, and the fourth number, and send an evaluation result to the output module, where the evaluation module includes:
a first statistics submodule, configured to count, in a first time period, the first number obtained by counting 0 s in the processed code stream, the second number obtained by counting 1 s in the processed code stream, and calculate a first target number, where the first target number is: an absolute value of a difference between the first number and the second number;
the second counting submodule is used for counting continuous 0 to obtain the third number and counting continuous 1 to obtain the fourth number in a second time period;
the obtaining submodule is used for obtaining the maximum value in the third number and recording the maximum value as the second target number and the maximum value in the fourth number and recording the maximum value as the third target number;
the evaluation submodule is used for evaluating the direct current balance performance and the jump performance according to the first target number, the second target number and the third target number, and the distribution condition of the second target number or the third target number is marked as a target distribution map by taking the length of 0 to 1 as a scale; estimating the trend through the distribution graph of the second target number and the third target number along with the test time, predicting the maximum value of 0 to 1, and sending the estimation result to the output module;
wherein the evaluation submodule is specifically configured to:
judging whether the number of the first targets is not more than a first preset value, whether the number of the second targets is not more than a second preset value and whether the number of the third targets is not more than a third preset value; if yes, determining that the evaluation result of the PCS system is qualified;
and the output module is used for sending the evaluation result of the evaluation module to the outside through an interface.
Preferably, the excitation code stream sent by the excitation module is: a PRBS pseudo-random sequence, or all 0 and all 1, or 0 and 1 switching sequences, or 0 and 1 length increasing sequences.
Preferably, the coding module is a high-speed coding module, and comprises a 64B/66B coding module, a 64B/67B coding module, a 32B/34B coding module and a 128B/130B coding module.
Preferably, the interface of the output module includes but is not limited to SPI, I2C, CSR, MDIO, MCI, APB bus interface.
In addition, the invention also discloses a PCS evaluation method, wherein the PCS is a physical coding sublayer, and the method comprises the following steps:
step 1: receiving an excitation code stream, and encoding the excitation code stream to obtain an encoded code stream;
step 2: carrying out scrambling processing on the coded code stream, and carrying out error correction, bit width conversion and/or synchronization processing on the coded code stream after scrambling processing to obtain a processed code stream;
and step 3: in a first time period, counting 0 in the processed code stream to obtain a first number, counting 1 in the processed code stream to obtain a second number, counting consecutive 0 in the second time period to obtain a third number, counting consecutive 1 in the second time period to obtain a fourth number, and evaluating the direct current balance performance and the jump performance of the PCS system according to the first number, the second number, the third number and the fourth number to obtain an evaluation result, specifically comprising:
in a first time period, counting 0 in the processed code stream to obtain the first number, counting 1 in the processed code stream to obtain the second number, and calculating a first target number, wherein the first target number is: an absolute value of a difference between the first number and the second number; in a second time period, counting continuous 0 to obtain the third number and counting continuous 1 to obtain the fourth number;
acquiring the maximum value of the third number, recording the maximum value as a second target number, and recording the maximum value of the fourth number as a third target number; evaluating the direct current balance performance and the jump performance according to the first target number, the second target number and the third target number, and recording the distribution condition of the second target number or the third target number as a target distribution map by taking the length of 0 to 1 as a scale; estimating a trend through a distribution graph of the second target number and the third target number along with test time, predicting a maximum value of 0 to 1, and finally outputting an estimation result, wherein the step of estimating the direct current balance performance and the jump performance according to the first target number, the second target number and the third target number comprises the following steps:
judging whether the number of the first targets is not more than a first preset value, whether the number of the second targets is not more than a second preset value and whether the number of the third targets is not more than a third preset value;
if yes, determining the evaluation result as qualified.
Preferably, the excitation code stream includes but is not limited to: a PRBS pseudo-random sequence, or all 0 and all 1, or 0 and 1 switching sequences, or 0 and 1 length increasing sequences.
In addition, the invention also discloses a readable storage medium, wherein a computer program is stored, and the program realizes the steps of any PCS evaluation method when being executed by a processor.
And a terminal comprising a processor memory having stored thereon program instructions that when executed by the processor implement the steps of any of the PCS estimation methods.
As described above, the PCS evaluation system, the PCS evaluation method, the readable storage medium, and the terminal of the present invention have the following advantages: the problem of PMA transmission performance degradation due to DC imbalance and consecutive 0 or 1 overlength problems is easily discovered and debugged early in PCS design.
Drawings
FIG. 1 is a schematic diagram of a PCS evaluation system according to the present invention.
FIG. 2 is a schematic diagram of an evaluation module according to the present invention.
FIG. 3 shows a target distribution diagram of the PCS estimation method of the present invention.
FIG. 4 is a diagram showing the distribution of the second target number and the third target number over the test time in the PCS evaluation method of the present invention.
FIG. 5 is a flow chart of a PCS estimation method of the present invention.
Description of the element reference numerals
1 PCS evaluation system
11 coding module
12 scramble module
13 processing module
14 evaluation module
15 output module
2 excitation module
3 PMA
Steps S501 to S503
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Referring to fig. 1, for a PCS evaluation system provided in an embodiment of the present invention, the evaluation system 1 includes: the device comprises an encoding module 11, a scrambling module 12, a processing module 13, an evaluation module 14 and an output module 15, wherein the encoding module 11, the scrambling module 12, the processing module 13, the evaluation module 14 and the output module 15 are connected in sequence.
And the encoding module 11 is configured to receive an excitation code stream sent by an external excitation module, and encode the excitation code stream.
It should be noted that the encoding module 11 needs to receive a code stream to be encoded, in the embodiment of the present invention, the code stream to be encoded comes from an excitation code stream sent by the excitation module 2, the excitation module 2 is used to send a digital signal composed of 0 and 1, specifically, the excitation code stream is: a PRBS pseudo-random sequence, or all 0 and all 1, or 0 and 1 switching sequences, or 0 and 1 length increasing sequences. The specific excitation code stream form is not limited herein in the embodiments of the present invention.
It is understood that the encoding module 11 is used for encoding the excitation code stream at high speed, and the specific encoding module 11 may be a 64B/66B encoding module, a 64B/67B encoding module, for example, 64B/66B encoding or 64B/67B encoding is a critical part of a gigabit ethernet PCS. It is a coding and decoding mode based on scrambling mechanism. The encoding method is a standard encoding method recommended by IEEE for 10G communication, and the process of implementing encoding is the prior art, and specific encoding processes in the embodiments of the present invention are not described herein.
And a scrambling module 12, configured to perform scrambling processing on the code stream of the coding module.
In the embodiment of the invention, the scrambling module 12 performs two parts of processing on the received code stream, one part of the processing is performed with DC balance processing and is specifically used for performing balance processing on 1 and 0 in the received code stream, and the other part is the scrambling module which is used for performing regular randomization processing on the codes and inhibiting longer connection 0 and longer connection 1 in the line codes.
And the processing module 13 is configured to perform error correction, and/or bit width conversion, and/or synchronization processing on the coded code stream after the scrambling processing to obtain a processed code stream.
In the embodiment of the present invention, the processing module 13 is configured to further process the signal processed by the interference module 12, specifically, may perform one or more processing manners of error correction processing, bit width conversion processing, or synchronization processing, and it can be understood that the signal subjected to error correction processing, bit width conversion processing, or synchronization processing changes, for example, 0 in the original partial signal becomes 1, or the original partial signal 1 becomes 0, which may cause a change of the signal, and may cause a DC imbalance and a problem of consecutive 0 or consecutive 1 being too long.
And the evaluation module 14 is configured to perform statistics on a first number obtained by performing statistics on 0 in the processed code stream and a second number obtained by performing statistics on 1 in the processed code stream in a first time period, perform statistics on a third number obtained by performing statistics on consecutive 0 in a second time period and a fourth number obtained by performing statistics on consecutive 1 in the second time period, perform evaluation on the dc balance performance and the hopping performance of the PCS system according to the first number, the second number, the third number, and the fourth number, and send an evaluation result to the output module.
Specifically, referring to fig. 2, the evaluation module 14 includes:
the first statistics submodule 141 is configured to count a first number obtained by counting 0 in the processed code stream and a second number obtained by counting 1 in the processed code stream in a first time period, and calculate a first target number, where the first target number is: an absolute value of a difference between the first number and the second number.
And the second counting submodule 142 is configured to count consecutive 0 s to obtain a third number and count consecutive 1 s to obtain a fourth number in a second time period.
Assuming that the first time period is 0.005ms, the first number of 0 s and the second number of 1 s are 105 and 96 respectively, the first target number is 105 minus 96 absolute values 9.
Assuming that the second time period is 0.04ms, counting for consecutive 0 s, where consecutive 0 s are two or more 0 s, the first number is a plurality of values when consecutive 0 s occur for a plurality of times, and assuming that the counted third number is: 2. 5, 3 and 7; similarly, for consecutive 1 s, the fourth number obtained is: 4. 2, 3 and 3. In addition, in the embodiment of the present invention, the first time period and the second time period may be the same time period, or may be different time periods, for example, the second time period is a sub-time period in the first time period, so that the number of consecutive 0 s and consecutive 1 s in each sub-time period can be measured more specifically, and the change of 0 s and 1 s can be reflected more.
The obtaining sub-module 143 is configured to obtain a maximum value of the third number, which is recorded as the second target number, and obtain a maximum value of the fourth number, which is recorded as the third target number.
Suppose, since the third number counted is: 2. 5, 3 and 7; the fourth number counted is: 4. 2, 3 and 3, then obtaining the maximum value of the third number as 7, namely the second target number is 7; the maximum value of the fourth number is obtained to be 4, i.e. the third target number is 7.
And the evaluation submodule 144 is configured to evaluate the dc balance performance and the jump performance according to the first target number, the second target number, and the third target number, and send an evaluation result to the output module.
In the embodiment of the present invention, it can be seen whether the total numbers of 0 and 1 in the time period are balanced according to the first target number representing the difference between the total numbers of 0 and 1 in the first time period, the second target number representing the maximum number of consecutive 0 in the second time period, and the third target number representing the maximum number of consecutive 1 in the second time period, and in addition, under the condition that the total numbers are balanced, if the data of consecutive 1 or consecutive 0 is too large, the jump performance is poor, and therefore, the dc balance performance and the jump performance can be evaluated according to the first target number, the second target number, and the third target number.
In a specific implementation manner of the present invention, the evaluation module 14 is configured to count the number of 1 s and 0 s within a period of time, and subtract the number of 1 s and 0 s to obtain an absolute value of the difference between the number of 1 s and the number of 0 s, which is the first target number; and counting the continuous 0 and the continuous 1 in the second time period, and acquiring the maximum value of the continuous 0 or the continuous 1, namely the second target number and the third target number.
Specifically, the evaluation sub-module 144 determines whether the number of the first targets is not greater than a first preset value, whether the number of the second targets is not greater than a second preset value, and whether the number of the third targets is not greater than a third preset value; and if so, determining that the evaluation result of the PCS system is qualified.
And when the number of the first targets is smaller than a preset first preset value, the number of the second targets is smaller than a second preset value and the number of the third targets is smaller than a third preset value, the fact that the direct current balance and the jump performance meet the conditions in the period of time is indicated, and therefore the fact that the direct current balance and the jump performance are qualified can be determined.
It can be understood that, the first preset value, the second preset value and the third preset value are set, and the first target number, the second target number and the third target number are respectively compared, for example, the first preset value is 10, when the first target number is smaller than the first preset value, it indicates that the difference between the numbers of 1 and 0 in the first time period is within 10, so that the difference between the numbers of 1 and 0 in the first time period can be measured, and the excessive difference between the numbers of 0 and 1 is avoided.
In addition, in the second time period, consecutive 0 s are counted and counted respectively to obtain the maximum value, for example, the maximum value is 4, then 4 is the second target number, and similarly, the maximum value of consecutive 1 s in the second time period can be obtained, and if 5 is assumed, then 5 is the third target number.
In order to avoid consecutive 1 overlengths or consecutive 0 overlengths, a second target number and a third target number are provided for comparing consecutive 0 s and consecutive 1 s. And combining the first target number, limiting the difference between the total number of 0 and 1 so as to ensure the direct current balance performance, and if the second target number is less than a second preset value and the third target number is less than a third preset value, indicating that the arrangement of continuous 0 and 1 is more balanced and ensuring the jump performance.
In addition, in the embodiment of the present invention, when the first target number, the second target number, and the third target number are set to satisfy other preset relationships, the evaluation result may be determined to be qualified, and the embodiment of the present invention is not specifically limited herein.
And the output module 15 is used for sending the evaluation result of the evaluation module to the outside through the interface.
Fig. 3 and 4 are fitting curves obtained by fitting a plurality of sets of test results. The test data specifically contains 3 variables: and (3) at a period of time t, the longest value is connected with 0 or 1, namely the second target number and the third target number M, and the longest value is connected with 0 or 1, namely the occurrence frequency N.
Fig. 3 shows a target distribution map. The profile is used to accurately fit the function of the longest 0 to 1 value as a function of the number of occurrences of that value over a period of time, which is used as an evaluation index for the PCS system.
In the figure, the horizontal axis represents the second target number or the third target number, i.e., the longest value is 0 or 1, and the vertical axis represents the number of occurrences of the value. T1, t2 and t3 represent different test times, wherein the time t3 is the longest. According to the statistical rules in the figure, the curve t3 corresponds to the maximum value of the vertical axis for the same values of the horizontal axis. That is, the longer the test time, the more the statistical recurrence, at the same second target or third target value.
For example, with the second target of 0 on the horizontal axis as the maximum value M and the vertical axis as the degree N, an approximate expression is obtained by curve fitting:
wherein a and b are constants. The values of a and b are different from each other in three curves of t1, t2 and t 3.
Usually, in a statistical test in a period of time, the maximum value of 0 to 1 does not appear from 1, and the starting point of the horizontal axis can be customized. The starting point is the value 33, which is the longest link 0 or 1, for example, based on statistical data in the actual link.
FIG. 4 is a graph showing the distribution of the second and third targets M as a function of the test time t, for accurately fitting M as a function of the test time t and predicting the extreme values. The horizontal axis represents time t, and the vertical axis represents the number of the second targets or the third targets M, so that the curve tends to a constant value.
For example, we get a fitting expression by fitting a large amount of data: m ═ klnt, where k is a constant. Through the function, a numerical value M corresponding to the second target number or the third target number when t is 100 years can be obtained, a predicted value is obtained through the quantitative analysis, and the predicted value is output as an evaluation result.
Specifically, in the embodiment of the present invention, the interface of the output module is an SPI bus interface or an I2C bus interface.
Therefore, applying the embodiment of the present invention, the evaluation method finds and debugs the problem of the decrease of the PMA transmission performance due to the DC imbalance and the long 0 length 1 too long at the early stage of the design. It is understood that when the output module 15 outputs the result of the evaluation module 14 and the evaluation module 15 determines that the evaluation result is qualified, the evaluation module 15 is connected to the PMA3, and the PCS is connected to the PMA3 for data communication.
In addition, referring to fig. 5, an embodiment of the present invention further provides a PCS evaluation method, where the method includes the following steps:
s501, receiving an excitation code stream, and encoding the excitation code stream to obtain an encoded code stream;
s502, carrying out scrambling processing on the coded code stream, and carrying out error correction, bit width conversion and/or synchronization processing on the coded code stream after scrambling processing to obtain a processed code stream;
s503, in a first time period, counting 0 in the processed code stream to obtain a first number, counting 1 in the processed code stream to obtain a second number, in a second time period, counting continuous 0 to obtain a third number, and counting continuous 1 to obtain a fourth number, and evaluating the direct current balance performance and the jump performance of the PCS system according to the first number, the second number, the third number and the fourth number to obtain an evaluation result.
In this embodiment of the present invention, step S503 includes:
in a first time period, counting a first number obtained by counting 0 in the processed code stream and a second number obtained by counting 1 in the processed code stream, and calculating a first target number, wherein the first target number is: an absolute value of a difference between the first number and the second number; in a second time period, counting continuous 0 to obtain a third number and counting continuous 1 to obtain a fourth number;
acquiring the maximum value of the third number, recording the maximum value as a second target number, and recording the maximum value of the fourth number as a third target number;
and evaluating the direct current balance performance and the jump performance according to the first target number, the second target number and the third target number to obtain an evaluation result.
In addition, the step of performing the evaluation of the dc balance performance and the jump performance according to the first target number, the second target number, and the third target number to obtain an evaluation result includes:
judging whether the number of the first targets is not more than a first preset value, whether the number of the second targets is not more than a second preset value and whether the number of the third targets is not more than a third preset value;
if yes, determining the evaluation result as qualified.
The specific implementation process refers to the embodiments of fig. 1 and fig. 2, and the embodiments of the present invention are not described herein again.
In summary, according to the PCS evaluation system and method provided by the present invention, the interference module is added after encoding, and the evaluation module evaluates the output of the entire PCS after the processing module (error correction, synchronization, and bit width conversion), so as to ensure that the occurrence of 0 and 1 in the signal output by the PCS in DC balance and the occurrence of consecutive 0 and consecutive 1 can be found in time, which plays a role in evaluating the entire PCS, and can prompt the output result of the PCS of the user in time, and therefore, the problem of PMA transmission performance degradation caused by the DC imbalance output by the PCS and the problem of consecutive 0 or 1 in the process of connecting the PCS and the PMA is ensured. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (8)
1. A PCS estimation system wherein the PCS is a physical coding sublayer, the estimation system comprising: the device comprises a coding module, a scrambling module, a processing module, an evaluation module and an output module, wherein the coding module, the scrambling module, the processing module, the evaluation module and the output module are sequentially connected;
the coding module is used for receiving an excitation code stream sent by an external excitation module and coding the excitation code stream;
the scrambling module is used for scrambling the code stream output by the coding module;
the processing module is used for carrying out error correction, bit width conversion and/or synchronous processing on the code stream after the scrambling processing to obtain a processed code stream;
the evaluation module is configured to, in a first time period, count a first number obtained by counting 0 in the processed code stream, count a second number obtained by counting 1 in the processed code stream, count a third number obtained by counting consecutive 0 in a second time period, count consecutive 1 in the processed code stream to obtain a fourth number, evaluate the dc balance performance and the jump performance of the PCS system according to the first number, the second number, the third number, and the fourth number, and send an evaluation result to the output module, where the evaluation module includes:
a first statistics submodule, configured to count, in a first time period, the first number obtained by counting 0 s in the processed code stream, the second number obtained by counting 1 s in the processed code stream, and calculate a first target number, where the first target number is: an absolute value of a difference between the first number and the second number;
the second counting submodule is used for counting continuous 0 to obtain the third number and counting continuous 1 to obtain the fourth number in a second time period;
the obtaining submodule is used for obtaining the maximum value in the third number and recording the maximum value as the second target number and the maximum value in the fourth number and recording the maximum value as the third target number;
the evaluation submodule is used for evaluating the direct current balance performance and the jump performance according to the first target number, the second target number and the third target number, and the distribution condition of the second target number or the third target number is marked as a target distribution map by taking the length of 0 to 1 as a scale; estimating the trend through the distribution graph of the second target number and the third target number along with the test time, predicting the maximum value of 0 to 1, and sending the estimation result to the output module;
wherein the evaluation submodule is specifically configured to:
judging whether the number of the first targets is not more than a first preset value, whether the number of the second targets is not more than a second preset value and whether the number of the third targets is not more than a third preset value; if yes, determining that the evaluation result of the PCS system is qualified;
and the output module is used for sending the evaluation result of the evaluation module to the outside through an interface.
2. The PCS evaluation system of claim 1 wherein the excitation code stream sent by the excitation module is: a PRBS pseudo-random sequence, or all 0 and all 1, or 0 and 1 switching sequences, or 0 and 1 length increasing sequences.
3. The PCS evaluation system of claim 1 wherein said encoding module is a high speed encoding module including a 64B/66B encoding module, a 64B/67B encoding module, a 32B/34B encoding module, a 128B/130B encoding module.
4. The PCS evaluation system of claim 1 wherein the interface of the output module includes but is not limited to SPI, I2C, CSR, MDIO, MCI, APB bus interfaces.
5. A PCS estimation method, wherein the PCS is a physical coding sublayer, the method comprising the steps of:
step 1: receiving an excitation code stream, and encoding the excitation code stream to obtain an encoded code stream;
step 2: carrying out scrambling processing on the coded code stream, and carrying out error correction, bit width conversion and/or synchronization processing on the coded code stream after scrambling processing to obtain a processed code stream;
and step 3: in a first time period, counting 0 in the processed code stream to obtain a first number, counting 1 in the processed code stream to obtain a second number, counting consecutive 0 in the second time period to obtain a third number, counting consecutive 1 in the second time period to obtain a fourth number, and evaluating the direct current balance performance and the jump performance of the PCS system according to the first number, the second number, the third number and the fourth number to obtain an evaluation result, specifically comprising:
in a first time period, counting 0 in the processed code stream to obtain the first number, counting 1 in the processed code stream to obtain the second number, and calculating a first target number, wherein the first target number is: an absolute value of a difference between the first number and the second number; in a second time period, counting continuous 0 to obtain the third number and counting continuous 1 to obtain the fourth number;
acquiring the maximum value of the third number, recording the maximum value as a second target number, and recording the maximum value of the fourth number as a third target number; evaluating the direct current balance performance and the jump performance according to the first target number, the second target number and the third target number, and recording the distribution condition of the second target number or the third target number as a target distribution map by taking the length of 0 to 1 as a scale; estimating a trend through a distribution graph of the second target number and the third target number along with test time, predicting a maximum value of 0 to 1, and finally outputting an estimation result, wherein the step of estimating the direct current balance performance and the jump performance according to the first target number, the second target number and the third target number comprises the following steps:
judging whether the number of the first targets is not more than a first preset value, whether the number of the second targets is not more than a second preset value and whether the number of the third targets is not more than a third preset value;
if yes, determining the evaluation result as qualified.
6. The PCS evaluation method of claim 5 wherein said excitation codestream includes, but is not limited to: a PRBS pseudo-random sequence, or all 0 and all 1, or 0 and 1 switching sequences, or 0 and 1 length increasing sequences.
7. A readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the PCS evaluation method of any of the claims 5 to 6.
8. A terminal comprising a processor memory having stored thereon program instructions, characterized in that: the processor executes program instructions to implement the steps in the PCS evaluation method as described in any of 5 to 6.
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