CN108922466B - Screen frame rate setting method and device - Google Patents
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- CN108922466B CN108922466B CN201810661100.7A CN201810661100A CN108922466B CN 108922466 B CN108922466 B CN 108922466B CN 201810661100 A CN201810661100 A CN 201810661100A CN 108922466 B CN108922466 B CN 108922466B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
- G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
Abstract
The invention discloses a method and a device for setting a screen frame rate, wherein the method for setting the screen frame rate comprises the following steps: obtaining values of DPI _ CLK _ SRC, divdor, width, height, hfp, hbp, hsync, vfp, vbp, vsync and lane _ num, wherein the DPI _ CLK _ SRC is a DPI clock, the divdor is a frequency division coefficient, the width of a width screen, the height is the height of the screen, and the hfp, hbp, hsync, vfp, vbp and vsync are time sequence parameters of the screen; calculating the value of Fps through a preset formula, wherein the Fps is a frame rate, and the preset formula is as follows: fps ═ DPI _ CLK _ SRC/divdor/(width + hfp + hbp + hsync)/(height + vfp + vbp + vsync); setting the frame rate of the screen to the value of Fps.
Description
Technical Field
The present invention relates to the field of display screens, and in particular, to a method and an apparatus for setting a screen frame rate.
Background
The frame rate and mipi rate of a screen, such as a CRT display screen, an LCD display screen, etc., determine the performance of the screen. In the prior art, when the frame rate is processed, the screen effect cannot reach the optimum effect due to approximate guess or wrong calculation, the consistency is poor, screen splash or screen flashing can occur, and the display screen can be damaged. The prior art cannot calculate the frame rate and the mipi rate of a real screen.
Disclosure of Invention
The invention mainly aims to provide a method and a device for setting a screen frame rate, which can calculate an accurate frame rate and an accurate mipi rate so as to improve the performance of a screen.
The invention provides a method for setting a screen frame rate, which comprises the following steps:
obtaining values of DPI _ CLK _ SRC, divdor, width, height, hfp, hbp, hsync, vfp, vbp, vsync and lane _ num, wherein the DPI _ CLK _ SRC is a DPI clock, the divdor is a frequency division coefficient, the width is the width of a screen, the height is the height of the screen, and the hfp, the hbp, the hsync, the vfp, the vbp and the vsync are time sequence parameters of the screen;
calculating the value of Fps through a preset formula, wherein Fps is a frame rate, and the preset formula is as follows:
Fps＝DPI_CLK_SRC/dividor/(width+hfp+hbp+hsync)/(height+vfp+vbp+vsync)；
setting the frame rate of the screen to the value of Fps.
Further, still include:
obtaining a Lane _ num value, wherein the Lane _ num is the channel number of the screen;
calculating the value range of phy _ feq according to a formula (DPI _ CLK _ SRC/divdor) x 3 x 8bit x 1.2< phy _ feq x lane _ num, and enabling phy _ feq to be the smallest integer in the value range, wherein phy _ feq is the mipi rate;
the mipi rate of the screen is set to the value of phy _ feq.
Further, the step of obtaining the value of dividor includes:
judging whether the DPI _ CLOCK _ SRC-divdor multiplied by the new _ CLOCK is larger than (new _ CLOCK/2);
if not, divdor is DPI _ CLOCK _ SRC/need _ CLOCK;
if yes, the divdor is DPI _ CLOCK _ SRC/need _ CLOCK +1, where need _ CLOCK indicates the current CLOCK frequency.
Further, the step of obtaining the value of DPI _ CLK _ SRC includes:
the value of DPI _ CLK _ SRC is set to 384000000.
Further, the step of obtaining the value of dividor includes:
the value of need _ clock is obtained using the formula (width + hfp + hbp + hsync) × (height + vfp + vbp + vsync) × 60.
The invention provides a screen frame rate setting device, comprising:
the first acquisition module is used for acquiring the values of DPI _ CLK _ SRC, divdor, width, height, hfp, hbp, hsync, vfp, vbp, vsync and lane _ num, wherein the DPI _ CLK _ SRC is a DPI clock, the divdor is a frequency division coefficient, the width is the width of a screen, the height is the height of the screen, and the hfp, hbp, hsync, vfp, vbp and vsync are time sequence parameters of the screen;
a first calculating module, configured to calculate a value of Fps according to a preset formula, where Fps is a frame rate, and the preset formula is:
Fps＝DPI_CLK_SRC/dividor/(width+hfp+hbp+hsync)/(height+vfp+vbp+vsync)；
and the first setting module is used for setting the frame rate of the screen to be the Fps value.
Further, still include:
the second obtaining module is used for obtaining a value of lane _ num, wherein the lane _ num is the channel number of the screen;
and the second calculation module is used for calculating the value of the phy _ feq, wherein phy _ feq is the mipi rate, the value range of phy _ feq is calculated according to a formula (DPI _ CLK _ SRC/divdor) multiplied by 3 multiplied by 8bit multiplied by 1.2< phy _ feq multiplied by lane _ num, and phy _ feq is the smallest integer in the value range.
And the second setting module is used for setting the mipi rate of the screen to be the value of phy _ feq.
Further, still include:
the judging and setting module is used for judging whether the DPI _ CLOCK _ SRC-divdor multiplied by the needed _ CLOCK is larger than (needed _ CLOCK/2), and if not, the divdor is equal to the DPI _ CLOCK _ SRC/needed _ CLOCK; if yes, divdor is DPI _ CLOCK _ SRC/need _ CLOCK +1, where need _ CLOCK indicates the current CLOCK frequency.
Further, still include:
a third setting module, configured to set the value of DPI _ CLK _ SRC to 384000000.
Further, still include:
and the calculation acquisition module is used for acquiring the value of the need _ clock by adopting a formula of (width + hfp + hbp + hsync) × (height + vfp + vbp + vsync) × 60.
According to the method and the device for setting the screen frame rate, the problem that the prior art cannot obtain the accurate screen frame rate and the accurate screen mipi rate is solved, the screen frame rate can be accurately calculated, the performance of the screen is improved, and screen blooming, screen flickering and screen damage are avoided.
Drawings
FIG. 1 is a diagram illustrating a method for setting a frame rate according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating another method for setting a frame rate according to the present invention;
FIG. 3 is a diagram illustrating an apparatus for setting a frame rate according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of another apparatus for setting a frame rate according to the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative only and should not be construed as limiting the invention.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Referring to fig. 1, an embodiment of a screen frame rate setting method provided by the present invention includes the following steps:
s1, obtaining values of DPI _ CLK _ SRC, divdor, width, height, hfp, hbp, hsync, vfp, vbp, vsync and lane _ num, wherein the DPI _ CLK _ SRC is a DPI clock, the divdor is a frequency division coefficient, the width is the width of a screen, the height is the height of the screen, and the hfp, the hbp, the hsync, the vfp, the vbp and the vsync are timing sequence parameters of the screen;
s2, calculating the value of Fps, which is obtained from the formula Fps ═ DPI _ CLK _ SRC/divdor/(width + hfp + hbp + hsync)/(height + vfp + vbp + vsync), where Fps is the frame rate;
and S3, setting the frame rate of the screen to be the Fps value.
The screen in the embodiment comprises a display and a monitor, and is a display tool for displaying the electronic file on the screen through a specific transmission setting and then reflecting the electronic file to human eyes. The screen includes a cathode ray tube display CRT, a plasma display PDP, a liquid crystal display LCD, an LED display screen, and the like. Depending on size or use, the screen may also include a cell phone screen, a computer screen, a television screen, and so forth.
DPI _ CLK _ SRC is a DPI clock with a default value of 384000000, which is 384000000 in this embodiment;
the width is the width of the screen, the height is the height of the screen, and the values of the width and the height are different according to the size of the screen. This embodiment takes an example of a screen having a resolution of 480 × 854.
For hfp, hbp, hsync, vfp, vbp, vsync, this embodiment takes values of 80,80,10,18,20, 6.
If divdor is known, for example, divdor is 11, the above known values are substituted into the frame rate calculation formula to obtain Fps 59, i.e., DPI _ CLK _ SRC/divdor/(width + hfp + hbp + hsync)/(height + vfp + vbp + vsync).
The frame rate of the screen is set to the calculated value of Fps, that is, the frame rate is set to 59, to improve the performance of the screen.
As shown in fig. 2, compared with the previous embodiment, an implementation of the screen frame rate setting method provided by the present invention further includes:
s4, obtaining a Lane _ num value, wherein the Lane _ num is the channel number of the screen;
s5, calculating a value of phy _ feq, wherein phy _ feq is a mipi rate, calculating a value range of phy _ feq according to a formula (DPI _ CLK _ SRC/divdor) multiplied by 3 multiplied by 8bit multiplied by 1.2< phy _ feq multiplied by lane _ num, and making phy _ feq be a minimum integer in the value range;
s6, set the mipi rate for the screen to the value of phy _ feq.
For example, DPI _ CLK _ SRC is a DPI clock, which is 384000000 by default, i.e. 384000000 is assumed in this embodiment;
if divdor is known, for example, divdor is 11, lane _ num is the number of channels of the screen, and if lane _ num is 2;
the known value is substituted into the formula (DPI _ CLK _ SRC/divdor) × 3 × 8bit × 1.2< phy _ feq × lane _ num, and phy _ feq is the smallest integer in the value range, so that phy _ feq is 503.
The mipi rate of the screen is set to the value of the calculated phy _ feq, i.e., the mipi rate is set to 503, to improve the performance of the screen.
In addition, in this embodiment, "S5, calculate the value of phy _ feq, where phy _ feq is the mipi rate, and calculate the value range of phy _ feq according to the formula (DPI _ CLK _ SRC/divdor) × 3 × 8bit × 1.2< phy _ feq × lane _ num," and make phy _ feq be the smallest integer in the value range, "step may be performed after" S3, the step of setting the frame rate of the screen to the Fps value, "or after" S1, the step of obtaining DPI _ CLK _ SRC, divdor, width, height, hfp, hbp, hsync, vfp, vbp, vsync, and lane _ num, "where DPI _ CLK _ SRC is the DPI clock, divdor is the frequency division coefficient, and width is the width of the screen, height is the height of the screen, and timing parameters of hfp, hbp, vsync, and vlan _ num" are performed before or after "step of obtaining the DPI _ CLK _ SRC, divdor, and" step.
Compared with the previous embodiment, in an implementation manner of the screen frame rate setting method provided by the present invention, the step of obtaining the value of dividor includes:
judging whether the DPI _ CLOCK _ SRC-divdor multiplied by the need _ CLOCK is larger than (need _ CLOCK/2), if not, the divdor is a value obtained by the DPI _ CLOCK _ SRC/need _ CLOCK; if yes, divdor is DPI _ CLOCK _ SRC/need _ CLOCK + 1;
here, the need _ clock indicates the clock frequency currently required, and the need _ clock is (width + hfp + hbp + hsync) × (height + vfp + vbp + vsync) × 60.
For example,
DPI _ CLK _ SRC is a DPI clock with a default value of 384000000, which is 384000000 in this embodiment;
width is the width of the screen and height is the height of the screen, and this embodiment takes the example of the screen with the resolution of 480 × 854.
For hfp, hbp, hsync, vfp, vbp, vsync, this embodiment takes values of 80,80,10,18,20, 6.
The value of need _ clock can be calculated using the formula (witdh + hfp + hbp + hsync) x (height + vfp + vbp + vsync) x 60-35022000.
When the known parameters are substituted into the formula, the need _ clock ═ t (witdh + hfp + hbp + hsync) × (height + vfp + vbp + vsync) × 60 ═ 35022000; DPI _ CLOCK _ SRC-divdor × new _ CLOCK > (new _ CLOCK/2), so divdor +1 is DPI _ CLOCK _ SRC/new _ CLOCK + 11.
According to the screen frame rate setting method provided by the invention, the problem that the prior art cannot obtain the accurate screen frame rate and the accurate screen mipi rate is solved, the screen frame rate can be accurately calculated, the screen performance is improved, and screen splash, screen flicker and screen damage are avoided.
Referring to fig. 3, an embodiment of a screen frame rate setting apparatus 100 provided by the present invention includes:
the first obtaining module 10 obtains values of DPI _ CLK _ SRC, divdor, width, height, hfp, hbp, hsync, vfp, vbp, vsync, and lane _ num, where DPI _ CLK _ SRC is a DPI clock, divdor is a frequency division coefficient, width is a screen width, height is a screen height, and hfp, hbp, hsync, vfp, vbp, and vsync are timing parameters of a screen;
a first calculating module 20, configured to calculate a value of Fps, where the value of Fps is obtained by a formula of Fps ═ DPI _ CLK _ SRC/divdor/(width + hfp + hbp + hsync)/(height + vfp + vbp + vsync), where Fps is a frame rate;
and a first setting module 30, configured to set the frame rate of the screen to the value of Fps.
The screen in the embodiment comprises a display and a monitor, and is a display tool for displaying the electronic file on the screen through a specific transmission setting and then reflecting the electronic file to human eyes. The screen includes a cathode ray tube display CRT, a plasma display PDP, a liquid crystal display LCD, an LED display screen, and the like. Depending on size or use, the screen may also include a cell phone screen, a computer screen, a television screen, and so forth.
Acquiring with the first acquisition module 10: DPI _ CLK _ SRC is a DPI clock with a default value of 384000000, which is 384000000 in this embodiment; the width is the width of the screen, the height is the height of the screen, and the values of the width and the height are different according to the size of the screen. This embodiment takes an example of a screen having a resolution of 480 × 854. For hfp, hbp, hsync, vfp, vbp, vsync, this embodiment takes values of 80,80,10,18,20, 6. If divdor is known, for example, divdor ═ 11.
The first calculating module 20 substitutes the known value into the frame rate calculation formula, where Fps is DPI _ CLK _ SRC/divdor/(width + hfp + hbp + hsync)/(height + vfp + vbp + vsync), and Fps is 59.
The first setting module 30 sets the frame rate of the screen to the calculated value of Fps, that is, the frame rate to 59 and the mipi rate to the value of phy _ feq, to improve the performance of the screen.
As shown in fig. 4, compared with the previous embodiment, an embodiment of the screen frame rate setting apparatus 100 provided by the present invention further includes:
a second obtaining module 40, configured to obtain a value of lane _ num, where lane _ num is a channel number of a screen;
the second calculating module 50 calculates the value of phy _ feq, where phy _ feq is the mipi rate, and calculates the value range of phy _ feq according to the formula (DPI _ CLK _ SRC/divdor) × 3 × 8bit × 1.2< phy _ feq × lane _ num, and phy _ feq is the smallest integer in the value range.
A second setting module 60 for setting the mipi rate of the screen to a value of phy _ feq.
Acquiring a value of lane _ num by using a second acquisition module 40, where lane _ num is a channel number of a screen, and for example, lane _ num is 2;
the second calculation submodule 50 is used to calculate phy _ feq. For example, DPI _ CLK _ SRC is a DPI clock, which is 384000000 by default, i.e. 384000000 is assumed in this embodiment;
if divdor is known, for example, divdor ═ 11;
the known value is substituted into the formula (DPI _ CLK _ SRC/divdor) × 3 × 8bit × 1.2< phy _ feq × lane _ num, and phy _ feq is the smallest integer in the value range, so that phy _ feq is 503.
The second setting module 60 is used to set the mipi rate of the screen to a value of phy _ feq, i.e., to 503 to improve the performance of the screen.
Compared with the previous embodiment, the screen frame rate setting apparatus 100 according to an embodiment of the present invention further includes:
a determining and setting module 70, configured to determine whether the DPI _ CLOCK _ SRC-divdor × new _ CLOCK is greater than (new _ CLOCK/2), and if not, the divdor is a value obtained by DPI _ CLOCK _ SRC/new _ CLOCK; if yes, divdor is DPI _ CLOCK _ SRC/need _ CLOCK +1, where need _ CLOCK indicates the currently required CLOCK frequency.
For example,
the DPI _ CLK _ SRC is a DPI clock and defaults to 384000000, and the third setting module 80 is adopted in the embodiment to set the DPI _ CLK _ SRC to 384000000;
width is the width of the screen and height is the height of the screen, and this embodiment takes the example of the screen with the resolution of 480 × 854.
For hfp, hbp, hsync, vfp, vbp, vsync, this embodiment takes values of 80,80,10,18,20, 6.
The calculation acquisition module 90 may be adapted to calculate the value of need _ clock using the formula need _ clock ═ (witdh + hfp + hbp + hsync) × (height + vfp + vbp + vsync) × 60.
The determination setting module 70 substitutes the known parameters into a formula, and need _ clock ═ by (witdh + hfp + hbp + hsync) × (height + vfp + vbp + vsync) × 60 ═ 35022000; DPI _ CLOCK _ SRC-divdor × new _ CLOCK > (new _ CLOCK/2), so divdor +1 is DPI _ CLOCK _ SRC/new _ CLOCK + 11.
According to the screen frame rate setting device provided by the invention, the problem that the accurate screen frame rate and the accurate screen mipi rate cannot be obtained in the prior art is solved, the screen frame rate can be accurately calculated, the screen performance is improved, and screen splash, screen flicker and screen damage are avoided.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (6)
1. A screen frame rate setting method, comprising the steps of:
obtaining values of DPI _ CLK _ SRC, divdor, width, height, hfp, hbp, hsync, vfp, vbp, vsync and lane _ num, wherein the DPI _ CLK _ SRC is a DPI clock, the divdor is a frequency division coefficient, the width is the width of a screen, the height is the height of the screen, and the hfp, the hbp, the hsync, the vfp, the vbp and the vsync are time sequence parameters of the screen;
calculating the value of Fps through a preset formula, wherein Fps is a frame rate, and the preset formula is as follows:
Fps＝DPI_CLK_SRC/dividor/(width+hfp+hbp+hsync)/(height+vfp+vbp+vsync)；
setting the frame rate of the screen as an Fps value;
obtaining a Lane _ num value, wherein the Lane _ num is the channel number of the screen;
calculating the value range of phy _ feq according to a formula (DPI _ CLK _ SRC/divdor) x 3 x 8bit x 1.2< phy _ feq x lane _ num, and enabling phy _ feq to be the smallest integer in the value range, wherein phy _ feq is the mipi rate;
setting the mipi rate of the screen to the value of phy _ feq;
obtaining the value of dividor includes:
judging whether the DPI _ CLOCK _ SRC-divdor multiplied by the new _ CLOCK is larger than (new _ CLOCK/2);
if not, divdor is DPI _ CLOCK _ SRC/need _ CLOCK;
if yes, the divdor is DPI _ CLOCK _ SRC/need _ CLOCK +1, where need _ CLOCK indicates the current CLOCK frequency.
2. The screen frame rate setting method of claim 1, wherein the obtaining of the value of DPI _ CLK _ SRC comprises:
the value of DPI _ CLK _ SRC is set to 384000000.
3. The screen frame rate setting method according to claim 1, wherein the obtaining of the value of divdor comprises:
the value of need _ clock is obtained using the formula (width + hfp + hbp + hsync) × (height + vfp + vbp + vsync) × 60.
4. A screen frame rate setting apparatus, comprising:
the first acquisition module is used for acquiring the values of DPI _ CLK _ SRC, divdor, width, height, hfp, hbp, hsync, vfp, vbp, vsync and lane _ num, wherein the DPI _ CLK _ SRC is a DPI clock, the divdor is a frequency division coefficient, the width is the width of a screen, the height is the height of the screen, and the hfp, hbp, hsync, vfp, vbp and vsync are time sequence parameters of the screen;
a first calculating module, configured to calculate a value of Fps according to a preset formula, where Fps is a frame rate, and the preset formula is:
Fps＝DPI_CLK_SRC/dividor/(width+hfp+hbp+hsync)/(height+vfp+vbp+vsync)；
the first setting module is used for setting the frame rate of the screen to be an Fps value;
the second obtaining module is used for obtaining a value of lane _ num, wherein the lane _ num is the channel number of the screen;
the second calculation module is used for calculating the value of phy _ feq, wherein phy _ feq is the mipi rate, the value range of phy _ feq is calculated according to a formula (DPI _ CLK _ SRC/divdor) multiplied by 3 multiplied by 8bit multiplied by 1.2< phy _ feq multiplied by lane _ num, and phy _ feq is made to be the smallest integer in the value range;
a second setting module for setting the mipi rate of the screen to a value of phy _ feq;
further comprising:
the judging and setting module is used for judging whether the DPI _ CLOCK _ SRC-divdor multiplied by the needed _ CLOCK is larger than (needed _ CLOCK/2), and if not, the divdor is equal to the DPI _ CLOCK _ SRC/needed _ CLOCK; if yes, divdor is DPI _ CLOCK _ SRC/need _ CLOCK +1, where need _ CLOCK indicates the current CLOCK frequency.
5. The screen frame rate setting apparatus according to claim 4, further comprising:
a third setting module, configured to set the value of DPI _ CLK _ SRC to 384000000.
6. The screen frame rate setting apparatus according to claim 4, further comprising:
and the calculation acquisition module is used for acquiring the value of the need _ clock by adopting a formula of (width + hfp + hbp + hsync) × (height + vfp + vbp + vsync) × 60.
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| CN101496089A (en) * | 2006-07-31 | 2009-07-29 | 夏普株式会社 | Display controller, display device, display system, and control method for display device |
| CN201904792U (en) * | 2010-12-22 | 2011-07-20 | 桂林电子科技大学 | Multi-channel adaptive multi-rate code speed regulating device |
| CN202662264U (en) * | 2012-06-08 | 2013-01-09 | 联美新视信息科技（上海）有限公司 | Liquid crystal display (LCD) refresh frequency selecting device |
| CN103997399A (en) * | 2014-05-05 | 2014-08-20 | 京东方科技集团股份有限公司 | EDP interface, handset and method for improving transmission rate of eDP interface communication |
| CN105869560A (en) * | 2016-04-01 | 2016-08-17 | 广东欧珀移动通信有限公司 | Display screen refreshing frame rate adjusting method and apparatus |
| CN107845357A (en) * | 2017-09-28 | 2018-03-27 | 深圳前海骁客影像科技设计有限公司 | Measurement jig lights the method and device of display screen |
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