CN108899057A - Read DQS signal door gating training method, device and data transmission system - Google Patents
Read DQS signal door gating training method, device and data transmission system Download PDFInfo
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- CN108899057A CN108899057A CN201810602252.XA CN201810602252A CN108899057A CN 108899057 A CN108899057 A CN 108899057A CN 201810602252 A CN201810602252 A CN 201810602252A CN 108899057 A CN108899057 A CN 108899057A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
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Abstract
The present invention provides a kind of reading DQS signal door gating training method, device and data transmission system, the door for first generating the clock period wide that a width is BL/2-1 reading DQS signal based on a read request gates enable signal, it controls the door gating enable signal again to be moved from left to right until the failing edge of door gating enable signal is just beyond the second-to-last rising edge for reading DQS signal, the door after being moved gates enable signal；Then by the door gating enable signal delay after the movement, the door after being postponed gates enable signal；Again using the rising edge of the door gating enable signal after the delay as the starting position of door strobe window, using the position of the last one failing edge for reading DQS signal as the end position of door strobe window, to obtain the final door strobe window for reading DQS signal, the timing allowance for reading DQS signal door gating training result can be greatly improved, system job stability is enhanced.
Description
Technical field
The present invention relates to field of data access technology more particularly to a kind of reading DQS signal door gating training method, device with
And data transmission system.
Background technique
DDR (Double Data Rate, Double Data Rate) system is DDR SDRAM (Synchronous Dynamic
Random Access Memory, double data rate Synchronous Dynamic Random Access Memory) system it is habitual referred to as,
Advantage is that memory capacity is big, at low cost, interface is mature, and when parallel burst access, can achieve higher access rate.
It please refers to shown in Fig. 1, generally, DDR system is mainly by controller DDRC, physical layer DDR PHY and memory grain
DRAM and between bus composition.The signal transmitted in bus mainly includes clock signal clk, command signal CMD, address letter
Number ADDR, data-signal DQ and read strobe signal DQS (also known as data sampling signal, data strobe signal or read DQS letter
Number).Wherein clock signal clk, command signal CMD, address signal ADDR are the one way signal from DDR PHY to DRAM, data
Signal DQ and reading DQS signal are two-way signalings.
The DDR system can transmit data using burst mode (Burst mode), specifically, grasp without reading and writing data
When making, DQ and DQS are in high resistant (High Z) state；And when carrying out read operation, referring to FIG. 2, DRAM first can be by DQS signal
The low level of (i.e. reading DQS signal) preset a cycle width, referred to as Preamble (preamble, such as the ideal DQS wave in Fig. 2
Instruction in shape), purpose be mainly prompt controller DDRC read data will occur, then DRAM with clock style to
Receiving end (the i.e. front-end receiver inside DDR PHY, for converting bus signals to internal Digital Logic of DDR PHY
Signal) it sends and reads DQS signal (as shown in the true DQS waveform in Fig. 2), until a burst (burst signal) terminates, at this
In the process, data-signal DQ (as shown in DQ waveform in Fig. 2) is and reads DQS signal edge and sent in alignment by DRAM.Work as DRAM
The reading DQS signal of sending becomes logic low (0, logic low) from high resistant (High Z) or becomes high resistant from low level (0)
When (High Z), due to non-ideal factors such as parasitic inductance capacitors, signal can generate oscillation (glitch, such as DQS true in Fig. 2
Virtual coil at waveform beginning and end is marked), these oscillations can be converted to Digital Logic by DDR PHY front-end receiver
" 1 ", in preamble (preamble) and postamble, (postorder is used for the reading DQS signal for causing DDR PHY front-end receiver to export
The data end of transmission for prompting controller DDRC request to read) place generate burr (glitch, before DDR PHY in Fig. 2
Marked described in virtual coil at the beginning and end of the reading DQS signal of end-receiver output), with jagged reading DQS signal meeting
Cause the data receiver (i.e. DDR PHY reads error in data) of mistake.Therefore to the reading of the front-end receiver output of DDR PHY
DQS signal carries out door gating training and is necessary, and can find suitable reading DQS signal door strobe window by searching algorithm
(DQS Gate Enable Window, as shown in Figure 2), thus filter read DQS signal at the beginning and end of burr, obtain
The reading DQS signal clean to one, then data DQ is sampled with clean reading DQS signal, it is correctly read to obtain
Data.Carrying out gated search to the reading DQS signal after the output of DDR PHY front-end receiver by searching algorithm (is not direct
Reading DQS waveform in bus is scanned for), enable DDR PHY that the data that DRAM is sent are correctly received.
It please refers to shown in Fig. 3, traditional reading DQS signal door gates training method, includes the following steps：
Firstly, it is BL/2 (BL that a Training Control device, which can generate a width,:Burst-length refers to the length of a reading and writing data
Degree, the burst-length of legend are equal to the door strobe window (not shown) of 8) a clock cycle, this strobe window is opposite to read DQS letter
It is number to the left；
Then, it controls the door strobe window and moves to right a step by a step and (from left to right postpone this gating step by step
Window), until finding left margin (as shown in the reading DQS signal door strobe window left margin in Fig. 3)；
Then, it controls the door strobe window continuation and moves to right a step by a step and (from left to right postpone the door step by step
Strobe window), until finding the right margin of the door strobe window (such as the reading DQS signal door strobe window right margin institute in Fig. 3
Show)；
Finally, asking a mean place to gate to get door to the end the result of the left margin and the right margin
The position of window (as shown in the position of the last reading DQS signal door strobe window in Fig. 3).
The above method, with reading the place Preamble (preamble) that DQS signal starts and the Postamble (postorder) terminated
Side, the effective timing allowance for (i.e. correctly) reading DQS signal of door strobe window distance is respectively 0.25T (when T is one
The clock period).When the speed of service of DDR system is further promoted, it is contemplated that voltage noise, variation of ambient temperature and signal are anti-
Equal non-ideal factors are penetrated, the timing allowance of 0.25T is simultaneously inadequate, this needs a kind of new method just to promote determining reading DQS
The timing allowance of the door strobe window of signal, to lay better basis for the stable work of DDR system.
Summary of the invention
The purpose of the present invention is to provide a kind of reading DQS signal door gating training method, device and systems, can be improved
Read the timing allowance of DQS signal door gating training result, the stability of enhancing system work.
To achieve the goals above, the present invention provides a kind of reading DQS signal door gating training method, includes the following steps：
The enabled letter of door gating for the clock period wide that a width is BL/2-1 reading DQS signal is generated according to a read request
Number, the BL is burst-length；
It controls the door gating enable signal to move from left to right relative to the reading DQS signal, until door gating makes
Door gating enabled letter of the failing edge of energy signal just beyond the second-to-last rising edge for reading DQS signal, after being moved
Number；
Door gating enable signal after postponing the movement gates enable signal with the door after being postponed, after the delay
Door gating enable signal rising edge and first rising edge for reading DQS signal between spacing not less than 0.25*T
Clock cycle；
Using the position of the rising edge of the door gating enable signal after the delay as door strobe window starting position, by institute
End position of the position for reading the last one failing edge of DQS signal as door strobe window is stated, obtains the reading DQS signal most
Whole door strobe window.
Optionally, the enabled letter of door gating after the door after being moved gates enable signal, and after being postponed
Before number, the reading DQS signal door gating training method further includes：By the rising edge of the door gating enable signal after the movement
As the starting position of initial gate strobe window, using the position of the last one failing edge for reading DQS signal as described first
The end position of beginning door strobe window, to obtain initial gate strobe window.
Optionally, before or after postponing the door gating enable signal after the movement, by detecting the reading automatically
The last one rising edge and failing edge of DQS signal come determine it is described read DQS signal the last one failing edge position.
Optionally, the failing edge of the door gating enable signal after the delay does not lag behind the last of the reading DQS signal
One rising edge is not ahead of the penultimate rising edge for reading DQS signal.
Optionally, the door gating enable signal after the movement is postponed into 0.5 clock cycle, to obtain maximum timing
Allowance.
The present invention also provides a kind of reading DQS signal doors to gate training device, including：
Training Control device, it is wide for generating the clock cycle that a width is BL/2-1 reading DQS signal according to a read request
The door of degree gates enable signal, and control the door gating enable signal moved from left to right relative to the readings DQS signal up to
The failing edge of the door gating enable signal is just beyond the second-to-last rising edge for reading DQS signal, after being moved
Door gating enable signal, and, the door gating enable signal after postponing the movement enables letter with the door gating after being postponed
Number, the spacing between the rising edge and first rising edge for reading DQS signal of the door gating enable signal after the delay
Not less than 0.25*T clock cycle；
Self closing logic circuit, for detecting described the last one rising edge and failing edge for reading DQS signal, to obtain
The position for reading the last one failing edge of DQS signal is stated, and then the rising edge of the door gating enable signal after the delay is made
For the starting position of door strobe window, using the position of the last one failing edge for reading DQS signal as door strobe window
End position obtains the final door strobe window for reading DQS signal.
Optionally, the failing edge of the door gating enable signal after the delay does not lag behind the last of the reading DQS signal
One rising edge is not ahead of the penultimate rising edge for reading DQS signal.
Optionally, the Training Control device by after the movement door gating enable signal postpone 0.5 clock cycle with
Door after being postponed gates enable signal, the rising edge and the reading DQS signal of the door gating enable signal after the delay
First rising edge between spacing be 0.5*T reading DQS signal clock cycle, to obtain maximum timing allowance.
Optionally, the self closing logic circuit include a delay cell, first to third trigger, it is first anti-to third
Phase device and the first to the second logic gate, wherein first trigger and second trigger series connection, first triggering
The input terminal of device, the input terminal of the third trigger and clock end one identical logic-high signal of reception, described first
The input terminal of the clock end of trigger and first phase inverter receives the reading DQS signal, first phase inverter it is defeated
Outlet connects the clock end of second trigger, and the clear terminal of first trigger and second trigger is connected to
The output end of the delay cell, the input terminal of the delay cell connect the output end of first logic gate, and described second
The output end of trigger connects the input terminal of the second logic gate, and the output end of second logic gate is connected to the third triggering
The set end of device, the clear terminal of the third trigger connect the output end of second phase inverter, second phase inverter
Input terminal receives the gating enable signal of the door after the delay, and the output end of the third trigger connects the defeated of third phase inverter
Enter the input terminal of end and first logic gate, the output end of the third phase inverter exports the final of the reading DQS signal
Door strobe window.
Optionally, described first to third trigger be D class trigger；First logic gate be three input terminals,
The nor gate of one output end, after two input terminals of first logic gate receive a reset signal and the delay respectively
Door gating enable signal；Second logic gate is the nor gate of two input terminals, output end, second logic gate
Another input terminal receives the reset signal.
Optionally, reading DQS signal door gating training device is applied in ddr interface circuit, the Training Control
Device is a part of the controller in the ddr interface circuit, and the self closing logic circuit is arranged in the ddr interface circuit
In physical layer on.
The present invention also provides a kind of data transmission systems, which is characterized in that gates instruction including reading DQS signal door of the invention
Practice device and for sending the memory grain for reading DQS signal to the reading DQS signal door gating training device.
Optionally, the data transmission system is DDR system, and the reading DQS signal door gating training device is applied
In ddr interface circuit, the Training Control device is a part of the controller in the ddr interface circuit, and the self closing is patrolled
It collects circuit to be arranged in the physical layer in the ddr interface circuit, passes through system between the memory grain and the physical layer
Bus connection.
Compared with prior art, technical solution of the present invention, first generating a width based on a read request is BL/2-1 reading
The door of the clock period wide of DQS signal gates enable signal, then controls the relatively described reading DQS letter of the door gating enable signal
It number moves from left to right until the failing edge of door gating enable signal is just beyond the second-to-last for reading DQS signal
Rising edge, the door after being moved gate enable signal；Then the door gating enable signal after postponing the movement is to be prolonged
The rising edge of the door gating enable signal to lag, the door gating enable signal after the delay reads the first of DQS signal with described
Spacing between a rising edge is not less than 0.25*T clock cycle；Again by the rising of the door gating enable signal after the delay
Along the starting position as door strobe window, using the position of the last one failing edge for reading DQS signal as door gating window
The end position of mouth can make the final door gating window for reading DQS signal to obtain the final door strobe window for reading DQS signal
Mouth has the allowance greater than 0.25 clock cycle in the position Preamble for the beginning for reading DQS signal, while reading DQS signal knot
Also there is the allowance greater than 0.25 clock cycle in the place of beam, therefore, compared to traditional method, improves and reads the choosing of DQS signal door
The timing allowance of logical training result has laid better basis for the stable work of system.
Detailed description of the invention
Fig. 1 is a kind of modular structure schematic diagram of DDR system；
Fig. 2 is timing diagram when DDR system shown in FIG. 1 carries out read operation；
Fig. 3 is a kind of signal waveforms read in DQS signal door gating training method；
Fig. 4 is the flow chart for reading DQS signal door gating training method of the specific embodiment of the invention；
Fig. 5 is the signal waveforms of the specific embodiment of the invention read in DQS signal door gating training method；
Fig. 6 is the modular structure schematic diagram for reading DQS signal door gating training device of the specific embodiment of the invention；
Fig. 7 is the structural schematic diagram of the self closing logic circuit of the specific embodiment of the invention；
Fig. 8 is the control sequential figure of the self closing logic circuit of the specific embodiment of the invention.
Specific embodiment
To be clearer and more comprehensible the purpose of the present invention, feature, a specific embodiment of the invention is made with reference to the accompanying drawing
Further instruction, however, the present invention can be realized with different forms, it should not be to be confined to the embodiment described.
Referring to FIG. 4, the present invention provides a kind of reading DQS signal door gating training method, include the following steps：
S1, the door gating for generating the clock period wide that a width is BL/2-1 reading DQS signal according to a read request make
Energy signal, BL is burst-length；
S2 controls the door gating enable signal and moves from left to right relative to the reading DQS signal, until the door gates
For the failing edge of enable signal just beyond the second-to-last rising edge for reading DQS signal, the door gating after being moved is enabled
Signal；
S3, the door gating enable signal after postponing the movement gates enable signal with the door after being postponed, described to prolong
Spacing between the rising edge and first rising edge for reading DQS signal of the door gating enable signal to lag is not less than
0.25*T clock cycle；
S4, using the position of the rising edge of the door gating enable signal after the delay as door strobe window starting position,
Using the position for reading the last one failing edge of DQS signal as the end position of door strobe window, the reading DQS signal is obtained
Final door strobe window.
Fig. 1, Fig. 5 and Fig. 6 are please referred to, when needing to be read out the data in DRAM, it will usually first initiate a reading
Request so that DRAM receive the corresponding read request comprising the information including order CMD and address AD DR, DRAM root
Data-signal DQ and reading DQS signal (ideally letter are sent to the front-end receiver of DDR PHY is synchronous according to the information
Number as shown in the ideal DQS in Fig. 5, but under real conditions, low level is transformed into and from low reading DQS signal from High-Z
When level conversion is to High-Z, which will receive the influence of parasitic inductance capacitor in transmission channel etc. and generates burr, such as
Shown in true DQS in Fig. 5), the reading DQS signal of the front-end receiver output of DDR PHY also can be with jagged, easy production at this time
Raw data read errors, therefore in order to avoid reading error in data, the reading DQS that the front-end receiver of DDR PHY exports need to be believed
Number carry out door gating training.Carry out the reading DQS signal door that the present invention will be described in detail below with reference to Fig. 4, Fig. 5 and Fig. 6 and gates training side
Method, specifically, first in step sl, it is (BL/2-1) a reading that Training Control device 11, which generates a width according to the read request,
The door gating enable signal (DQS Gate Enable Signal, not shown) of DQS signal clock period wide, wherein BL is prominent
Length is sent out, refers to the length of a reading and writing data, the burst-length in Fig. 5 is equal to 8, and reading DQS signal is DDR PHY front end receiver
The reading DQS signal of device output, therefore the door gating enable signal generated is 3 reading DQS signal clock period wides, substantially
It is a door strobe window；Then, in step s 2, firstly, the control door gating enable signal of Training Control device 11 is past from a left side
It moves right, the searching algorithm in moving process in Training Control device 11 can data-signal (DQ) whether correct (one based on the received
As be whether consistent by comparing the data of Writing/Reading) judge whether the position of current door gating enable signal correct, until
The failing edge of door gating enable signal after movement obtains just just beyond the penultimate rising edge for reading DQS signal
Door after true movement gates enable signal, as shown in the position 1 of Fig. 5；After each mobile door gating enable signal, it will move
Starting position of the rising edge of door gating enable signal afterwards as current initial gate strobe window, and pass through a self closing
(Self-close circuit) logic circuit 12 starts detection and reads the last one rising edge of DQS signal and failing edge, works as detection
When to a last failing edge (end position as current initial gate strobe window), the closing of self closing logic circuit 12 is worked as
Preceding initial gate strobe window has obtained current initial gate strobe window, as shown in the position 2 of Fig. 5, the current initial gate
Whether the position that strobe window is used to detect the door gating enable signal after this movement is correct, specifically, at the beginning of current
Beginning door strobe window gates reading DQS signal, and so as to receive corresponding data-signal DQ, (door gating after movement makes
Can signal position it is correct when can receive data D0~D7), searching algorithm in Training Control device 11 data based on the received
Whether correctly judge whether the position (i.e. position 1) of the door gating enable signal after this movement is correct, when incorrect,
Continue to control door gating enable signal movement, until the failing edge of door gating enable signal is believed just beyond the reading DQS
Number penultimate rising edge, after having looked for correct movement at this time door gating enable signal position (i.e. position in Fig. 5
Shown in 1)；Then, in step s3, door of the Training Control device 11 after step S2 is mobile gates enable signal (the i.e. position of Fig. 5
1) delay gate gates half of enable signal reading DQS signal clock cycle (i.e. 0.5*T) and arrives to the position of Fig. 53 on the basis of
Door after delay gates enable signal；Then, in step s 4, start detection again by self closing logic circuit 12 and read DQS
The last one rising edge of signal and failing edge, when detecting the last one failing edge, self closing logic circuit 12 closes door choosing
Logical window has obtained the final door strobe window (i.e. last door gating training result) as shown in the position 4 of Fig. 5, it is opened
Beginning position (i.e. start time) is exactly that the starting position of the door gating enable signal after postponing shown in the position 3 of Fig. 5 (starts
Moment, or finally the leading edge position of door strobe window is the leading edge position of the door gating enable signal after delay), it
End position (i.e. finish time) be to be controlled by self closing logic circuit 12, always it is described read DQS signal last
It is closed when a failing edge, i.e., failing edge position, that is, the last one failing edge for reading DQS signal of final door strobe window
Position.
It can be seen that the reading DQS signal door of the present embodiment gates training method, the final door gating for reading DQS signal can be made
There is the timing allowance of 0.5*T in the position for the Preamble (preamble) that window starts at it, is 2 times of training method shown in Fig. 3；
Judge that the condition of timing allowance becomes only because controlling using self closing in the place that the reading DQS signal terminates simultaneously
Want shown in the position 3 in Fig. 5 postpone after door gating enable signal failing edge do not lag behind the reading DQS signal last
A rising edge is not ahead of the reading DQS signal penultimate rising edge, then the self closing logic circuit can be correct
Work, particularly, as previously mentioned, the door after delay gates enable signal when the door after delay is mobile gates enable signal 0.5*T
Falling edge in it is described read DQS signal the last one rising edge and penultimate rising edge middle position, can get
It is up to the timing allowance of 0.5*T, is 2 times of training method shown in Fig. 3.From the above analysis, method of the invention can
To greatly improve the timing allowance for reading DQS signal door gating training result, better base has been laid for the stable work of DDR system
Plinth.
It should be noted that prolonging in above-described embodiment to door gating enable signal (i.e. position 1 in Fig. 5) after the movement
Slow 0.5*T can obtain the timing allowance of 0.5*T in the place of the beginning and end of last door strobe window, for the present invention
The optimum embodiment of technical solution, but in the other embodiment of the present invention, if the requirement to timing allowance is not too high, such as
The timing allowance that can permit the place of the beginning and end of last door strobe window can be unequal, then in step s3,
As long as the time for postponing the gating enable signal of the door after the movement enables to the rising of the door gating enable signal after delay
It is greater than 0.25*T along the timing allowance between first rising edge of reading DQS signal, and the door gating after the delay is enabled
The failing edge of signal does not lag behind the last one rising edge of the reading DQS signal or is not ahead of the reading DQS signal inverse
Second rising edge, so that it may meet the requirements, such as 0.25 or 0.6 reading DQS signal clock cycle of delay.In addition, in this hair
In bright other embodiments, those skilled in the art are not restricted to borrow to the whether correct judgment method in position 1 in Fig. 5
Help initial gate strobe window of the invention (i.e. initial position be it is mobile after door gating enable signal rising edge, end position
For read DQS signal the last one failing edge door strobe window) judged, can also directly be selected using the door after mobile
For logical enable signal as current door strobe window, searching algorithm in Training Control device 11 can data-signal based on the received
(DQ) whether correct (such as whether consistent with preceding partial data D0~D3 for writing in data by comparing received data)
Whether correct (the enabled letter of door gating after determining current movement in position to judge the gating enable signal of the door after current movement
Number failing edge whether just beyond it is described read DQS signal penultimate rising edge), it can be seen that, in above-described embodiment
The step of obtaining initial gate strobe window also can be omitted, i.e., only complete delay it is mobile after door gate enable signal, just into
Row reads the detection of the last one rising edge and failing edge of DQS signal.
Referring to FIG. 6, the present invention also provides a kind of reading DQS signal doors to gate training device, including 11 He of Training Control device
Self closing logic circuit 12, Training Control device 11 and self closing logic circuit 12, which receive, reads DQS signal, and Training Control device 11
Output end connection self closing logic circuit 12 an input terminal.
The Training Control device 11 is used to generate a width according to a read request (i.e. the corresponding read request of reading DQS signal)
The door of the clock period wide of BL/2-1 reading DQS signal gates enable signal, and it is opposite to control the door gating enable signal
The DQS signal of reading is moved from left to right until the failing edge of door gating enable signal is just beyond the reading DQS signal
Second-to-last rising edge, door after being moved gates enable signal, and, the door gating after postponing the movement is enabled
Signal gates enable signal with the door after being postponed, the rising edge of the door gating enable signal after the delay and the reading
Spacing between first rising edge of DQS signal is not less than 0.25*T clock cycle, and the door gating after the delay is enabled
The failing edge of signal does not lag behind described the last one rising edge for reading DQS signal or is not ahead of the reading DQS signal
Penultimate rising edge, such as Training Control device 11 postpone the gating 0.5 reading DQS signal of enable signal of the door after the movement
Clock cycle (i.e. 0.5*T).The Training Control device 11 is also used to the door gating enable signal after the delay being sent to institute
State self closing logic circuit 12.
The self closing logic circuit 12 is used to detect described the last one rising edge and failing edge for reading DQS signal, with
Obtain it is described read DQS signal the last one failing edge position, and then using after the delay door gating enable signal as
The starting position of door strobe window, using the position of the last one failing edge for reading DQS signal as the knot of door strobe window
Beam position obtains the final door strobe window for reading DQS signal.In the present embodiment, referring to FIG. 7, the self closing logic
Circuit 12 include a delay cell 120, first to third trigger DFF0~DFF2, first to third phase inverter U1~U3 and
The first to the second logic gate G1~G2, wherein first to third trigger DFF0~DFF2 is D class trigger, and described first
Logic gate is the nor gate (NOR) of three input terminals, output end, second logic gate be two input terminals, one it is defeated
The nor gate (NOR) of outlet；The first trigger DFF0 and the second trigger DFF1 series connection (i.e. the first trigger DFF0
Output end connect the input terminal D of the second trigger DFF1), the input terminal (D) of the first trigger DFF0, third touching
The input terminal (D) and clock end (CP) for sending out device DFF2 receive an identical logic-high signal tie_hi (i.e. level for " 1) ",
It is corresponding that the input terminal of the clock end (CP) of the first trigger DFF0 and the first phase inverter U1 receive the read request
Reading DQS signal (substantially DDR PHY front-end receiver output after reading DQS signal, converted via bus level at this time
For the digital logic level inside circuit, unless otherwise stated, the door gating training of pair reading DQS signal described in the present embodiment is
Refer to and the training of door gating carried out to the reading DQS signal after the output of DDR PHY front-end receiver), the output of the first phase inverter U1
The clock end (CP) of end connection the second trigger DFF1, the first trigger DFF0 and the second trigger DFF1's
Clear terminal (CDN) is connected to the output end of the delay cell 120, the input terminal connection of the delay cell 120 described the
The output end of one logic gate G1, the output end (Q) of the second trigger DFF1 connect an input terminal of the second logic gate G2,
Another input terminal of second logic gate receives reset signal rst, and the output end of the second logic gate G2 is connected to institute
The set end (SDN) of third trigger DFF2 is stated, the clear terminal (CDN) of the third trigger DFF2 connects second reverse phase
The output end of device U2, the input terminal of the second phase inverter U2 receive the door gating after the delay that the Training Control device 11 conveys
The input terminal of output end (Q) the connection third phase inverter U3 of enable signal dqsg_en_i, the third trigger DFF2 and institute
An input terminal of the first logic gate G1 is stated, after other two input terminal of the first logic gate G1 receives the delay respectively
Door gate the enable signal dqsg_en_i and reset signal rst, the third phase inverter U3 output end output described in
Read the final door strobe window dqsg_en_o of DQS signal.Second logic gate G2 is used to set 1 letter to third trigger DFF2 offer
Number dqs_sdn, delay cell 120 are used to provide reset signal cdn, third to the first trigger DFF0 and the second trigger DFF1
Trigger DFF2 is used to provide input signal dqs_falling, the first logic gate to the first logic gate G1 and third phase inverter U3
G1 is used to provide to delay cell 120, and the second phase inverter U2 is used to provide reset signal dqs_cdn to third trigger DFF2.
First trigger DFF0 and the second trigger DFF1 is used to detect the last one rising edge for reading DQS signal and the last one decline
Edge, third trigger DFF2 has clear 0 control and sets 1 control, when reset signal dqs_cdn is 0, third trigger DFF2's
Output end (Q) is low level 0, and when setting 1 signal dqs_sdn is 0, the output end (Q) of third trigger DFF2 is high level 1.
Fig. 8 is the control sequential figure of self closing logic circuit 12 shown in Fig. 7, in conjunction with the timing of each signal in the figure, it can be seen that
Self closing logic circuit is how to detect to read the last one rising edge of DQS signal and failing edge, and close a strobe window,
Wherein dqsg_en_i is that the door gating enable signal after the delay that Training Control device 11 is sent (delays 0.5*T clock week
Phase), output signal dqsg_en_o is the final door strobe window for reading DQS signal, specifically, when dqsg_en_i is by low change
When high (being in leading edge position), it is 0 (i.e. leading edge position), third trigger that reset signal dqs_cdn, which is by 1 jump,
DFF2 output signal dqs_falling becomes 0, and the output signal of third phase inverter U3 becomes 1 at this time, for opening for door strobe window
Begin moment (obtaining a rising edge of strobe window dqsg_en_o), and keeps the time width of high level in dqsg_en_i
Interior, reset signal dqs_cdn remains zero, and reset signal rst remains zero, and the cdn signal of generation remains zero, third triggering
The output signal dqs_falling of device DDF2 remains zero；And when dqsg_en_i is 0 (i.e. failing edge position) by 1 jump,
Reset signal dqs_cdn becomes 1, since dqs_falling, rst signal are also 0, the letter of the first logic gate G1 output
Number become 1 from 0, i.e. cdn becomes 1, and the first trigger DFF0 and the second trigger DFF1 detection are read in the last one of DQS signal
It rises edge and failing edge and 1 signal is exported by the second trigger DFF1, what the second logic gate G2 was exported at this time sets 1 signal dqs_sdn
Become 0, and then the output signal dqs_falling of third trigger DFF2 is caused to become 1 from 0, third phase inverter U3 output
Signal becomes low level (0) from high level (1), gates at this time for the finish time of door strobe window dqsg_en_o to get to door
The signal of the failing edge of window dqsg_en_o, the first logic gate G1 output correspondingly becomes 0 from 1 again, accordingly, by delay
The cdn signal of the delay output of unit 120 is also 0 by 1 jump, so that the output of the first trigger DFF0 and the second trigger DFF1
It is cleared, set 1 signal dqs_sdn becomes 1 again.
Reading DQS signal door of the invention gates training device, can be realized the automatic instruction for reading DQS signal door strobe window
Practice, and the door strobe window of timing allowance larger (for example, 0.5*T) can be obtained, the stability of system work can be enhanced,
Avoid the non-ideal factors bring read operation mistake such as voltage noise, variation of ambient temperature and signal reflex, reading of the invention
DQS signal door gating training device can be applied in ddr interface circuit, referring to FIG. 1, the Training Control device 11 is described
A part of controller DDRC in ddr interface circuit, the self closing logic circuit 12 can be set in the ddr interface electricity
In physical layer (DDR PHY) in road.
The present invention also provides a kind of data transmission systems as a result, gate training device including reading DQS signal door of the invention
And for sending the memory grain for reading DQS signal to the reading DQS signal door gating training device.Fig. 1 and Fig. 6 are please referred to,
The data transmission system can be DDR system, and the reading DQS signal door gating training device is applied in ddr interface circuit
In, the Training Control device 11 is a part of the controller of the ddr interface, and the self closing logic circuit 12 is arranged in institute
It states in the physical layer (DDR PHY) in ddr interface circuit, the memory grain can be DRAM, can be with the ddr interface electricity
It is connected between physical layer DDR PHY in road by system bus, the system bus mainly includes being used for transmission clock signal
The route of CLK, the route for being used for transmission command signal CMD and address signal ADDR, be used for transmission the route of data-signal DQ with
And it is used for transmission the route for reading DQS signal.Data transmission system of the invention, due to using reading DQS signal door of the invention
Training device is gated, therefore job stability is improved.
Obviously, those skilled in the art can carry out various modification and variations without departing from spirit of the invention to invention
And range.If in this way, these modifications and changes of the present invention belong to the claims in the present invention and its equivalent technologies range it
Interior, then the present invention is also intended to include these modifications and variations.
Claims (13)
1. a kind of reading DQS signal door gates training method, which is characterized in that include the following steps：
The door for generating the clock period wide that a width is BL/2-1 reading DQS signal according to a read request gates enable signal,
BL is burst-length；
It controls the door gating enable signal to move from left to right relative to the reading DQS signal, until the door gates enabled letter
Number failing edge just beyond it is described read DQS signal second-to-last rising edge, after move door gating enable signal；
Door gating enable signal after postponing the movement gates enable signal with the door after being postponed, the door after the delay
The spacing gated between the rising edge of enable signal and first rising edge for reading DQS signal is not less than 0.25*T clock
Period；
Using the position of the rising edge of the door gating enable signal after the delay as door strobe window starting position, by the reading
End position of the position of the last one failing edge of DQS signal as door strobe window obtains the final door for reading DQS signal
Strobe window.
2. reading DQS signal door as described in claim 1 gates training method, which is characterized in that the door choosing after being moved
After logical enable signal, and before the door after being postponed gates enable signal, the reading DQS signal door gates training method
Further include：Using the rising edge of the door gating enable signal after the movement as the starting position of initial gate strobe window, by institute
End position of the position for reading the last one failing edge of DQS signal as the initial gate strobe window is stated, it is initial to obtain
Door strobe window.
3. reading DQS signal door as claimed in claim 1 or 2 gates training method, which is characterized in that described by detecting automatically
The last one rising edge and the failing edge of DQS signal are read to determine the position of the last one failing edge for reading DQS signal.
4. reading DQS signal door as described in claim 1 gates training method, which is characterized in that the door gating after the delay
The failing edge of enable signal does not lag behind described the last one rising edge for reading DQS signal or is not ahead of the reading DQS letter
Number penultimate rising edge.
5. reading DQS signal door as described in claim 1 gates training method, which is characterized in that select the door after the movement
Logical enable signal postpones 0.5 clock cycle, to obtain maximum timing allowance.
6. a kind of reading DQS signal door gates training device, which is characterized in that including：
Training Control device, for generating the clock period wide that a width is BL/2-1 reading DQS signal according to a read request
Door gating enable signal, and it is mobile from left to right until described relative to the reading DQS signal to control the door gating enable signal
Door choosing of the failing edge of door gating enable signal just beyond the second-to-last rising edge for reading DQS signal, after being moved
Logical enable signal, and, the door gating enable signal after postponing the movement gates enable signal, institute with the door after being postponed
Spacing between the rising edge and first rising edge for reading DQS signal of door gating enable signal after stating delay is not less than
0.25*T clock cycle；
Self closing logic circuit, for detecting described the last one rising edge and failing edge for reading DQS signal, to obtain the reading
The position of the last one failing edge of DQS signal, and then using the rising edge of the door gating enable signal after the delay as door
The starting position of strobe window, using the position of the last one failing edge for reading DQS signal as the end of door strobe window
Position obtains the final door strobe window for reading DQS signal.
7. reading DQS signal door as claimed in claim 6 gates training device, which is characterized in that the door gating after the delay
The failing edge of enable signal does not lag behind described the last one rising edge for reading DQS signal or is not ahead of the reading DQS letter
Number penultimate rising edge.
8. reading DQS signal door as claimed in claim 6 gates training device, which is characterized in that the Training Control device is by institute
Door gating enable signal after stating movement postpones 0.5 clock cycle and gates enable signal with the door after being postponed, described to prolong
Spacing between the rising edge and first rising edge for reading DQS signal of the door gating enable signal to lag is 0.5*T
The DQS signal clock cycle is read, to obtain maximum timing allowance.
9. reading DQS signal door as claimed in claim 6 gates training device, which is characterized in that the self closing logic circuit
Including a delay cell, first to third trigger, first to third phase inverter and the first to the second nor gate, wherein institute
State the first trigger and second trigger series connection, the input of the input terminal of first trigger, the third trigger
End and clock end receive an identical logic-high signal, the clock end of first trigger and first phase inverter
Input terminal receive and read DQS signal, the output end of first phase inverter connects the clock end of second trigger, described the
The clear terminal of one trigger and second trigger is connected to the output end of the delay cell, the delay cell it is defeated
Entering the output end that end connects first nor gate, the output end of second trigger connects the input terminal of the second nor gate,
The output end of second logic gate is connected to the set end of the third trigger, the clear terminal connection of the third trigger
The output end of second phase inverter, the input terminal of second phase inverter receive the gating enable signal of the door after the delay,
The input terminal of the output end connection third phase inverter of the third trigger and the input terminal of first nor gate, described the
The output end of three phase inverters exports the final door strobe window for reading DQS signal.
10. reading DQS signal door as claimed in claim 9 gates training device, which is characterized in that described first to third triggers
Device is D class trigger；First logic gate is the nor gate of three input terminals, output end, first logic gate
Two input terminals receive respectively the door after a reset signal and the delay gating enable signal；Second logic gate is two
Another input terminal of the nor gate of a input terminal, output end, second logic gate receives the reset signal.
11. the reading DQS signal door as described in any one of claim 6 to 10 gates training device, which is characterized in that described
It reads DQS signal door gating training device to apply in ddr interface circuit, the Training Control device is in the ddr interface circuit
Controller a part, the self closing logic circuit is arranged in the physical layer in the ddr interface circuit.
12. a kind of data transmission system, which is characterized in that including reading DQS signal door described in any one of claim 6 to 11
Gate training device and for sending the memory grain for reading DQS signal to the reading DQS signal door gating training device.
13. data transmission system as claimed in claim 12, which is characterized in that the data transmission system is DDR system, institute
The reading DQS signal door gating training device stated is applied in ddr interface circuit, and the Training Control device is the ddr interface electricity
A part of controller in road, the self closing logic circuit is arranged in the physical layer in the ddr interface circuit, described
It is connected between memory grain and the physical layer by system bus.
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