CN108897706A - Accelerator interface - Google Patents

Abstract

The invention relates to an accelerator interface, which solves the technical problems of low applicability, low transmission rate and high delay, and is connected between a server and an accelerator by adopting the accelerator interface; the accelerator interface is a DDR interface which comprises a DDR storage module and a high-speed selector switch for controlling the sharing or disconnection of DDR memory units, the accelerator interface adopts the technical scheme that DDR addresses and command signal sequences are adopted to complete data communication between a server and an accelerator, the problem is solved well, and the accelerator interface can be used for connecting the accelerator and the server or the server.

Description

A kind of accelerator interfaces

Technical field

The present invention relates to accelerator fields, and in particular to a kind of accelerator interfaces.

Background technique

Artificial intelligence needs to carry out machine learning, is quickly calculated with intelligent algorithm.General purpose computer is difficult to meet, and needs Various types of accelerators.Accelerator requires have high transmission rates and low-latency.Graphics processor（Graphics Processing Unit, abbreviation GPU）And field programmable gate array（Field-Programmable Gate Array, letter Claim FPGA）It is most important algorithm accelerator.

The interface that current above-mentioned accelerator and server use is bus interface PCI express, bus interface PCI The maximum bandwidth of express is 16MB/s.Also, the PCI express of high bandwidth is generally used at high-end server central Manage device（Central Processing Unit, abbreviation CPU）.Therefore, there are high performance accelerators for existing accelerator interfaces Interface suitability is poor, and that there are transmission rates is low, postpones high technical problem.Therefore it provides one kind can be adapted to extensively it is various The high-performance accelerator interfaces of server and server are with regard to necessary.

Summary of the invention

The technical problem to be solved by the present invention is to applicability existing in the prior art is low, transmission rate is low, and delay is high The technical issues of.A kind of new accelerator interfaces are provided, which has applicability wide, and transmission rate is high, postpones low The characteristics of.

In order to solve the above technical problems, the technical solutions adopted are as follows：

A kind of accelerator interfaces, the accelerator interfaces are connected between server and accelerator；The accelerator interfaces are DDR Interface, ddr interface include DDR memory module, and the high speed COMS bus exchange switch that control DDR internal storage location is shared or disconnected, described Accelerator interfaces complete the data communication of server and accelerator using the address DDR and command signal sequence.

In above scheme, for optimization, further, the circuit that switches at high speed is high-speed analog switch.

Further, the DDR internal storage location is dynamic random access memory or dual inline memory module.

Further, the capacity of the dynamic random access memory is 4GB-8GB.

Further, the data communication of the server and accelerator is both-way communication, the memory size of DDR internal storage location For the communal space.

Further, the DDR internal storage location is shared need to execute the following steps：

Step 1, server executes acceleration task, and task data is written；

Step 2, Acceleration of starting device interface, accelerator knot carry out the confirmation of State tracking logic commands match, fit through, execute Step 3, it fails to match then repeats step 2；

Step 3, idle DDR internal storage location switching is waited；

Step 4, switch Accelerator control DDR internal storage location；

Step 5, acceleration task is handled；

Step 6, switching server controls DDR internal storage location, and server real-time query accelerates task status, and task status is not complete Cheng Ze returns to step 2, and task status is shared to complete then to terminate DDR internal storage location.

Further, the State tracking logic commands match, which confirms, includes：

Step A, DDR internal storage location reads the order of column address strobe time delay, tracking mode；

Step B is tracked and is successfully then executed output matching confirmation instruction；

Step C, tracking are completed, and column address strobe time delay command parameter is restored, and execute State tracking logic next time Commands match.

Beneficial effects of the present invention：

Effect one, the present invention is used between the ddr interface access server and accelerator of high bandwidth, and realizes ddr interface Memory sharing, provide more high bandwidth, the lower accelerator interfaces of delay；It can provide 64 DDR4 SODIMM, 26.6GB/ S), delay time also reducible 10 times of reduction；

Effect two, ddr interface exist in all universal cpus, and applicability than before only deposit by high performance accelerator interfaces It is more powerful in high-performance CPU.

Detailed description of the invention

Present invention will be further explained below with reference to the attached drawings and examples.

Fig. 1, the connection schematic diagram of accelerator interfaces.

Fig. 2, order tracking and reception schematic diagram.

Fig. 3, DDR internal storage location share schematic diagram.

The interface diagram of Fig. 4, DDR4.

Specific embodiment

In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to embodiments, to the present invention It is further elaborated.It should be appreciated that described herein, specific examples are only used to explain the present invention, is not used to limit The fixed present invention.

Embodiment 1

The present embodiment provides a kind of accelerator interfaces, such as Fig. 1, the accelerator interfaces are connected between server and accelerator； The accelerator interfaces are ddr interface, and ddr interface includes DDR memory module, and control DDR internal storage location is shared or disconnects High speed COMS bus exchange switch, the accelerator interfaces complete the number of server and accelerator using the address DDR and command signal sequence According to communication.

The accelerator of the present embodiment uses FPGA, the alternative DRAM of DDR internal storage location.Remaining is similar to the present embodiment, no longer Description.DDR3 or DDR4 can be used in ddr interface.

Since ddr interface does not interrupt interaction mechanism, the present embodiment uses the address DDR, command signal special sequence It does server to communicate with accelerator, this special sequence is the unique sequences and original using the CAS LATENCY setting in MR0 There is the normal work of DRAM not conflict, the setting of original CAS LATENCY can be restored to after the sequence ends.Utilize LOAD It is as follows that accelerator switching start command is done in order：

DDR3：MR0[6：4] [2] CAS Latency sequence：5,14,6,13,9.

DDR4：MR0 [12] [6] [4] [2] CAS Latency sequence：10,32,12,30,24.

In addition, the clock of server and accelerator can not be completely the same, therefore, switching time will meet DDR3/DDR4 Code requirement.

Wherein, the circuit that switches at high speed is high-speed analog switch.The parameter of high-speed analog switch is primarily upon high speed mould The switch speed of quasi- switch.Very quickly, the present embodiment is using SGM4717 high speed for the switch speed of existing analog switch Dual-channel analog switch.

In detail, the DDR internal storage location is dynamic random access memory or dual inline memory module.

Wherein, the dynamic random access memory, the i.e. capacity of DRAM are 4GB-8GB.

Wherein, the data communication of the server and accelerator is both-way communication, and the memory size of DDR internal storage location is total Enjoy space.

In addition, the DDR internal storage location is shared need to execute the following steps such as Fig. 3：

Step 1, server executes acceleration task, and task data is written；

Step 2, Acceleration of starting device interface, accelerator knot carry out the confirmation of State tracking logic commands match, fit through, execute Step 3, it fails to match then repeats step 2；

Step 3, idle DDR internal storage location switching is waited；

Step 4, switch Accelerator control DDR internal storage location；

Step 5, acceleration task is handled；

Step 6, switching server controls DDR internal storage location, and server real-time query accelerates task status, and task status is not complete Cheng Ze returns to step 2, and task status is shared to complete then to terminate DDR internal storage location.

Wherein, such as Fig. 2, the State tracking logic commands match, which confirms, includes：

Step A, DDR internal storage location reads the order of column address strobe time delay, and tracking mode successively tracks each state；

Step B is tracked and is successfully then executed output matching confirmation instruction；

Step C, tracking are completed, and column address strobe time delay command parameter is restored, and execute State tracking logic next time Commands match.

Wherein, the Interface status of DDR4 such as Fig. 4.

Although the illustrative specific embodiment of the present invention is described above, in order to the technology of the art Personnel are it will be appreciated that the present invention, but the present invention is not limited only to the range of specific embodiment, to the common skill of the art For art personnel, as long as long as various change the attached claims limit and determine spirit and scope of the invention in, one The innovation and creation using present inventive concept are cut in the column of protection.

Claims (7)

1. a kind of accelerator interfaces, it is characterised in that：The accelerator interfaces are connected between server and accelerator；It is described to add Fast device interface is ddr interface, and ddr interface includes DDR memory module, and the high speed that control DDR internal storage location is shared or disconnected Switching switch, the accelerator interfaces complete the data communication of server and accelerator using the address DDR and command signal sequence.

2. accelerator interfaces according to claim 1, it is characterised in that：The circuit that switches at high speed is opened for High Speed Analog It closes.

3. accelerator interfaces according to claim 1, it is characterised in that：The DDR internal storage location is dynamic randon access Memory or dual inline memory module.

4. accelerator interfaces according to claim 3, it is characterised in that：The capacity of the dynamic random access memory is 4GB-8GB。

5. accelerator interfaces according to claim 1, it is characterised in that：The data communication of the server and accelerator is Both-way communication, the memory size of DDR internal storage location are the communal space.

6. accelerator interfaces according to claim 1, it is characterised in that：The DDR internal storage location is shared need to execute it is following Step：

Step 1, server executes acceleration task, and task data is written；

Step 2, Acceleration of starting device interface, accelerator knot carry out the confirmation of State tracking logic commands match, fit through, execute Step 3, it fails to match then repeats step 2；

Step 3, idle DDR internal storage location switching is waited；

Step 4, switch Accelerator control DDR internal storage location；

Step 5, acceleration task is handled；

Step 6, switching server controls DDR internal storage location, and server real-time query accelerates task status, and task status is not complete Cheng Ze returns to step 2, and task status is shared to complete then to terminate DDR internal storage location.

7. accelerator interfaces according to claim 6, it is characterised in that：The State tracking logic commands match confirmation packet It includes：

Step A, DDR internal storage location reads the order of column address strobe time delay, tracking mode；

Step B is tracked and is successfully then executed output matching confirmation instruction；

Step C, tracking are completed, and column address strobe time delay command parameter is restored, and execute State tracking logic next time Commands match.