CN108897491A - A kind of quick Access Optimization method and system of isomery mixing memory - Google Patents
A kind of quick Access Optimization method and system of isomery mixing memory Download PDFInfo
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- CN108897491A CN108897491A CN201810541232.6A CN201810541232A CN108897491A CN 108897491 A CN108897491 A CN 108897491A CN 201810541232 A CN201810541232 A CN 201810541232A CN 108897491 A CN108897491 A CN 108897491A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0685—Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
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Abstract
The present invention relates to mixing memory techniques fields, provide a kind of quick Access Optimization method and system of isomery mixing memory, method includes：Processing is optimized to the command process expense of NVMe agreement；After the command process expense optimization processing to NVMe agreement, when ordering starting, command queue is polled using Endpoint；It is tested whether the arrival loaded using the tracking position content in poll reception buffer area to DRAM, the completion of the change characterization read command of the tracking position, to solve the problems, such as that the speed of NVM memory access and DRAM memory access is unmatched, it being capable of quick access on the isomery mixing memory platform based on NVM expansion system memory to NVM memory, raising system entirety memory access performance, to improve the performance of isomery mixing memory platform.
Description
Technical field
The invention belongs to mix memory techniques field more particularly to a kind of quick Access Optimization method of isomery mixing memory and
System.
Background technique
As big data, memory calculate the development and use of application, the demand to memory size and performance is increasing, but
The at high cost of dynamic random access memory (Dynamic Random Access Memory, DRAM) is in one of them influence
An important factor for depositing capacity extension.And nonvolatile storage (Non-volatile Memory, NVM) is used as a kind of novel medium,
With mechanical hard disk ratio, access speed is fast, the also concern increasingly by market of non-volatile characteristic.NVM Express is one
The expansible host of a enterprise and normal client end system exploitation for using PCI Express SSD controls chip interface
Standard.NVMe provides a whole set of relatively sufficiently complex data structure and transaction methods.It is submitted by multiple orders
Queue, order complete queue etc. and carry out order distribution and processing.Although the mechanism that NVMe is provided is fine, to mixing memory system
System needs pointedly to propose simplified, applicable agreement, and the interface of access is allowed adequately to use non-volatile memories
The advantages of device, plays superiority bandwidth to the greatest extent.
Currently, NVM is used as PCIE SSD or SAS SSD, main function is to replace mechanical hard disk.Use NVM pairs
Memory expansion uses NVMe agreement generally using PCIe bus is based on.NVM Express is one for using PCI
The expansible host of the enterprise of Express SSD and the exploitation of normal client end system controls chip interface standard.But NVMe
The mechanism of offer is not fully suitble to isomery mixing memory system, and complicated, relevance grade is not high, can not be adequately using non-easy
The advantages of property lost memory, superiority bandwidth is played to the greatest extent.Meanwhile the time of PCIe bus data packet switch is more than K word
Time needed for the data transmission of section, there are many unnecessary packet-switchings, cause to NVM memory access low efficiency.
Summary of the invention
The purpose of the present invention is to provide a kind of quick Access Optimization methods of isomery mixing memory, it is intended to solve the prior art
The problem of mechanism that middle NVMe is provided not fully is suitble to isomery mixing memory system, NVM memory access low efficiency.
The invention is realized in this way a kind of quick Access Optimization method of isomery mixing memory, the method includes following
Step：
Processing is optimized to the command process expense of NVMe agreement, wherein the command process expense of the NVMe agreement
The parsing of acquisition, order packet, the distribution of order packet including order and the transmission for completing order packet；
After the command process expense optimization processing to the NVMe agreement, when ordering starting, using Endpoint pairs
Command queue is polled；
It is tested whether the arrival loaded using the tracking position content in poll reception buffer area to DRAM, the tracking
The completion of the change characterization read command of position.
As an improvement scheme, the step of command process expense to NVMe agreement optimizes processing is specific
Include the following steps：
A dedicated command process unit is generated, the command process unit is used for the order in the NVMe agreement
Acquisition and complete order packet transmission flow carry out control execution；
A moderator is generated, the moderator is used for the distribution to the order packet in the NVMe agreement into arbitration.
As an improvement scheme, the method also includes following step：
Erasing order is added in I/O order, the erasing order is used for the control wiped flash and PCM, note
Record the erasing times to the different erasure locations of flash and PCM.
As an improvement scheme, it is described after the command process expense optimization processing to the NVMe agreement, work as life
When enabling starting, the step of being polled using Endpoint to command queue, specifically includes following step：
The time of PCIE transmission is estimated；
Fetching portion order first, and execute corresponding processing operation；
According to the PCIE transmission time estimated, control is while Next Command reaches into the Next Command
Processing.
As an improvement scheme, it is described using poll receive buffer area in tracking position content DRAM load is arrived
Up to whether tested the step of specifically include following step：
Several marker bits are set in receiving buffer area in advance；
Before order executes, host receiver buffer is written into pre-set marker bit；
Imperfect label in the reception buffer area is detected, judges whether order has executed completion.
Another object of the present invention is to provide a kind of quick Access Optimization system of isomery mixing memory, the system packets
It includes：
Protocol optimization processing module optimizes processing for the command process expense to NVMe agreement, wherein described
The command process expense of NVMe agreement includes the acquisition of order, the parsing of order packet, the distribution of order packet and completes order packet
It sends；
Endpoint poller module, for working as order after the command process expense optimization processing to the NVMe agreement
When starting, command queue is polled using Endpoint；
Track position poller module, arrival that the tracking position content for being received in buffer area using poll loads DRAM and
It is no to be tested, the completion of the change characterization read command of the tracking position.
As an improvement scheme, the protocol optimization processing module specifically includes：
Command process unit generation module, for generating a dedicated command process unit, the command process unit
Control execution is carried out for the acquisition to the order in the NVMe agreement and the transmission flow for completing order packet；
Moderator generation module, for generating a moderator, the moderator is used for the life in the NVMe agreement
Enable the distribution of packet into arbitration.
As an improvement scheme, the system also includes：
Erasing instruction adding module, for erasing order to be added in I/O order, the erasing order is used for flash
The control wiped with PCM records the erasing times to the different erasure locations of flash and PCM.
As an improvement scheme, the Endpoint poller module specifically includes：
Time estimates module, for estimating to the time that PCIE is transmitted；
Partial order processing module is used for fetching portion order first, and executes corresponding processing operation；
Next Command processing and control module, for according to the PCIE transmission time estimated, control to be arrived when Next Command
Up to while into the Next Command processing.
As an improvement scheme, tracking position poller module specifically includes：
Marker bit setup module, for setting several marker bits in receiving buffer area in advance；
Marker bit writing module, for before order executes, pre-set marker bit write-in host to be received buffering
Area；
Judgment module is detected, for detecting to the imperfect label in the reception buffer area, whether judges order
Completion is executed.
In embodiments of the present invention, processing is optimized to the command process expense of NVMe agreement, wherein the NVMe association
The command process expense of view includes the acquisition of order, the parsing of order packet, the distribution of order packet and the transmission for completing order packet；?
After the command process expense optimization processing of the NVMe agreement, when order starting when, using Endpoint to command queue into
Row poll；It is tested whether the arrival loaded using the tracking position content in poll reception buffer area to DRAM, the tracking
The completion of the change characterization read command of position, thus solve the problems, such as that the speed of NVM memory access and DRAM memory access is unmatched, it can be in base
In the quick access on the isomery mixing memory platform of NVM expansion system memory to NVM memory, the memory access of system entirety is improved
Can, to improve the performance of isomery mixing memory platform.
Detailed description of the invention
Fig. 1 is the implementation flow chart of the quick Access Optimization method of isomery mixing memory provided by the invention；
Fig. 2 is the implementation flow chart provided by the invention that processing is optimized to the command process expense of NVMe agreement；
Fig. 3 is provided by the invention after the command process expense optimization processing to the NVMe agreement, when order starts
When, command queue is polled using Endpoint implementation flow chart；
Whether Fig. 4 is the arrival that the tracking position content provided by the invention using in poll reception buffer area loads DRAM
The implementation flow chart tested；
Fig. 5 is the structural block diagram of the quick Access Optimization system of isomery mixing memory provided by the invention.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
Fig. 1 shows the implementation flow chart of the quick Access Optimization method of isomery mixing memory provided by the invention, specific
Include the following steps：
In step s101, processing is optimized to the command process expense of NVMe agreement, wherein the NVMe agreement
Command process expense includes the acquisition of order, the parsing of order packet, the distribution of order packet and the transmission for completing order packet.
In step s 102, it after the command process expense optimization processing to the NVMe agreement, when ordering starting, adopts
Command queue is polled with Endpoint.
In step s 103, it is carried out whether the arrival loaded using the tracking position content in poll reception buffer area to DRAM
Test, the completion of the change characterization read command of the tracking position.
Wherein, as shown in Fig. 2, the command process expense to NVMe agreement specifically included the step of optimizing processing it is following
Step：
In step s 201, a dedicated command process unit is generated, the command process unit is used for described
The acquisition of order in NVMe agreement and the transmission flow for completing order packet carry out control execution；
In step S202, a moderator is generated, the moderator is used for the order packet in the NVMe agreement
Distribute into arbitration.
Wherein, moderator selects one or more to be first carried out from a batch order of acquisition, and arbitration operation can be real
Different priority between now ordering, to guarantee that certain key operations can be executed preferentially.
In embodiments of the present invention, erasing order is added in I/O order, the erasing order is used for flash and PCM
The control wiped records the erasing times to the different erasure locations of flash and PCM；
To next time the region of data is written in the erasing times selection based on different zones.
In embodiments of the present invention, as shown in figure 3, after the command process expense optimization processing to the NVMe agreement,
When ordering starting, the step of being polled using Endpoint to command queue, specifically includes following step：
In step S301, the time of PCIE transmission is estimated；
In step s 302, fetching portion order first, and execute corresponding processing operation；
In step S303, according to the PCIE transmission time estimated, control enters institute while Next Command reaches
State the processing of Next Command.
In this embodiment, when ordering starting, the poll of command queue is carried out using the end Endpoint to substitute
" doorbell " signal of original NVMe, using the characteristic of PCIe full duplex, the one or more life of the lasting transmission of equipment
Request is enabled to arrive " doorbell " signal of command queue without waiting for host of DRAM.By estimating the time of PCIe transmission, if
Standby to obtain number order in advance, ideally, it is next that the time that Next Command reaches just is that equipment can handle
When a order.
In embodiments of the present invention, DRAM is loaded as shown in figure 4, receiving the tracking position content in buffer area using poll
Arrival whether the step of being tested specifically include following step：
In step S401, several marker bits are set in receiving buffer area in advance；
In step S402, before order executes, host receiver buffer is written into pre-set marker bit；
In step S403, the imperfect label in the reception buffer area is detected, judges order whether
Execute completion.
In this embodiment, the tracking position content in buffer area is received to test the arrival of DRAM load using poll, chase after
The change of track position implies the completion of read command.It is received in caching not using being marked based on " imperfect label " method of caching
The part of completion.Some marker bits are set in receiving caching in advance, these marker bits are not present in the data packet of transmission
In, before order executes, label known to this is written to host receiver buffer, is received in buffer area " no by monitoring
Complete label " judges whether order has been completed.Quick chain from CPU to DRAM is used to the judgement whether order is completed
It connects, avoids chaining sending any unnecessary data bit or data packet in relatively slow PCIe.
Fig. 5 shows the structural block diagram for the quick Access Optimization system of isomery mixing memory that the present invention listened, wherein in order to
Convenient for explanation, part related to the embodiment of the present invention is only gived in figure.
The quick Access Optimization system of isomery mixing memory includes：
Protocol optimization processing module 11 optimizes processing for the command process expense to NVMe agreement, wherein described
The command process expense of NVMe agreement includes the acquisition of order, the parsing of order packet, the distribution of order packet and completes order packet
It sends；
Endpoint poller module 12, for working as life after the command process expense optimization processing to the NVMe agreement
When enabling starting, command queue is polled using Endpoint；
Position poller module 13 is tracked, the arrival loaded for receiving the tracking position content in buffer area using poll to DRAM
Whether tested, it is described tracking position change characterization read command completion.
Wherein, protocol optimization processing module 11 specifically includes：
Command process unit generation module 14, for generating a dedicated command process unit, the command process list
Member is for the acquisition to the order in the NVMe agreement and completes that the transmission flow of packet is ordered to carry out control execution；
Moderator generation module 15, for generating a moderator, the moderator is used for in the NVMe agreement
Order the distribution of packet into arbitration.
In this embodiment, erasing instruction adding module 16, for erasing order, the erasing to be added in I/O order
The control for being wiped flash and PCM is ordered, the erasing times to the different erasure locations of flash and PCM are recorded.
In embodiments of the present invention, Endpoint poller module 12 specifically includes：
Time estimates module 17, for estimating to the time that PCIE is transmitted；
Partial order processing module 18 is used for fetching portion order first, and executes corresponding processing operation；
Next Command processing and control module 19, for according to the PCIE transmission time estimated, Next Command to be worked as in control
Into the processing of the Next Command while arrival.
In embodiments of the present invention, tracking position poller module 13 specifically includes：
Marker bit setup module 20, for setting several marker bits in receiving buffer area in advance；
Marker bit writing module 21, for pre-set marker bit write-in host being received slow before order executes
Rush area；
Judgment module 22 is detected, for detecting to the imperfect label in the reception buffer area, judges that order is
It is no to have executed completion.
The function of above-mentioned modules is as recorded in above method embodiment, and details are not described herein.
In embodiments of the present invention, processing is optimized to the command process expense of NVMe agreement, wherein the NVMe association
The command process expense of view includes the acquisition of order, the parsing of order packet, the distribution of order packet and the transmission for completing order packet；?
After the command process expense optimization processing of the NVMe agreement, when order starting when, using Endpoint to command queue into
Row poll；It is tested whether the arrival loaded using the tracking position content in poll reception buffer area to DRAM, the tracking
The completion of the change characterization read command of position, thus solve the problems, such as that the speed of NVM memory access and DRAM memory access is unmatched, it can be in base
In the quick access on the isomery mixing memory platform of NVM expansion system memory to NVM memory, the memory access of system entirety is improved
Can, to improve the performance of isomery mixing memory platform.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention
Made any modifications, equivalent replacements, and improvements etc., should all be included in the protection scope of the present invention within mind and principle.
Claims (10)
1. a kind of quick Access Optimization method of isomery mixing memory, which is characterized in that the method includes the following steps：
Processing is optimized to the command process expense of NVMe agreement, wherein the command process expense of the NVMe agreement includes
The acquisition of order, the parsing of order packet, the distribution of order packet and the transmission for completing order packet；
After the command process expense optimization processing to the NVMe agreement, when ordering starting, using Endpoint to order
Queue is polled；
It is tested whether the arrival loaded using the tracking position content in poll reception buffer area to DRAM, the tracking position
Change the completion of characterization read command.
2. the quick Access Optimization method of isomery mixing memory according to claim 1, which is characterized in that described to be assisted to NVMe
The step of command process expense of view optimizes processing specifically includes following step：
A dedicated command process unit is generated, the command process unit is used for obtaining to the order in the NVMe agreement
The transmission flow for taking and completing order packet carries out control execution；
A moderator is generated, the moderator is used for the distribution to the order packet in the NVMe agreement into arbitration.
3. the quick Access Optimization method of isomery mixing memory according to claim 2, which is characterized in that the method is also wrapped
Include following step：
Erasing order is added in I/O order, the erasing order is used for the control wiped flash and PCM, record pair
The erasing times of the different erasure locations of flash and PCM.
4. the quick Access Optimization method of isomery mixing memory according to claim 3, which is characterized in that described to described
After the command process expense optimization processing of NVMe agreement, when ordering starting, command queue is polled using Endpoint
The step of specifically include following step：
The time of PCIE transmission is estimated；
Fetching portion order first, and execute corresponding processing operation；
According to the PCIE transmission time estimated, control is while Next Command reaches into the place of the Next Command
Reason.
5. the quick Access Optimization method of isomery mixing memory according to claim 4, which is characterized in that described to use poll
The step of testing whether receiving the arrival that the tracking position content in buffer area loads DRAM specifically includes following step：
Several marker bits are set in receiving buffer area in advance；
Before order executes, host receiver buffer is written into pre-set marker bit；
Imperfect label in the reception buffer area is detected, judges whether order has executed completion.
6. a kind of quick Access Optimization system of isomery mixing memory, which is characterized in that the system comprises：
Protocol optimization processing module optimizes processing for the command process expense to NVMe agreement, wherein the NVMe association
The command process expense of view includes the acquisition of order, the parsing of order packet, the distribution of order packet and the transmission for completing order packet；
Endpoint poller module, for starting after the command process expense optimization processing to the NVMe agreement when ordering
When, command queue is polled using Endpoint；
Track position poller module, for using poll receive buffer area in tracking position content DRAM is loaded arrival whether into
Row test, the completion of the change characterization read command of the tracking position.
7. the quick Access Optimization system of isomery mixing memory according to claim 6, which is characterized in that the protocol optimization
Processing module specifically includes：
Command process unit generation module, for generating a dedicated command process unit, the command process unit is used for
The transmission flow of acquisition and completion order packet to the order in the NVMe agreement carries out control execution；
Moderator generation module, for generating a moderator, the moderator is used for the order packet in the NVMe agreement
Distribution into arbitration.
8. the quick Access Optimization system of isomery mixing memory according to claim 7, which is characterized in that the system is also wrapped
It includes：
Erasing instruction adding module, for erasing order to be added in I/O order, the erasing order is used for flash and PCM
The control wiped records the erasing times to the different erasure locations of flash and PCM.
9. the quick Access Optimization system of isomery mixing memory according to claim 8, which is characterized in that the Endpoint
Poller module specifically includes：
Time estimates module, for estimating to the time that PCIE is transmitted；
Partial order processing module is used for fetching portion order first, and executes corresponding processing operation；
Next Command processing and control module, for according to the PCIE transmission time estimated, control to be reached when Next Command
Enter the processing of the Next Command simultaneously.
10. the quick Access Optimization system of isomery mixing memory according to claim 9, which is characterized in that the tracking position
Poller module specifically includes：
Marker bit setup module, for setting several marker bits in receiving buffer area in advance；
Marker bit writing module, for before order executes, host receiver buffer to be written in pre-set marker bit；
Judgment module is detected, for detecting to the imperfect label in the reception buffer area, judges order whether
Execute completion.
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