CN108880606B - Method and device for transmitting synchronization signals - Google Patents

Method and device for transmitting synchronization signals Download PDF

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Publication number
CN108880606B
CN108880606B CN201710510737.1A CN201710510737A CN108880606B CN 108880606 B CN108880606 B CN 108880606B CN 201710510737 A CN201710510737 A CN 201710510737A CN 108880606 B CN108880606 B CN 108880606B
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synchronization signal
signal block
slot
symbols
mapping
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CN108880606A (en
Inventor
刘瑾
凯文·卡·勤·欧
袁璞
向铮铮
罗俊
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7073—Synchronisation aspects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7073—Synchronisation aspects
    • H04B1/7083—Cell search, e.g. using a three-step approach
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W48/00—Access restriction; Network selection; Access point selection
    • H04W48/16—Discovering, processing access restriction or access information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W48/00—Access restriction; Network selection; Access point selection
    • H04W48/20—Selecting an access point
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements

Abstract

The application discloses a method for transmitting a synchronization signal, which is used for solving the problem of long access time of a cell. The method comprises the following steps: generating a first synchronous signal block group and a second synchronous signal block group, mapping m synchronous signal blocks in the first synchronous signal block group into x symbols, wherein the number of symbols with phase difference between the two synchronous signal blocks in the mapped first synchronous signal block group belongs to a first set; mapping n synchronous signal blocks in the second synchronous signal block group to other y symbols, wherein the number of symbols which are different between two synchronous signal blocks in the mapped second synchronous signal block group belongs to a first set, the number of symbols which are different between one synchronous signal block in the mapped second synchronous signal block group and one synchronous signal block in the mapped first synchronous signal block group belongs to a second set, and numerical values in the second set are not overlapped with numerical values in the first set; the first synchronization signal block packet and the second synchronization signal block packet are transmitted.

Description

Method and device for transmitting synchronization signals
The present application claims priority from chinese patent office filed on 16/5/2017 under the name of 201710344557.0 entitled "method and apparatus for transmitting synchronization signals" and chinese patent application filed on 16/6/2017 under the name of 201710459666.7 entitled "method and apparatus for transmitting synchronization signals", the entire contents of which are incorporated herein by reference.
Technical Field
The present application relates to the field of communications technologies, and in particular, to a method for transmitting a synchronization signal, a network device, and a terminal device.
Background
In a conventional cellular communication system, a network side periodically broadcasts a downlink synchronization signal to a covered area in an agreed manner through a base station, so that a terminal device needing to access a network can acquire synchronization of a downlink communication link before accessing the network and correctly acquire communication system information needed by the access network.
In the latest air interface design process for 5G, the concept of a Synchronization Signal block (SS block or SSB) is proposed in consideration of the requirement of the multi-beam technology. The beams have a configurable mapping relationship with the SS block, e.g., the base station transmits a different SS block through each beam of the multiple beams, or 2 beams may transmit the same SS block. The SS block contains a plurality of Orthogonal Frequency Division Multiplexing (OFDM) symbols. A Synchronization Signal pulse (SS burst) comprises a plurality of SS blocks. In other words, SS block is transmitted over time-frequency resources mapped in SS burst.
After the User Equipment (UE) completes the cell search process, the UE has already acquired downlink synchronization with the cell, and at this time, the UE needs to detect the SS block and know how the cell is configured according to the system information acquired from the SS block, so as to access the cell and correctly work in the cell.
Multiple SS blocks transmitted in an SS burst contain the same information. However, when detecting the SS block, the UE cannot determine whether the detected SS blocks belong to the same SS burst. Therefore, the terminal device needs to perform descrambling, cyclic shift, and subsequent protocol processing on the data transmitted in the plurality of SS blocks. Therefore, the process of signal processing of the plurality of SS blocks detected by the UE is complex and time-consuming, resulting in a long cell access time of the UE.
Disclosure of Invention
The embodiment of the application provides a method for transmitting a synchronization signal, which is used for solving the problem of long cell access time caused by the fact that UE cannot determine whether a plurality of SS blocks belong to the same SS burst.
In a first aspect, a method for transmitting a synchronization signal is provided, including:
the network equipment generates a first synchronous signal block packet and a second synchronous signal block packet, wherein the first synchronous signal block packet comprises m synchronous signal blocks, the second synchronous signal block packet comprises n synchronous signal blocks, and m and n are positive integers greater than or equal to 2;
mapping m synchronization signal blocks in the first synchronization signal block group into x symbols, wherein x is 7m, and the number of symbols with a difference between any two synchronization signal blocks in the mapped first synchronization signal block group belongs to a first set;
mapping n synchronization signal blocks in the second synchronization signal block group to y other symbols, where y is 7n, the number of symbols that are different between any two synchronization signal blocks in the mapped second synchronization signal block group belongs to the first set, the number of symbols that are different between one synchronization signal block in the mapped second synchronization signal block group and one synchronization signal block in the mapped first synchronization signal block group belongs to a second set, and a value in the second set does not overlap with a value in the first set;
and the network equipment transmits the synchronous signal blocks in the first synchronous signal block group and the synchronous signal blocks in the second synchronous signal block group through the mapped time-frequency resources.
After the network device performs resource mapping by using the above resource mapping method, the number of symbols that are different between two synchronization signal blocks in the same synchronization signal block grouping in the time domain belongs to the first set, and the number of symbols that are different between two synchronization signal blocks in different synchronization signal block grouping does not belong to the first set. When the terminal device receives the synchronization signal and detects a plurality of synchronization signal blocks, it can determine whether the two synchronization signal blocks belong to the same synchronization signal block group according to the number of symbols of the phase difference between the two synchronization signal blocks. The terminal equipment can then obtain a plurality of synchronous signal blocks belonging to the same synchronous signal block group and carry out simplified processing on the plurality of synchronous signal blocks belonging to the same synchronous signal block group, thereby simplifying the signal processing flow and shortening the time and processing resources consumed by processing the synchronous signal blocks. The terminal equipment can obtain the system information carried in the synchronous signal block more quickly, and the network access time is shortened.
In one possible implementation, the values included in the first set are even numbers, and the values included in the second set are odd numbers.
Accordingly, the arrangement of the first set and the second set is beneficial to simplifying the terminal equipment to confirm whether two synchronization signal blocks belong to the same synchronization signal block group. After determining the number of the phase difference symbols, the terminal equipment judges whether the number of the phase difference symbols is an even number. If the number of symbols of the difference is even, the terminal device determines that the first synchronization signal block and the second synchronization signal block belong to the same synchronization signal block group.
In one possible implementation, m and n are 4, and x and y are 28.
If m and n are 4 and x and y are 28, in a possible implementation manner, each slot includes 7 symbols, and mapping m synchronization signal blocks in the first synchronization signal block group into x symbols includes:
mapping a first synchronization signal block in the first synchronization signal block grouping on the 2 nd-5 th symbol of the 1 st slot in the continuous 8 slots, mapping a second synchronization signal block in the first synchronization signal block grouping on the 2 nd-5 th symbol of the 3 rd slot in the continuous 8 slots, mapping a third synchronization signal block in the first synchronization signal block grouping on the 2 nd-5 th symbol of the 5 th slot in the continuous 8 slots, mapping a fourth synchronization signal block in the first synchronization signal block grouping on the 2 nd-5 th symbol of the 7 th slot in the continuous 8 slots;
the mapping n synchronization signal blocks in the second synchronization signal block grouping into y further symbols comprises:
mapping a first synchronization signal block of the second synchronization signal block grouping on the 2 nd-5 th symbol of the 2 nd slot of the consecutive 8 slots, mapping a second synchronization signal block of the second synchronization signal block grouping on the 2 nd-5 th symbol of the 4 th slot of the consecutive 8 slots, mapping a third synchronization signal block of the second synchronization signal block grouping on the 2 nd-5 th symbol of the 6 th slot of the consecutive 8 slots, and mapping a fourth synchronization signal block of the second synchronization signal block grouping on the 2 nd-5 th symbol of the 8 th slot of the consecutive 8 slots.
If m and n are 4 and x and y are 28, in a possible implementation manner, each slot includes 14 symbols, and mapping m synchronization signal blocks in the first synchronization signal block group into x symbols includes:
mapping a first synchronization signal block in the first synchronization signal block grouping on the 2 nd-5 th symbol of the 1 st slot in the consecutive 4 slots, mapping a second synchronization signal block in the first synchronization signal block grouping on the 2 nd-5 th symbol of the 2 nd slot in the consecutive 4 slots, mapping a third synchronization signal block in the first synchronization signal block grouping on the 2 nd-5 th symbol of the 3 rd slot in the consecutive 4 slots, mapping a fourth synchronization signal block in the first synchronization signal block grouping on the 2 nd-5 th symbol of the 4 th slot in the consecutive 4 slots;
the mapping n synchronization signal blocks in the second synchronization signal block grouping into y further symbols comprises:
mapping a first synchronization signal block of the second synchronization signal block grouping on the 9 th-12 th symbols of the 1 st slot of the consecutive 4 slots, mapping a second synchronization signal block of the second synchronization signal block grouping on the 9 th-12 th symbols of the 2 nd slot of the consecutive 4 slots, mapping a third synchronization signal block of the second synchronization signal block grouping on the 9 th-12 th symbols of the 3 rd slot of the consecutive 4 slots, and mapping a fourth synchronization signal block of the second synchronization signal block grouping on the 9 th-12 th symbols of the 4 th slot of the consecutive 4 slots.
In one possible implementation, the following values 14, 28, 42 are included in the first set, and the following values 7, 21, 35, 49 are included in the second set.
If m and n are 4 and x and y are 28, in a possible implementation manner, each slot includes 14 symbols, and mapping m synchronization signal blocks in the first synchronization signal block group into x symbols includes:
mapping a first synchronization signal block in the first synchronization signal block grouping on the 4 th-7 th symbols of the first time slot, mapping a second synchronization signal block in the first synchronization signal block grouping on the 8 th-11 th symbols of the first time slot, mapping a third synchronization signal block in the first synchronization signal block grouping on the 3 rd-6 th symbols of the second time slot, and mapping a fourth synchronization signal block in the first synchronization signal block grouping on the 7 th-10 th symbols of the second time slot;
the mapping n synchronization signal blocks in the second synchronization signal block grouping into y further symbols comprises:
mapping a first synchronization signal block of the second synchronization signal block grouping on the 4 th-7 th symbols of the third slot, mapping a second synchronization signal block of the second synchronization signal block grouping on the 8 th-11 th symbols of the third slot, mapping a third synchronization signal block of the second synchronization signal block grouping on the 3 rd-6 th symbols of the fourth slot, and mapping a fourth synchronization signal block of the second synchronization signal block grouping on the 7 th-10 th symbols of the fourth slot, wherein the first slot, the second slot, the third slot and the fourth slot are 4 consecutive slots.
In one possible implementation, the first set includes the following values: 4. 9, 13, 17, the second set comprising the following values: 11. 15 and 19.
If m and n are 4 and x and y are 28, in a possible implementation manner, each slot includes 14 symbols, and mapping m synchronization signal blocks in the first synchronization signal block group into x symbols includes:
mapping a first synchronization signal block in the first synchronization signal block grouping on the 3 rd to 6 th symbols of the first time slot, mapping a second synchronization signal block in the first synchronization signal block grouping on the 7 th to 10 th symbols of the first time slot, mapping a third synchronization signal block in the first synchronization signal block grouping on the 4 th to 7 th symbols of the second time slot, and mapping a fourth synchronization signal block in the first synchronization signal block grouping on the 8 th to 11 th symbols of the second time slot;
the mapping n synchronization signal blocks in the second synchronization signal block grouping into y further symbols comprises:
mapping a first synchronization signal block of the second synchronization signal block packet on the 3 rd to 6 th symbols of the third slot, mapping a second synchronization signal block of the second synchronization signal block packet on the 7 th to 10 th symbols of the third slot, mapping a third synchronization signal block of the second synchronization signal block packet on the 4 th to 7 th symbols of the fourth slot, mapping a fourth synchronization signal block of the second synchronization signal block packet on the 8 th to 11 th symbols of the fourth slot, the first slot, the second slot, the third slot and the fourth slot being 4 consecutive slots.
In one possible implementation, the first set includes the following values: 4. 11, 15, 19, the second set comprising the following values: 9. 13 and 17.
In a possible implementation manner, the values included in the first set are smaller than a predetermined threshold, and the values included in the second set are larger than the predetermined threshold.
Accordingly, the arrangement of the first set and the second set is beneficial to simplifying the terminal equipment to confirm whether two synchronization signal blocks belong to the same synchronization signal block group. After determining the number of the symbols with the phase difference, the terminal equipment judges whether the number of the symbols with the phase difference exceeds a preset threshold value. If the number of symbols that differ does not exceed a predetermined threshold, the terminal device determines that the first synchronization signal block and the second synchronization signal block belong to the same synchronization signal block group.
In one possible implementation, m and n are 4, and x and y are 28.
If m and n are 4 and x and y are 28, in a possible implementation manner, the predetermined threshold is a positive integer greater than or equal to 21.
If m and n are 4 and x and y are 28, in a possible implementation manner, each slot includes 7 symbols, and mapping m synchronization signal blocks in the first synchronization signal block group into x symbols includes:
mapping a first synchronization signal block in the first synchronization signal block group on the 2 nd-5 th symbol of a first time slot, mapping a second synchronization signal block in the first synchronization signal block group on the 1 st-4 th symbol of a second time slot, mapping a third synchronization signal block in the first synchronization signal block group on the 2 nd-5 th symbol of a third time slot, and mapping a fourth synchronization signal block in the first synchronization signal block group on the 1 st-4 th symbol of a fourth time slot, wherein the first time slot, the second time slot, the third time slot and the fourth time slot are continuous time slots;
the mapping n synchronization signal blocks in the second synchronization signal block grouping into y further symbols comprises:
mapping a first synchronous signal block in the first synchronous signal block group on the 2 nd to 5 th symbols of a fifth time slot, mapping a second synchronous signal block in the first synchronous signal block group on the 1 st to 4 th symbols of a sixth time slot, mapping a third synchronous signal block in the first synchronous signal block group on the 2 nd to 5 th symbols of a seventh time slot, and mapping a fourth synchronous signal block in the first synchronous signal block group on the 1 st to 4 th symbols of an eighth time slot, wherein the fifth time slot, the sixth time slot, the seventh time slot and the eighth time slot are continuous time slots, and the fourth time slot and the fifth time slot are separated by at least 2 time slots.
If m and n are 4 and x and y are 28, in a possible implementation manner, each slot includes 14 symbols, and mapping m synchronization signal blocks in the first synchronization signal block group into x symbols includes:
mapping a first synchronization signal block in the first synchronization signal block group on the 2 nd to 5 th symbols of a first time slot, mapping a second synchronization signal block in the first synchronization signal block group on the 8 th to 11 th symbols of the first time slot, mapping a third synchronization signal block in the first synchronization signal block group on the 2 nd to 5 th symbols of a second time slot, and mapping a fourth synchronization signal block in the first synchronization signal block group on the 8 th to 11 th symbols of the second time slot, wherein the first time slot and the second time slot are continuous time slots;
the mapping n synchronization signal blocks in the second synchronization signal block grouping into y further symbols comprises:
mapping a first synchronization signal block in the second synchronization signal block packet on the 2 nd-5 th symbol of a third slot, mapping a second synchronization signal block in the second synchronization signal block packet on the 8 th-11 th symbol of the third slot, mapping a third synchronization signal block in the second synchronization signal block packet on the 2 nd-5 th symbol of a fourth slot, and mapping a fourth synchronization signal block in the second synchronization signal block packet on the 8 th-11 th symbol of the fourth slot, wherein the third slot and the fourth slot are consecutive slots and the second slot and the third slot are separated by at least 1 slot.
If m and n are 4 and x and y are 28, in a possible implementation manner, if each slot includes 14 symbols, mapping m synchronization signal blocks in the first synchronization signal block group into x symbols includes:
mapping a first synchronization signal block in the first synchronization signal block grouping on the 2 nd to 5 th symbols of a first time slot, mapping a second synchronization signal block in the first synchronization signal block grouping on the 7 th to 10 th symbols of the first time slot, mapping a third synchronization signal block in the first synchronization signal block grouping on the 2 nd to 5 th symbols of a second time slot, and mapping a fourth synchronization signal block in the first synchronization signal block grouping on the 7 th to 10 th symbols of the second time slot, wherein the first time slot and the second time slot are continuous time slots;
the mapping n synchronization signal blocks in the second synchronization signal block grouping into y further symbols comprises:
mapping a first synchronization signal block in the second synchronization signal block group on the 2 nd to 5 th symbols of a third time slot, mapping a second synchronization signal block in the second synchronization signal block group on the 7 th to 10 th symbols of the third time slot, mapping a third synchronization signal block in the second synchronization signal block group on the 2 nd to 5 th symbols of a fourth time slot, and mapping a fourth synchronization signal block in the second synchronization signal block group on the 7 th to 10 th symbols of the fourth time slot, wherein the third time slot and the fourth time slot are consecutive time slots, and the second time slot and the third time slot are separated by at least 1 time slot.
If m and n are 4 and x and y are 28, in a possible implementation manner, if each slot includes 14 symbols, mapping m synchronization signal blocks in the first synchronization signal block group into x symbols includes:
mapping a first synchronization signal block in the first synchronization signal block group on the 3 rd to 6 th symbols of a first time slot, mapping a second synchronization signal block in the first synchronization signal block group on the 8 th to 11 th symbols of the first time slot, mapping a third synchronization signal block in the first synchronization signal block group on the 3 rd to 6 th symbols of a second time slot, and mapping a fourth synchronization signal block in the first synchronization signal block group on the 8 th to 11 th symbols of the second time slot, wherein the first time slot and the second time slot are continuous time slots;
the mapping n synchronization signal blocks in the second synchronization signal block grouping into y further symbols comprises:
mapping a first synchronization signal block in the second synchronization signal block packet on the 3 rd to 6 th symbols of a third slot, mapping a second synchronization signal block in the second synchronization signal block packet on the 8 th to 11 th symbols of the third slot, mapping a third synchronization signal block in the second synchronization signal block packet on the 3 rd to 6 th symbols of a fourth slot, and mapping a fourth synchronization signal block in the second synchronization signal block packet on the 8 th to 11 th symbols of the fourth slot, wherein the third slot and the fourth slot are consecutive slots and the second slot and the third slot are separated by at least 1 slot.
If m and n are 4 and x and y are 28, in a possible implementation manner, if each slot includes 14 symbols, mapping m synchronization signal blocks in the first synchronization signal block group into x symbols includes:
mapping a first synchronization signal block in the first synchronization signal block grouping on the 3 rd to 6 th symbols of a first time slot, mapping a second synchronization signal block in the first synchronization signal block grouping on the 7 th to 10 th symbols of the first time slot, mapping a third synchronization signal block in the first synchronization signal block grouping on the 3 rd to 6 th symbols of a second time slot, and mapping a fourth synchronization signal block in the first synchronization signal block grouping on the 7 th to 10 th symbols of the second time slot, wherein the first time slot and the second time slot are continuous time slots;
the mapping n synchronization signal blocks in the second synchronization signal block grouping into y further symbols comprises:
mapping a first synchronization signal block in the second synchronization signal block packet on the 3 rd to 6 th symbols of a third slot, mapping a second synchronization signal block in the second synchronization signal block packet on the 7 th to 10 th symbols of the third slot, mapping a third synchronization signal block in the second synchronization signal block packet on the 3 rd to 6 th symbols of a fourth slot, and mapping a fourth synchronization signal block in the second synchronization signal block packet on the 7 th to 10 th symbols of the fourth slot, wherein the third slot and the fourth slot are consecutive slots and the second slot and the third slot are separated by at least 1 slot.
If m and n are 4 and x and y are 28, in a possible implementation manner, if each slot includes 14 symbols, mapping m synchronization signal blocks in the first synchronization signal block group into x symbols includes:
mapping a first synchronization signal block in the first synchronization signal block grouping on the 4 th-7 th symbols of a first time slot, mapping a second synchronization signal block in the first synchronization signal block grouping on the 8 th-11 th symbols of the first time slot, mapping a third synchronization signal block in the first synchronization signal block grouping on the 4 th-7 th symbols of a second time slot, and mapping a fourth synchronization signal block in the first synchronization signal block grouping on the 8 th-11 th symbols of the second time slot, wherein the first time slot and the second time slot are continuous time slots;
the mapping n synchronization signal blocks in the second synchronization signal block grouping into y further symbols comprises:
mapping a first synchronization signal block in the second synchronization signal block packet on the 4 th-7 th symbols of a third slot, mapping a second synchronization signal block in the second synchronization signal block packet on the 8 th-11 th symbols of the third slot, mapping a third synchronization signal block in the second synchronization signal block packet on the 4 th-7 th symbols of a fourth slot, and mapping a fourth synchronization signal block in the second synchronization signal block packet on the 8 th-11 th symbols of the fourth slot, wherein the third slot and the fourth slot are consecutive slots and the second slot and the third slot are separated by at least 1 slot.
In one possible implementation, the predetermined threshold is a positive integer greater than 12 and less than 18.
If m and n are 4 and x and y are 28, in a possible implementation manner, each slot includes 14 symbols, and mapping m synchronization signal blocks in the first synchronization signal block group into x symbols includes:
mapping a first synchronization signal block in the first synchronization signal block packet on the 5 th to 8 th symbols of a first slot, mapping a second synchronization signal block in the first synchronization signal block packet on the 9 th to 12 th symbols of the first slot, mapping a third synchronization signal block in the first synchronization signal block packet on the 13 th to 14 th symbols of the first slot and the 1 st to 2 nd symbols of a second slot, and mapping a fourth synchronization signal block in the first synchronization signal block packet on the 3 rd to 6 th symbols of the second slot;
the mapping n synchronization signal blocks in the second synchronization signal block grouping into y further symbols comprises:
mapping a first synchronization signal block in the second synchronization signal block packet on the 7 th-10 th symbols of a third slot, mapping a second synchronization signal block in the second synchronization signal block packet on the 11 th-14 th symbols of the third slot, mapping a third synchronization signal block in the second synchronization signal block packet on the 1 st-4 th symbols of a fourth slot, and mapping a fourth synchronization signal block in the second synchronization signal block packet on the 5 th-8 th symbols of the fourth slot, wherein the first slot, the second slot, the third slot and the fourth slot are consecutive slots.
In one possible implementation, the symbols mapped by the first and second synchronization signal block packets occupy the first 5 milliseconds of a synchronization signal pulse set transmission period in which the first and second synchronization signal block packets are located, and the transmission period of the synchronization signal pulse set is configured as one of: 5 milliseconds, 10 milliseconds, 20 milliseconds, 40 milliseconds, 80 milliseconds, 160 milliseconds.
In a second aspect, a method for transmitting a synchronization signal is provided, including:
the terminal equipment detects a first synchronous signal block and a second synchronous signal block in a sending period of a synchronous signal pulse set;
the terminal equipment determines the number of symbols of a phase difference between the time domain resource occupied by the first synchronous signal block and the time domain resource occupied by the second synchronous signal block;
if the number of symbols differing by the phase belongs to a predetermined set, the terminal device determines that the first synchronization signal block and the second synchronization signal block belong to the same synchronization signal block group.
In one possible implementation, the values included in the predetermined set are even numbers.
In one possible implementation, the values included in the predetermined set are less than a predetermined threshold.
In one possible implementation, the transmission period of the set of synchronization signal pulses is configured as one of: 5ms, 10ms, 20ms, 40ms, 80ms, 160ms, the synchronization signal block and second synchronization signal block being detected by the terminal device in the first 5ms of the set of synchronization signal pulses transmission period.
In a third aspect, a network device is provided, where the network device has a function of implementing the method of the first aspect or any one of the possible implementations of the first aspect. The functions can be realized by hardware, and the functions can also be realized by executing corresponding software by hardware. The hardware or software includes one or more modules corresponding to the above-described functions.
In a fourth aspect, a computer storage medium is provided, which is used to store computer software instructions for the network device, and which contains a program designed to execute the first aspect or any one of the possible implementation manners of the first aspect.
In a fifth aspect, a terminal device is provided, where the terminal device has a function of implementing the method of the second aspect or any one of the possible implementations of the second aspect. The functions can be realized by hardware, and the functions can also be realized by executing corresponding software by hardware. The hardware or software includes one or more modules corresponding to the above-described functions.
A sixth aspect provides a computer storage medium for storing computer software instructions for the terminal device, which contains a program designed to execute the second aspect or any one of the possible implementation manners of the second aspect.
In a seventh aspect, an embodiment of the present application provides a communication system, including the network device described in any one of the third aspect or possible implementation manners of the third aspect, and the terminal device described in any one of the fifth aspect or possible implementation manners of the fifth aspect.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic diagram of a network system applied in the embodiment of the present application;
fig. 2 is a schematic structural diagram of an SS block packet provided in an embodiment of the present application;
fig. 3 is a schematic diagram of a resource mapping manner of an SS block packet according to an embodiment of the present application;
fig. 4 is a flowchart of a method for transmitting a synchronization signal according to an embodiment of the present disclosure;
fig. 5 is a flowchart of another method for transmitting a synchronization signal according to an embodiment of the present application;
fig. 6 is a schematic diagram of a resource mapping method according to an embodiment of the present application;
fig. 7 is a schematic diagram of another resource mapping manner provided in the embodiment of the present application;
fig. 8 is a schematic diagram of another resource mapping manner provided in the embodiment of the present application;
fig. 9 is a schematic diagram of another resource mapping manner provided in the embodiment of the present application;
fig. 10 is a schematic diagram of another resource mapping manner provided in the embodiment of the present application;
fig. 11 is a schematic diagram of another resource mapping manner provided in the embodiment of the present application;
fig. 12 is a schematic diagram of another resource mapping manner provided in the embodiment of the present application;
fig. 13 is a schematic diagram of another resource mapping manner provided in the embodiment of the present application;
fig. 14 is a schematic diagram of another resource mapping manner provided in the embodiment of the present application;
fig. 15 is a schematic diagram of inband interference provided by an embodiment of the present application;
fig. 16 is a schematic diagram of another resource mapping manner provided in the embodiment of the present application;
fig. 17 is a schematic diagram of another resource mapping manner provided in the embodiment of the present application;
fig. 18 is a schematic diagram of another resource mapping manner provided in the embodiment of the present application;
fig. 19 is a flowchart of a method for transmitting a synchronization signal according to an embodiment of the present application;
fig. 20 is a schematic diagram of a resource mapping when a base station transmits an SS block according to an embodiment of the present application;
fig. 21 is a schematic diagram of another resource mapping when a base station transmits an SS block according to an embodiment of the present application;
fig. 22 is a schematic diagram of another resource mapping when a base station transmits an SS block according to an embodiment of the present application;
fig. 23 is a schematic diagram of another resource mapping when a base station transmits an SS block according to an embodiment of the present application;
fig. 24 is a schematic diagram of another resource mapping when a base station transmits an SS block according to an embodiment of the present application;
fig. 25 is a schematic diagram of another resource mapping when a base station transmits an SS block according to an embodiment of the present application;
fig. 26 is a schematic diagram of another resource mapping when a base station transmits an SS block according to an embodiment of the present application;
fig. 27 is a schematic diagram of another resource mapping when a base station transmits an SS block according to an embodiment of the present application;
fig. 28 is a flowchart of a method for transmitting a synchronization signal according to an embodiment of the present application;
fig. 29 is a schematic diagram of inband interference provided by an embodiment of the present application;
fig. 30 is a schematic diagram of another resource mapping when a base station transmits an SS block according to an embodiment of the present application;
fig. 31 is a schematic structural diagram of a network device according to an embodiment of the present application;
fig. 32 is a schematic structural diagram of another network device according to an embodiment of the present application;
fig. 33 is a schematic structural diagram of a terminal device according to an embodiment of the present application;
fig. 34 is a schematic structural diagram of another terminal device according to an embodiment of the present application;
fig. 35 is a schematic diagram of a resource mapping manner of a synchronization signal block according to an embodiment of the present application;
fig. 36 is a schematic diagram of another resource mapping manner of a synchronization signal block according to an embodiment of the present application;
fig. 37 is a schematic diagram of another resource mapping method for a synchronization signal block according to an embodiment of the present application.
Detailed Description
The technical solution in the present application will be described below with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a network system applied in the embodiment of the present application. As shown in fig. 1, the network system 100 may include a network device 102 and terminal devices 104, 106, 108, 110, 112, and 114, wherein the network device and the terminal devices are connected by wireless. It should be understood that fig. 1 only illustrates that the network system includes one network device, but the embodiment of the present invention is not limited thereto, for example, the system may also include more network devices; similarly, the system may also comprise more terminal devices.
Various embodiments are described herein in connection with a terminal device. Terminal equipment may also refer to UEs, access terminals, mobile stations, remote terminals, mobile devices, user terminals, user agents. The terminal device may also be a handheld device with wireless communication functionality, a computing device or other processing device connected to a wireless modem, a vehicle device, a wearable device, a terminal device in a future 5G Network or a terminal device in a future evolved Public Land Mobile Network (PLMN) Network, etc.
By way of example, and not limitation, in embodiments of the present invention, the terminal device may also be a wearable device. Wearable equipment can also be called wearable intelligent equipment, is the general term of applying wearable technique to carry out intelligent design, develop the equipment that can dress to daily wearing, like glasses, gloves, wrist-watch, dress and shoes etc.. A wearable device is a portable device that is worn directly on the body or integrated into the clothing or accessories of the user. The wearable device is not only a hardware device, but also realizes powerful functions through software support, data interaction and cloud interaction. The generalized wearable smart device includes full functionality, large size, and can implement full or partial functionality without relying on a smart phone, such as: smart watches or smart glasses and the like, and only focus on a certain type of application functions, and need to be used in cooperation with other devices such as smart phones, such as various smart bracelets for physical sign monitoring, smart jewelry and the like. In the embodiments of the present application, a structure and a processing flow of a terminal device are described with a UE as an example.
Various embodiments are described herein in connection with a network device. The Network device may be a device for communicating with a terminal device, and the Network device may be a Base Transceiver Station (BTS) in a Global System for Mobile communication (GSM) or Code Division Multiple Access (CDMA) System, a Base Station (NodeB, NB) in a Wideband Code Division Multiple Access (WCDMA) System, an evolved Node B (eNB, or eNodeB) in a Long Term Evolution (LTE) System, a wireless controller in a Cloud Radio Access Network (CRAN) scenario, or a Base Station (gbb or gsb) in a future 5G Network. In the embodiments of the present application, a base station is taken as an example to describe a structure and a processing flow of a network device.
Fig. 2 is a schematic diagram of a possible SS block packet structure. A plurality of SS blocks are contained in one SS block group. Alternatively, an SS block packet may be a Synchronization Signal burst (SS burst). Alternatively, one SS block packet is mapped on at least 2 slots (slots) in the time domain.
Optionally, one SS block contains a Primary Synchronization Signal (PSS) of 1 OFDM symbol or a New wireless Primary Synchronization Signal (NR-PSS), a Secondary Synchronization Signal (SSs) of 1 OFDM symbol or a New wireless Secondary Synchronization Signal (NR-SSs) and a Physical Broadcast Channel (PBCH) of 2 OFDM symbols or a New wireless Physical Broadcast Channel (NR-PBCH). Where NR-PSS and NR-SSS may have the functionality of PSS and SSS, respectively, in legacy standards (e.g., LTE). For example, NR-PSS may be used to determine OFDM symbol timing, frequency synchronization, slot timing and cell ID within a cell group; the NR-SSS may be used to determine frame timing, cell group, etc., or the NR-PSS and NR-SSS may have different functions from those of the current PSS and SSS, which is not limited in the embodiments of the present application. In addition, the NR-PSS and NR-SSS may adopt the same or different sequences as the current PSS and SSS, respectively, which is not limited in the embodiment of the present invention. In addition, in the embodiment of the present application, the NR-PBCH may have the same or different function as the PBCH in the conventional standard (e.g., LTE), which is also not limited in the embodiment of the present invention. Alternatively, a Master Information Block (MIB) may be carried in the NR-PBCH. It should be noted that the arrangement of the OFDM symbols in the SS block corresponding to the PSS, the SSS, and the PBCH is not limited to the four arrangement shown in fig. 2.
If the terminal device can confirm a plurality of SS blocks belonging to the same SS block group when receiving the synchronization signal, simplified processing, for example, combining demodulated SS blocks, may be performed on the plurality of SS blocks belonging to the same SS block group. However, when the network device sends the SS block, resource mapping is performed on the SS blocks in the same SS block group in the physical layer. When the network device sends the SS blocks, some resource mapping methods will cause that when the UE receives the SS blocks, it cannot be determined whether the two received SS blocks belong to the same SS block group or belong to different SS block groups. As shown in fig. 3, 4 SS blocks of the first SS block group are respectively mapped to the 2 nd to 5 th OFDM symbols of slot 1, the 9 th to 12 th OFDM symbols of slot 1, the 2 nd to 5 th OFDM symbols of slot 2, and the 9 th to 12 th OFDM symbols of slot 2; and mapping 4 SS blocks of the second SS block group on the 2 nd to 5 th OFDM symbols of slot 3, the 9 th to 12 th OFDM symbols of slot 3, the 2 nd to 5 th OFDM symbols of slot 4 and the 9 th to 12 th OFDM symbols of slot 4 respectively. Thus, every two SS blocks are separated by 3 OFDM symbols. For example, after demodulation, the UE cannot combine soft bit data obtained by demodulation from two SS blocks, and needs to perform decoding, cyclic shift (cyclic shift), and other processing on each SS block. The resource mapping method leads to more complex subsequent signal processing, thereby affecting the performance of the communication system.
The embodiment of the application provides a method for transmitting a synchronous signal, and when a network device sends an SS block, resource mapping is carried out on the SS block in an SS block group according to a preset resource mapping mode. Therefore, when the terminal equipment receives the SS blocks, whether the SS blocks belong to the same SS block group or not is confirmed according to the relative position relation among the SS blocks, and the subsequent processing is simplified.
The main implementation principle, the specific implementation mode and the corresponding beneficial effects of the technical scheme of the embodiment of the invention are explained in detail with reference to the drawings.
Example one
Fig. 4 is a flowchart of a method for transmitting a synchronization signal according to an embodiment of the present application. The flow chart describes the process of the network device, taking the base station as an example, transmitting the synchronization signal from the perspective of the base station. In the following embodiments of the present application, a base station is taken as an example to introduce the working principle and function of a network device.
Step 41, the network device generates a first synchronization signal block packet and a second synchronization signal block packet. The first synchronization signal block group comprises m synchronization signal blocks, and the second synchronization signal block group comprises n synchronization signal blocks, wherein m and n are positive integers greater than or equal to 2. The values of m and n may be the same or different, and the present application does not limit this.
Alternatively, the structure of the synchronization signal block can refer to fig. 2, but is not limited to the 4 possibilities shown in fig. 2.
And step 42, the network device maps m synchronization signal blocks in the first synchronization signal block packet into x symbols, wherein x is 7m, and the number of symbols with a difference between any two synchronization signal blocks in the mapped first synchronization signal block packet belongs to a first set. Mapping at least n synchronization signal blocks in the second synchronization signal block group to another y symbols, where y is 7n, the number of symbols that are different between any two synchronization signal blocks in the mapped second synchronization signal block group also belongs to the first set, the number of symbols that are different between one synchronization signal block in the mapped second synchronization signal block group and one synchronization signal block in the mapped first synchronization signal block group belongs to a second set, and the numerical value in the second set does not overlap the numerical value in the first set.
Optionally, when m and n are 2, x and y are 14.
Optionally, when m and n are 4, x and y are 28.
The above-mentioned another y symbols refer to symbols other than the x symbols, and there is no coincident symbol among the x symbols and the y symbols.
The first set contains at least one value and the second set contains at least one value. The total number of values contained in the first set may or may not be equal to the total number of values contained in the second set. A value in the second set that is not coincident with a value in the first set means that there is no value present in both the first set and the second set. In other words, if a value is present in the first set, it is not possible for the value to be present in the second set, and vice versa. It is also understood that there is no intersection between the first set and the second set.
Step 43, the network device transmits the synchronization signal blocks in the first synchronization signal block packet and the synchronization signal blocks in the second synchronization signal block packet by using the mapped time-frequency resources.
Alternatively, the sync signal block packet is a sync signal pulse (English: ss burst). A plurality of sync block packets may be transmitted in one sync burst set (english). Optionally, the synchronization signal blocks in the mapped first synchronization signal block packet and the synchronization signal blocks in the mapped second synchronization signal block packet occupy the first 5ms in one ss burst set transmission period in the time domain.
The ss burst set transmission period is configurable in the communication system, and can be configured as one of the following: 5ms (English: ms), 10ms, 20ms, 40ms, 80ms, 160 ms.
Alternatively, the synchronization signal transmission method shown in fig. 4 is applicable to communication systems with various frequency points, such as a communication system with a subcarrier spacing of 15kHz, a communication system with a subcarrier spacing of 30kHz, a communication system with a subcarrier spacing of 120kHz, and a communication system with a subcarrier spacing of 240 kHz.
After the network device performs resource mapping by using the above resource mapping method, the number of symbols that are different between two synchronization signal blocks in the same synchronization signal block grouping in the time domain belongs to the first set, and the number of symbols that are different between two synchronization signal blocks in different synchronization signal block grouping does not belong to the first set. When the terminal device receives the synchronization signal and detects a plurality of synchronization signal blocks, it can determine whether the two synchronization signal blocks belong to the same synchronization signal block group according to the number of symbols of the phase difference between the two synchronization signal blocks. The terminal equipment can then obtain a plurality of synchronous signal blocks belonging to the same synchronous signal block group and carry out simplified processing on the plurality of synchronous signal blocks belonging to the same synchronous signal block group, thereby simplifying the signal processing flow and shortening the time and processing resources consumed by processing the synchronous signal blocks. The terminal equipment can obtain the system information carried in the synchronous signal block more quickly, and the network access time is shortened.
Fig. 5 is a flowchart of another method for transmitting a synchronization signal according to an embodiment of the present application. The flowchart describes a procedure in which the terminal device, taking the UE as an example, receives a synchronization signal from the perspective of the terminal device. In the following embodiments of the present application, UE is taken as an example to introduce the working principle and function of the terminal device.
Step 51, the terminal device detects the first synchronization signal block and the second synchronization signal block in a ss burst set transmission period.
Optionally, the terminal device detects a plurality of synchronization signal blocks in one ss burst set transmission period through blind detection. And selecting 2 synchronous signal blocks from the plurality of synchronous signal blocks obtained by blind detection, and determining whether the selected 2 synchronous signal blocks belong to the same synchronous signal block group. It is thus possible to determine a plurality of synchronization signal blocks each contained in each synchronization signal block packet in the transmission period of one synchronization signal pulse set.
Optionally, since the network device maps two synchronization signal block packets in the first 5 microseconds of the transmission period of the synchronization signal burst set. The terminal device thus detects a number of sync signal blocks in the first 5ms of each transmission period of ss burst set.
Step 52, the terminal device determines the number of symbols of the phase difference between the time domain resource occupied by the first synchronization signal block and the time domain resource occupied by the second synchronization signal block.
In step 53, the terminal device determines that the number of the symbols with the phase difference determined in step 52 belongs to a predetermined set, and if the number of the symbols with the phase difference belongs to the predetermined set, executes step 54.
In this embodiment, the predetermined set is the first set in the embodiment shown in fig. 4.
Step 54, the terminal device determines that the first synchronization signal block and the second synchronization signal block belong to the same synchronization signal block group.
Alternatively, the terminal device may perform simplified processing on a plurality of synchronization signal blocks belonging to the same synchronization signal block packet, for example, in soft combining the demodulation results of the plurality of synchronization signal blocks, performing subsequent protocol processing on the result of the soft combining, and the like, without performing decoding, cyclic shift, and subsequent protocol processing on each synchronization signal block, respectively.
Alternatively, in step 53, if the number of symbols that differ does not belong to the predetermined set, step 55 is performed, and the terminal device determines that the first synchronization signal block and the second synchronization signal block belong to different synchronization signal block groups.
In this embodiment, when the terminal device detects multiple sync signal blocks in a sending period of a sync signal pulse set, it may determine whether two sync signal blocks belong to the same sync signal block group according to whether the number of symbols having a difference between the two sync signal blocks belongs to a predetermined set, so as to further obtain multiple sync signal blocks belonging to the same sync signal block group. The terminal device can perform a simplified signal processing flow for a plurality of subsequent synchronization signal blocks belonging to the same synchronization signal block group. Because the signal processing flow is simplified, the time and the processing resource for processing the synchronous signal block are shortened, the system information carried in the synchronous signal block can be obtained more quickly, and the network access time is shortened.
The following describes various resource mapping manners of the synchronization signal block provided by the embodiments of the present application with reference to fig. 6 to 30. These resource mapping schemes may be applied in step 42 of fig. 4. The resource mapping manners shown in fig. 6 to 30 are suitable for the case where each synchronization signal block group includes 4 synchronization signal blocks, and each synchronization signal block group is mapped onto 28 symbols, that is, the values of m and n are 4, and the values of x and y are 28. When any resource mapping mode in fig. 6-30 is adopted, the terminal device can determine whether two synchronization signal blocks belong to the same synchronization signal block group according to whether the detected number of symbols that are different between the two synchronization signal blocks belongs to a predetermined set.
Fig. 6 and fig. 7 are schematic diagrams of a resource mapping method according to an embodiment of the present application. The two resource mapping schemes are respectively suitable for different slot formats, the resource mapping scheme shown in fig. 6 is suitable for a scenario in which a slot used by the communication system includes 7 symbols, and the resource mapping scheme shown in fig. 7 is suitable for a scenario in which a slot used by the communication system includes 14 symbols. In the resource mapping scheme shown in fig. 6 or fig. 7, the number of symbols that are different between any two synchronization signal blocks in the same synchronization signal block group belongs to a first set, the number of symbols that are different between two synchronization signal blocks belonging to different synchronization signal block groups belongs to a second set that is not overlapped with the first set, and the value included in the first set is an even number, and the value included in the second set is an odd number.
The resource mapping scheme provided in fig. 6 is applicable to a scenario in which a slot used by the communication system includes 7 symbols. The network device maps the first and second synchronization signal block packets onto different 4 time slots, for example onto 4 time slots spaced apart among 8 consecutive time slots. A specific resource mapping manner is described below with ss burst as an example of a synchronization signal block packet, and it can be understood that in the case that a time slot used by the communication system includes 7 symbols, a subcarrier spacing supported by the communication system on a frequency domain may be 15kHz, 30kHz, 120kHz, or 240 kHz.
As shown in fig. 6, slots j to j +7 represent consecutive 8 slots. The network equipment maps ss block1 in ss burst k on the 2 nd to 5 th symbols of the 1 st time slot in the continuous 8 time slots, maps ss block2 in ss burst k on the 2 nd to 5 th symbols of the 3 rd time slot in the continuous 8 time slots, maps ss block 3 in ss burst k on the 2 nd to 5 th symbols of the 5 th time slot in the continuous 8 time slots, and maps ss block4 in ss burst k on the 2 nd to 5 th symbols of the 7 th time slot in the continuous 8 time slots.
The network equipment maps ss block1 in ss burst k +1 to the 2 nd-5 th symbol of the 2 nd time slot in the continuous 8 time slots, maps ss block2 in ss burst k +1 to the 2 nd-5 th symbol of the 4 th time slot in the continuous 8 time slots, maps ss block 3 in ss burst k +1 to the 2 nd-5 th symbol of the 6 th time slot in the continuous 8 time slots, and maps ss block4 in ss burst k +1 to the 2 nd-5 th symbol of the 8 th time slot in the continuous 8 time slots.
In fig. 6, the 8 slots for transmitting ss burst k and ss burst k +1 occupy the first 4ms of a ss burst set transmission period in total, and are indicated by shading. Fig. 6 illustrates an example of the transmission period of ss burst set as 20ms, and it is understood that the transmission period of ss burst set can be configured as 5ms, 10ms, 40ms, 80ms, 160ms, etc.
The resource mapping scheme provided in fig. 7 is applicable to a scenario in which a slot used by the communication system includes 14 symbols. The network device maps the second synchronization signal block packet and the first synchronization signal block packet onto different symbols in the same 4 slots. A specific resource mapping manner is described below with ss burst as an example of a synchronization signal block grouping, and it can be understood that in the case that a time slot used by the communication system contains 14 symbols, the subcarrier spacing supported by the communication system on the frequency domain may be 15kHz, 30kHz, 120kHz, or 240 kHz.
As shown in fig. 7, slot i to slot i +3 represent 4 consecutive slots. The network equipment maps ss block1 in ss burst k on the 2 nd to 5 th symbols of the 1 st time slot in the continuous 4 time slots, maps ss block2 in ss burst k on the 2 nd to 5 th symbols of the 2 nd time slot in the continuous 4 time slots, maps ss block 3 in ss burst k on the 2 nd to 5 th symbols of the 3 rd time slot in the continuous 4 time slots, and maps ss block4 in ss burst k on the 2 nd to 5 th symbols of the 4 th time slot in the continuous 4 time slots.
The network equipment maps ss block1 in ss burst k +1 to the 9 th-12 th symbol of the 1 st time slot in the continuous 4 time slots, maps ss block2 in ss burst k +1 to the 9 th-12 th symbol of the 2 nd time slot in the continuous 4 time slots, maps ss block 3 in ss burst k +1 to the 9 th-12 th symbol of the 3 rd time slot in the continuous 4 time slots, and maps ss block4 in ss burst k +1 to the 9 th-12 th symbol of the 4 th time slot in the continuous 4 time slots.
The 4 slots used for transmission of ss burst k and ss burst k +1 in fig. 7 occupy the first 4ms of a ss burst set transmission period in total, and are indicated by shading. Fig. 7 illustrates an example of a transmission period of ss burst set as 20ms, and it is understood that the transmission period of ss burst set may be configured as 5ms, 10ms, 40ms, 80ms, or 160 ms.
As can be seen from the mapping manners shown in fig. 6 and fig. 7, after the resource mapping is completed, the number of symbols that are different between the synchronization signal blocks belonging to the same synchronization signal block group is even.
For example, for ss burst k in FIG. 6 or FIG. 7, ss block1 differs from ss block2 by 14 symbols, ss block1 differs from ss block 3 by 28 symbols, and ss block1 differs from ss block4 by 42 symbols. For ss burst k +1, ss block1 differs from ss block2 by 14 symbols, ss block1 differs from ss block 3 by 28 symbols, and ss block1 differs from ss block4 by 42 symbols.
However, the number of symbols of the phase difference between the respective sync signal blocks belonging to different sync signal block groups is odd. For example, ss block1 in ss burst k differs from ss block1 in ss burst k +1 by 7 symbols, ss block1 in ss burst k differs from ss block2 in ss burst k +1 by 21 symbols, ss block1 in ss burst k differs from ss block 3 in ss burst k +1 by 35 symbols, and ss block1 in ss burst k differs from ss block4 in ss burst k +1 by 49 symbols.
In the resource mapping scheme shown in fig. 6 and fig. 7, the number of symbols that differ between the synchronization signal blocks in the same synchronization signal block group belongs to a first set, and the values of the first set include: {14, 28, 42 }. The number of symbols of the phase difference between the synchronization signal blocks in different synchronization signal block groups belongs to a second set, and the values of the second set comprise: {7, 21, 35, 49 }.
The resource mapping schemes provided in fig. 6 and 7 belong to uniform mapping. The uniform mapping means that after the resource mapping is completed, the number of symbols that are different between any two adjacent ss blocks is a fixed value, for example, in fig. 6 and fig. 7, the number of symbols that are different between any two adjacent ss blocks is 7.
In the method for transmitting a synchronization signal provided in an embodiment of the present application, when a network device sends a first synchronization signal block packet and a second synchronization signal block packet, after resource mapping is completed, the number of symbols that are different between any 2 synchronization signal blocks in the mapped first synchronization signal block packet is an even number, the number of symbols that are spaced between any 2 synchronization signal blocks in the mapped second synchronization signal block packet is an even number, and the number of symbols that are spaced between one synchronization signal block in the mapped second synchronization signal block packet and one synchronization signal block in the mapped first synchronization signal block packet is an odd number. The mapping mode can ensure that when the terminal equipment receives the synchronous signal blocks, whether the two synchronous signal blocks belong to the same synchronous signal block group or not can be confirmed according to the number of the symbols of the phase difference between the two synchronous signal blocks, so that the soft combination processing is carried out on a plurality of synchronous signal blocks belonging to the same synchronous signal block group, and the signal processing flow is simplified.
The uniform mapping shown in fig. 6 and fig. 7 is only an example of resource mapping, and actually, the mapping method shown in fig. 6 or fig. 7 is slightly adjusted to be changed into the non-uniform mapping method, so long as the condition that the number of symbols that are different between any two synchronization signal blocks in the same synchronization signal block group belongs to a first set and the number of symbols that are different between synchronization signal blocks in different synchronization signal block groups belongs to a second set that is not overlapped with the first set is satisfied, the terminal device can still determine a plurality of synchronization signal blocks belonging to the same synchronization signal block group according to the number of symbols that are different between two synchronization signal blocks. For example, referring to fig. 8, the resource mapping manner shown in fig. 8 is to shift the symbols mapped by the second synchronization signal block by 1 bit after the symbols mapped by the second synchronization signal block are based on fig. 6. Thus, the number of symbols with phase difference between the synchronization signal blocks in the same synchronization signal block group belongs to the first set, and the value of the first set is still: {14, 28, 42 }. At this time, the number of symbols that are different between two sync signal blocks belonging to different sync signal block groups belongs to a second set, and the value of the second set is changed to: {8, 22, 36, 50 }. In the resource mapping scheme shown in fig. 8, although the values included in the first set and the second set are both even numbers, the values included in the first set and the second set do not overlap with each other.
For the terminal device, if the network device adopts the resource mapping manner shown in fig. 6 or fig. 7, after determining the number of symbols that detect the difference between the time domain resource of the first synchronization signal block and the time domain resource of the second synchronization signal block in step 52 in fig. 5, the terminal device determines that the first synchronization signal block and the second synchronization signal block belong to the same synchronization signal block group if the number of symbols that detect the difference belongs to the first set. The values in the first set are all even. Optionally, after determining the number of the phase difference symbols, the terminal device may adopt a simplified determination manner, that is, determine whether the number of the phase difference symbols is an even number. If the number of symbols of the difference is even, the terminal device determines that the first synchronization signal block and the second synchronization signal block belong to the same synchronization signal block group. If the number of symbols that differ is not even, it is determined that the first synchronization signal block and the second synchronization signal block belong to different synchronization signal block groups.
If the network device adopts the resource mapping manner shown in fig. 8, after determining the number of symbols that detect the difference between the time domain resource of the first synchronization signal block and the time domain resource of the second synchronization signal block in step 52 shown in fig. 5, the terminal device cannot directly determine whether the first synchronization signal block and the second synchronization signal block belong to the same synchronization signal block group according to whether the number of symbols that detect the difference is an even number, but needs to determine whether the number of symbols that detect the difference belongs to the first set: {14, 28, 42 }. If it belongs to the first set, it is determined that the first and second synchronization signal blocks belong to the same synchronization signal block group.
Fig. 9-14 are schematic diagrams of another resource mapping method provided in the embodiment of the present application. The resource mapping scheme shown in fig. 9 is applicable to a scenario in which a slot used by the communication system includes 7 symbols. The resource mapping schemes shown in fig. 10-14 are applicable to a scenario in which a slot used by the communication system contains 14 symbols. In the resource mapping manners shown in fig. 9-14, the number of symbols spaced between any two synchronization signal blocks in the same synchronization signal block group belongs to a first set, the number of symbols spaced between two synchronization signal blocks in different synchronization signal block groups belongs to a second set that does not overlap with the first set, and a value included in the first set is smaller than a predetermined threshold and a value included in the second set is larger than the predetermined threshold.
Fig. 9 is a schematic diagram of a resource mapping method according to an embodiment of the present application. The resource mapping scheme shown in fig. 9 is applicable to a scenario in which a slot used by the communication system includes 7 symbols. The network device maps the first synchronization signal block packet to 4 consecutive slots and the second synchronization signal block packet to another 4 consecutive slots, the two consecutive 4 slots being separated by 2 slots. In the following, ss burst is taken as an example of a synchronization signal block packet, and a description is given with reference to fig. 9 for a possible specific resource mapping manner, it can be understood that, in a case where a slot used by a communication system includes 7 symbols, the possible resource mapping manner is not limited to the mapping manner shown in fig. 9.
As shown in fig. 9, slot j to slot j +9 represent consecutive 10 slots. The ss block starts with the 1 st or 2 nd symbol of each slot. The network equipment maps ss block1 in ss burst k to the 2 nd-5 th symbol of the 1 st slot j in continuous 10 time slots, maps ss block2 in ss burst k to the 1 st-4 th symbol of the 2 nd slot j +1 in continuous 10 time slots, maps ss block 3 in ss burst k to the 2 nd-5 th symbol of the 3 rd slot j +2 in continuous 10 time slots, and maps ss block4 in ss burst k to the 1 st-4 th symbol of the 4 th slot j +3 in continuous 10 time slots.
The network equipment maps ss block1 in ss burst k +1 to the 2-5 th symbol of the 7 th slot j +6 in the continuous 10 time slots, maps ss block2 in ss burst k +1 to the 1-4 th symbol of the 8 th slot j +7 in the continuous 10 time slots, maps ss block 3 in ss burst k +1 to the 2-5 th symbol of the 9 th slot j +8 in the continuous 10 time slots, and maps ss block4 in ss burst k +1 to the 1-4 th symbol of the 10 th slot j +9 in the continuous 10 time slots.
In fig. 9, the 10 slots slot j to slot j +9 for transmitting ss burst k and ss burst k +1 occupy the first 2.5ms of a ss burst set transmission period in total and are indicated by shading. Fig. 9 illustrates an example of a transmission period of ss burst set as 20ms, and it is understood that the transmission period of ss burst set may be configured as 5ms, 10ms, 40ms, 80ms, or 160 ms.
In the case where the time slot used by the communication system is a time slot containing 14 symbols, the network device maps the first synchronization signal block packet to 2 consecutive time slots, and maps the second synchronization signal block packet to another 2 consecutive time slots, where the two consecutive 2 time slots are separated by 1 time slot. In the following, a specific resource mapping manner is described with reference to fig. 10 by taking ss burst as an example of a synchronization signal block packet, and it can be understood that, in the case that a slot used by a communication system includes 14 symbols, the possible resource mapping manner is not limited to the mapping manner shown in fig. 10.
As shown in fig. 10, slot i to slot i +4 represent consecutive 5 slots. The network equipment maps ss block1 in ss burst k to the 2 nd-5 th symbol of the 1 st slot i in the continuous 5 time slots, maps ss block2 in ss burst k to the 8 th-11 th symbol of the 1 st slot i in the continuous 5 time slots, maps ss block 3 in ss burst k to the 2 nd-5 th symbol of the 2 nd slot i +1 in the continuous 5 time slots, and maps ss block4 in ss burst k to the 8 th-11 th symbol of the 2 nd slot i +1 in the continuous 5 time slots.
The network equipment maps ss block1 in ss burst k +1 to the 2-5 th symbol of the 4 th slot i +3 in the 5 continuous time slots, maps ss block2 in ss burst k +1 to the 8-11 th symbol of the 4 th slot i +3 in the 5 continuous time slots, maps ss block 3 in ss burst k +1 to the 2-5 th symbol of the 5 th slot i +4 in the 5 continuous time slots, and maps ss block4 in ss burst k +1 to the 8-11 th symbol of the 5 th slot i +4 in the 5 continuous time slots.
The 5 slots slot i to slot i +4 used for transmission of ss burst k and ss burst k +1 in fig. 10 use the first 2.5ms in a ss burst set transmission period, indicated by shading. Fig. 10 illustrates an example of a transmission period of ss burst set as 20ms, and it is understood that the transmission period of ss burst set may be configured as 5ms, 10ms, 40ms, 80ms, or 160 ms.
As can be seen from the mapping shown in fig. 9 and 10, the predetermined threshold may be set to 21. After the resource mapping is completed, the number of symbols of the phase difference between the synchronous signal blocks belonging to the same synchronous signal block group is less than a preset threshold value. For example, for each sync signal block in ss burst k in FIG. 9 or FIG. 10, ss block1 differs from ss block2 by 6 symbols, ss block1 differs from ss block 3 by 14 symbols, and ss block1 differs from ss block4 by 20 symbols, all of which are less than the predetermined threshold 21. For each sync signal block in ss burst k +1 in FIG. 9 or FIG. 10, ss block1 differs from ss block2 by 6 symbols, ss block1 differs from ss block 3 by 14 symbols, and ss block1 differs from ss block4 by 20 symbols, all of which are less than the predetermined threshold 21.
However, the number of symbols that differ between the synchronization signal blocks belonging to different synchronization signal block groups exceeds a predetermined threshold. For example ss block4 in ss burst k in fig. 9 or fig. 10 is closest to ss block1 in ss burst k +1 by 22 symbols, exceeding the predetermined threshold 21.
The advantage of using the resource mapping shown in fig. 10 is that the communication system is not hindered to transmit data in the same frequency band using the resource mapping shown in fig. 9, thereby avoiding bringing in-band interference.
Optionally, similar to the application scenario of fig. 10, in the case that the timeslot used by the communication system is a timeslot including 14 symbols, there may be at least another 4 resource mapping manners. For the sake of simplicity, the resource mapping manner in one timeslot is only described as an example. The distribution among the plurality of slots in one synchronization signal pulse transmission period is similar to that of fig. 10. I.e. the first synchronization signal block packet is mapped onto 2 consecutive time slots and the second synchronization signal block packet is mapped onto another 2 consecutive time slots, the two consecutive 2 time slots being separated by 1 time slot. Wherein the resource mapping in each of the 1 st, 2 nd, 4 th and 5 th slots among the 5 consecutive slots is shown in fig. 11-14, respectively. Similarly to fig. 10, in the mapping schemes shown in fig. 11 to 14, the number of symbols spaced between any two synchronization signal blocks in the same synchronization signal block group belongs to a first set, the number of symbols spaced between two synchronization signal blocks in different synchronization signal block groups belongs to a second set which does not overlap with the first set, and the value included in the first set is smaller than a predetermined threshold, and the value included in the second set is larger than the predetermined threshold. Alternatively, the predetermined threshold may be set to 21.
As shown in fig. 11, the network device maps one ss block on the 2 nd to 5 th symbols in the slot and another ss block on the 7 th to 10 th symbols of the slot.
As shown in fig. 12, the network device maps one ss block on the 3 rd to 6 th symbols of the slot and another ss block on the 8 th to 11 th symbols of the slot.
As shown in fig. 13, the network device maps one ss block on the 3 rd to 6 th symbols of the slot and another ss block on the 7 th to 10 th symbols of the slot.
As shown in fig. 13, the network device maps one ss block on the 4 th-7 th symbols of the slot and another ss block on the 8 th-11 th symbols of the slot.
As can be seen from fig. 10 to 14, in a scenario where a slot of a communication system includes a frequency domain resource of 14 symbols, when a network device performs resource mapping, a non-uniform mapping manner may be adopted, that is, in one slot, a character position of ss-block mapping in a first half slot is different from a character position of ss-block mapping in a second half slot.
The resource mapping schemes shown in fig. 9-14 are applicable to communication systems with various frequency points, such as a communication system with a subcarrier spacing of 15kHz, a communication system with a subcarrier spacing of 30kHz, a communication system with a subcarrier spacing of 120kHz, and a communication system with a subcarrier spacing of 240 kHz. Further, the resource mapping schemes shown in fig. 9-14 are preferably applicable to communication systems with subcarrier spacing of 30 kHz. This is because the reason that the network device preferably adopts non-uniform mapping in the scene of 30kHz subcarrier spacing is mainly to meet the requirement of uplink/downlink switching (DL/UL switching). As shown in fig. 15, assuming that the synchronization signal resource mapping scheme shown in fig. 6 is still used to transmit the synchronization signal block packets in the scenario where the subcarrier spacing is 30kHz, when the data of 15kHz and the synchronization signal block of 30kHz coexist in the same frequency band, the network device does not have time to perform DL/UL switching operation. Therefore, if the synchronization signal resource mapping manner shown in fig. 6 is applied to a scene with a subcarrier spacing of 30kHz, in-band (intra-band) uplink and downlink interference will occur. Therefore, for the requirement of transmitting synchronization signals in a scenario where the subcarrier spacing is 30kHz and the time slot contains 14 symbols, at least 1 symbol is reserved at the beginning of each time slot and at least 3 symbols are reserved at the end of each time slot to avoid in-band interference. The resource mapping of the various synchronization signal blocks shown in fig. 10-14 can avoid inband interference.
It is considered that resource mapping for a synchronization signal block in the scenario where the slot contains 14 symbols does not prevent operation in the slot containing 7 symbols. Of the 5 resource mapping schemes shown in fig. 10-14, only the resource mapping scheme shown in fig. 10 allows DL/UL switching to be performed in a slot including 7 symbols.
For the terminal device, if the network device adopts the resource mapping manner shown in fig. 9-fig. 14, after determining the number of symbols that detect the difference between the time domain resource of the first synchronization signal block and the time domain resource of the second synchronization signal block in step 52 in fig. 5, the terminal device determines that the first synchronization signal block and the second synchronization signal block belong to the same synchronization signal block group if the number of symbols that detect the difference belongs to the first set. And all the numerical values in the first set are smaller than a preset threshold value. Therefore, after determining the number of the symbols with the phase difference, the terminal device may adopt a simplified judgment manner, that is, judge whether the number of the symbols with the phase difference exceeds a predetermined threshold. Since the threshold 21 is predetermined in the resource mapping schemes shown in fig. 10 to 14, accordingly, if the number of symbols that differ does not exceed the predetermined threshold, the terminal device determines that the first synchronization signal block and the second synchronization signal block belong to the same synchronization signal block group. If the number of symbols that differ exceeds a predetermined threshold, it is determined that the first and second synchronization signal blocks belong to different synchronization signal block groups.
Here, it should be noted that: the mapping manner of 2 sync signal blocks in one slot containing 7 symbols or one slot containing 14 symbols shown in fig. 9-14 can also be applied to other scenarios, and is not limited to the scenario shown in fig. 9 or 10 in which two sync signal blocks are mapped in ss burst set in a packet manner, i.e. not limited to the scenario of packet mapping. The mapping manner of separately mapping 2 synchronization signal blocks in one time slot may also be applied to a non-packet-mapped scenario, so as to solve other technical problems, such as how to reserve symbol resources for uplink and downlink control in one time slot.
Fig. 16-18 are schematic diagrams of another resource mapping scheme provided herein, respectively. Similar to the resource mapping schemes shown in fig. 10 to 14, in a scenario where a slot used by the communication system includes 14 symbols, when the network device performs resource mapping, 4 synchronization signal blocks in the first synchronization signal block packet are respectively mapped into 2 consecutive slots, and 4 synchronization signal blocks in the second synchronization signal block packet are respectively mapped into another 2 consecutive slots. In contrast to fig. 10-14, the two groups of consecutive slots are separated by 0 slots, i.e. the first and second synchronization signal block packets are mapped into 4 consecutive slots. The number of symbols at intervals between any two synchronization signal blocks in the same mapped synchronization signal block group belongs to a first set, the number of symbols at intervals between two synchronization signal blocks in different mapped synchronization signal block groups belongs to a second set which is not overlapped with the first set, a value contained in the first set is smaller than a preset threshold, and a value contained in the second set is larger than the preset threshold. The values of the predetermined threshold differ from the mapping schemes of fig. 9-14.
Fig. 16-17 illustrate possible mapping of a sync block from the perspective of mapping a sync block packet to 2 consecutive slots, respectively. Fig. 18 illustrates a resource mapping manner from the perspective of mapping two step signal block packets to one synchronization signal pulse transmission period.
The resource mapping scheme shown in fig. 16 to 18 is applicable to communication systems with various frequency points, for example, a communication system with a subcarrier spacing of 15kHz, a communication system with a subcarrier spacing of 30kHz, a communication system with a subcarrier spacing of 120kHz, and a communication system with a subcarrier spacing of 240 kHz. Further, the resource mapping schemes shown in fig. 16-18 are preferably applicable to communication systems with a subcarrier spacing of 240kHz and 14 symbols in a time slot. This is because, in a scenario where the subcarrier spacing of the communication system is 240kHz and the used time slot is a time slot including 14 symbols, for uplink and downlink control, it is necessary to reserve 4 symbols each at the start of the first time slot and at the end of the second time slot in two consecutive time slots (i.e., 28 consecutive symbols). In order to avoid uplink and downlink interference in the same frequency band, at least 6 symbols are reserved at the end of the second time slot of two continuous time slots after the time slot defined by the subcarrier with the interval of 240kHz is known.
Fig. 16 is a schematic diagram of a first mapping manner of a synchronization signal block packet according to an embodiment of the present application. The network device maps a first synchronization signal block in a synchronization signal block packet on the 5 th to 8 th symbols of a first time slot, maps a second synchronization signal block in the synchronization signal block packet on the 9 th to 12 th symbols of the first time slot, maps a third synchronization signal block in the synchronization signal block packet on the 13 th to 14 th symbols of the first time slot and the 1 st to 2 nd symbols of a second time slot, and maps a fourth synchronization signal block in the synchronization signal block packet on the 3 rd to 6 th symbols of the second time slot. I.e. one synchronization signal block packet is mapped in the consecutive 16 symbols starting from the 5 th symbol of the first slot.
Fig. 17 is a schematic diagram of a second mapping manner of a synchronization signal block packet according to an embodiment of the present application. The difference from fig. 16 is that one synchronization signal block packet is mapped in consecutive 16 symbols starting from the 7 th symbol of the first slot.
Fig. 18 is a schematic diagram of mapping two synchronization signal block packets into one synchronization signal pulse transmission period according to the embodiment of the present application. The network device maps two synchronization signal blocks into 4 consecutive slots slot i to slot i +3 in groups, maps the first synchronization signal block into the 1 st and 2 nd slots slot i to slot i +1 in 4 consecutive slots by using the mapping mode shown in fig. 16, and maps the second synchronization signal block into the 3 rd and 4 th slots slot i +2 to slot i +3 in 4 consecutive slots by using the mapping mode shown in fig. 17.
Fig. 18 uses ss burst as an example of a sync block packet. And mapping the ss block1 in the ss burst k on the 5 th-8 th symbol of the slot i, mapping the ss block2 in the ss burst k on the 9 th-12 th symbol of the slot i, mapping the ss block 3 in the ss burst k on the 13 th-14 th symbol of the slot i and the 1 st-2 th symbol of the slot i +1, and mapping the ss block4 in the ss burst k on the 3 rd-6 th symbol of the slot i + 1.
The method comprises the steps of mapping ss block1 in ss burst k +1 on the 7 th to 10 th symbols of slot i +2, mapping ss block2 in ss burst k +1 on the 11 th to 14 th symbols of slot i +2, mapping ss block 3 in ss burst k +1 on the 1 st to 4 th symbols of slot i +3, and mapping ss block4 in ss burst k +1 on the 5 th to 8 th symbols of slot i + 3.
As can be seen from the mapping shown in fig. 18, the predetermined threshold may be set to a positive integer greater than 12 and less than 18, for example, 14. After the resource mapping is completed, the number of symbols of the phase difference between the synchronous signal blocks belonging to the same synchronous signal block group is less than a preset threshold value. For example, for each sync signal block in ss burst k, ss block1 differs from ss block2 by 4 symbols, ss block1 differs from ss block 3 by 8 symbols, and ss block1 differs from ss block4 by 12 symbols, all of which are less than the predetermined threshold 21. For each sync signal block in ss burst k +1, ss block1 differs from ss block2 by 4 symbols, ss block1 differs from ss block 3 by 8 symbols, and ss block1 differs from ss block4 by 12 symbols, all of which are less than the predetermined threshold 14.
However, the number of symbols that differ between the synchronization signal blocks belonging to different synchronization signal block groups exceeds a predetermined threshold. For example ss block4 in ss burst k is closest to ss block1 in ss burst k +1 by 18 symbols, exceeding the predetermined threshold 14.
After the network device performs resource mapping on the synchronization signal block packet by sampling the resource mapping manners shown in fig. 16 to fig. 18, when the network device sends the synchronization signal pulse set, the network device sends the 4 consecutive slots slot i to slot i +3 used for transmitting the first synchronization signal block packet and the second synchronization signal block packet in the first 1 microsecond in the synchronization signal pulse set sending period, as shown by the shading. Fig. 18 illustrates an example of a transmission period of ss burst set as 20ms, and it is understood that the transmission period of ss burst set may be configured as 5ms, 10ms, 40ms, 80ms, or 160 ms.
For the terminal device, if the network device adopts the resource mapping manner shown in fig. 16-fig. 18, after determining the number of symbols that are different between the time domain resource in which the first synchronization signal block is detected and the time domain resource in which the second synchronization signal block is detected in step 52 in fig. 5, the terminal device determines that the first synchronization signal block and the second synchronization signal block belong to the same synchronization signal block group if the terminal device belongs to the first set. And all the numerical values in the first set are smaller than a preset threshold value.
Optionally, after determining the number of the symbols with the phase difference, the terminal device may adopt a simplified determination manner, that is, the terminal device determines whether the number of the symbols with the phase difference is smaller than a predetermined threshold. Since the predetermined threshold is a positive integer greater than 12 and less than 18, for example, 14, in the resource mapping schemes shown in fig. 16-18, accordingly, if the number of symbols that differ is less than the predetermined threshold, the terminal device determines that the first synchronization signal block and the second synchronization signal block belong to the same synchronization signal block group. And if the number of the symbols with the phase difference is larger than a preset threshold value, the terminal equipment determines that the first synchronous signal block and the second synchronous signal block belong to different synchronous signal block groups.
On the basis of fig. 18, it is also possible to construct a resource mapping manner for other synchronization signal blocks, for example, at least 1 slot is inserted between the 2 nd slot i +1 and the 3 rd slot i +2 in fig. 18. The value range of the predetermined threshold should also be changed adaptively, and is not listed here.
Fig. 19 is a flowchart of a synchronization signal transmission method according to an embodiment of the present application. Fig. 20-27 and fig. 30 are schematic diagrams of another resource mapping method provided in the embodiment of the present application, respectively. These resource mapping schemes are applicable to a scenario where a slot used by the communication system contains 14 symbols. Similar to fig. 6 to 8, the number of symbols that are different between any two synchronization signal blocks in the same synchronization signal block group in the resource mapping schemes shown in fig. 20 to 27 belongs to the first set, and the number of symbols that are different between two synchronization signal blocks in different synchronization signal block groups belongs to a second set in which the first set is not overlapped with each other. In contrast to fig. 6-8, the first set may contain both even and odd numbers, and the second set may contain both even and odd numbers, but the first and second sets do not contain the same values.
In particular, the resource mapping schemes shown in fig. 20-23 are applicable to a scenario in which a slot used by the communication system includes 14 symbols. The number of symbols which are different from each other and belong to the same synchronization signal block group after mapping belongs to a first set, and the first set comprises {4, 9, 13 and 17 }; the number of symbols that differ for each synchronization signal block belonging to different groups of synchronization signal blocks after mapping belongs to a second set comprising {11, 15, 19 }.
The resource mapping schemes shown in fig. 24-27 are applicable to a scenario in which a slot used by the communication system contains 14 symbols. The number of symbols which are different from each synchronization signal block belonging to the same synchronization signal block group after mapping belongs to a first set, and the first set comprises {4, 11, 15 and 19 }; the number of symbols that differ for each synchronization signal block belonging to different groups of synchronization signal blocks after mapping belongs to a second set comprising {9, 13, 17 }.
Example two
Fig. 19 is a flowchart of a method for transmitting a synchronization signal according to an embodiment of the present application. The flow chart describes the process of the network device, taking the base station as an example, transmitting the synchronization signal from the perspective of the base station. In the following embodiments of the present application, a base station is taken as an example to introduce the working principle and function of a network device.
Step 191, the base station generates a synchronization signal pulse, wherein the synchronization signal pulse comprises a first synchronization signal block, a second synchronization signal block, a third synchronization signal block, and a fourth synchronization signal block.
In the embodiment of the present application, a synchronization signal pulse includes at least 4 synchronization signal blocks, and a time domain resource of one synchronization signal pulse includes 2 slots. It should be noted that, one sync signal pulse may include more sync signal blocks, such as 6 sync signal blocks and 8 sync signal blocks, and the resource locations mapped by 4 sync signal blocks among them are within the protection scope of the present application as long as they meet the requirements in the embodiments of the present application.
Step 192, the base station continuously transmits the first synchronization signal block and the second synchronization signal block in a first time slot, and continuously transmits the third synchronization signal block and the fourth synchronization signal block in a second time slot. In this application, continuous transmission refers to transmission through continuous OFDM symbols.
The first synchronization signal block is mapped to a first resource, the second synchronization signal block is mapped to a second resource, the third synchronization signal block is mapped to a third resource, the fourth synchronization signal block is mapped to a fourth resource, the position of the first resource in the first time slot is different from the position of the third resource in the second time slot, and the position of the second resource in the first time slot is different from the position of the fourth resource in the second time slot.
Optionally, the first time slot and the second time slot are consecutive time slots.
According to the method for transmitting the synchronous signals, when the base station sends a plurality of SS blocks in the same SS burst, the plurality of SS blocks are mapped on different resource positions in different slots. When the UE receives the SS blocks, after determining that the plurality of SS blocks belong to the same SS burst according to the resource positions of the SS blocks in the slots, simplifying the information in the plurality of SS blocks, thereby improving the performance of the communication system.
Fig. 20 is a schematic diagram of a resource mapping when a base station transmits an SS block according to an embodiment of the present application. There are 2 SS bursts as shown in FIG. 20, denoted as SS burst k and SS burst k + 1. Wherein, slot i and slot j are two slots in SS burst k, and slot m and slot n are two slots in SS burst k + 1. The slot i and the slot j may be two consecutive slots or may not be two consecutive slots, and in this example, only the slot i and the slot j are two consecutive slots for illustration.
And 4 SS blocks are transmitted in each SS burst and are respectively marked as SS block1, SS block2, SS block 3 and SS block 4. For an SS burst, the system information, synchronization information, and other information in 4 SS blocks transmitted in the SS burst are the same. The system information, the synchronization information and other information in the SS block transmitted in different SS bursts are different. For example, the above information is the same in 4 SS blocks in SS burst k, but the above information is different for SS block1 in SS burst k and SS block1 in SS burst k + 1.
Taking SS burst k as an example, slot i and slot j are two consecutive slots. Wherein SS block1 and SS block2 are transmitted on 8 continuous symbols on slot i, and SS block 3 and SS block4 are transmitted on 8 continuous symbols on slot j. Optionally, SS block1 is sent on the 4 th to 7 th symbols of slot i, and SS block2 is sent on the 8 th to 11 th symbols of slot i. SS block 3 is sent on the 3 rd to 6 th symbols of slot j, and SS block4 is sent on the 7 th to 10 th symbols of slot j.
PSS, SSs and PBCH are included in one SS block. Optionally, there may be multiple ways to order the OFDM symbols respectively corresponding to PSS, SSS and PBCH.
As shown in fig. 20, PSS in SS block1 is transmitted on the 4 th symbol of slot i, SSs of SS block1 is transmitted on the 5 th symbol of slot i, and PBCH of SS block1 is transmitted on the 6 th to 7 th symbols of slot i. PSS in SS block2 is sent on the 8 th symbol of slot i, SSS of SS block1 is sent on the 9 th symbol of slot i, and PBCH of SS block1 is sent on the 10 th-11 th symbol of slot i.
PSS in SS block 3 is sent on the 3 rd symbol of slot j, SSS of SS block 3 is sent on the 4 th symbol of slot i, and PBCH of SS block 3 is sent on the 5 th-6 th symbol of slot i. PSS in SS block4 is sent on the 7 th symbol of slot j, SSS of SS block4 is sent on the 8 th symbol of slot i, and PBCH of SS block4 is sent on the 9 th to 10 th symbols of slot i.
The resource mapping of 4 SS blocks in SS burst k +1 is substantially similar to that of SS burst k, please refer to fig. 20.
Therefore, when the UE detects the synchronization signal blocks, it can determine whether different synchronization signal blocks belong to the same SS burst according to the symbol positions between different synchronization signal blocks. Still taking the resource mapping manner of fig. 20 as an example, the PSS in SS block1 in SS burst k is 4 symbols away from the PSS in SS block2 in SS burst k, the PSS in SS block1 in SS burst k is 13 symbols away from the PSS in SS block 3 in SS burst k, and the PSS in SS block1 in SS burst k is 17 symbols away from the PSS in SS block4 in SS burst k. The PSS in SS block2 in SS burst k is 9 symbols away from the PSS in SS block 3 in SS burst k. In other words, two sync signal blocks belong to the same SS burst if the phase difference between the two sync signal blocks is 4, 9, 13, 17 symbols. Two synchronization signal blocks belong to different SS bursts if the number of symbols apart between the two synchronization signal blocks is not any of 4, 9, 13, 17.
Again taking the resource mapping scheme of fig. 20 as an example, the above conclusion is verified by the number of symbols spaced between the sync signal blocks in different SS bursts. The PSS in SS block 3 in SS burst k is 15 symbols away from the PSS in SS block1 in SS burst k +1, the PSS in SS block 3 in SS burst k is 19 symbols away from the PSS in SS block2 in SS burst k +1, the PSS in SS block4 in SS burst k is 11 symbols away from the PSS in SS block1 in SS burst k +1, and the PSS in SS block4 in SS burst k is 15 symbols away from the PSS in SS block2 in SS burst k + 1. It can be seen that in fig. 20, the synchronization signal blocks in different SS bursts differ from each other by 11, 15, 19, which are different from any of the above 4, 9, 13, 17.
Fig. 20 is a schematic diagram of a resource mapping manner provided by taking the first sorting manner as an example. The first sorting mode is that in one SS block, PSS occupies the 1 st symbol, SSS occupies the 2 nd symbol, and PBCH occupies the 3 rd to 4 th symbols.
FIG. 21 is a schematic diagram of a resource mapping method provided by taking a second sorting method as an example. The second sorting mode is that in one SS block, PSS occupies the 1 st symbol, SSs occupies the 3 rd symbol, and PBCH occupies the 2 nd and 4 th symbols. Fig. 21 is different from fig. 20 only in the way of ordering the symbols occupied by various signals in one SS block, and the mapping way of each SS block in the same SS burst and the number of symbols spaced between each SS block are the same as those in fig. 20, and are not repeated here.
FIG. 22 is a schematic diagram of a resource mapping method provided by taking a third sorting method as an example. The third sorting mode is that in one SS block, PSS occupies the 2 nd symbol, SSs occupies the 3 rd symbol, and PBCH occupies the 1 st and 4 th symbols. Fig. 22 is different from fig. 20 in the way of ordering the symbols occupied by various signals in only one SS block, and the mapping way of each SS block in the same SS burst and the number of symbols spaced between each SS block are the same as those in fig. 20, and are not repeated here.
FIG. 23 is a schematic diagram of a resource mapping method provided by taking a fourth sorting method as an example. The fourth ordering mode is that in one SS block, PSS occupies the 1 st symbol, SSs occupies the 4 th symbol, and PBCH occupies the 2 nd and 3 rd symbols. Fig. 22 is different from fig. 20 in the way of ordering the symbols occupied by various signals in only one SS block, and the mapping way of each SS block in the same SS burst and the number of symbols spaced between each SS block are the same as those in fig. 20, and are not repeated here.
Fig. 24 is a schematic diagram of resource mapping when a base station transmits an SS block according to an embodiment of the present application. There are 2 SS bursts as shown in FIG. 24, denoted as SS burst k and SS burst k + 1. Wherein, slot i and slot j are two slots in SS burst k, and slot m and slot n are two slots in SS burst k + 1.
And 4 SS blocks are transmitted in each SS burst and are respectively marked as SS block1, SS block2, SS block 3 and SS block 4. For an SS burst, the system information, synchronization information, and other information in 4 SS blocks transmitted in the SS burst are the same. The system information, synchronization information and other information of the SS block transmitted in different SS bursts are different. For example, the above information is the same in 4 SS blocks in SS burst k, and the above information is different in SS block1 in SS burst k and SS block1 in SS burst k + 1.
Taking SS burst k as an example, slot i and slot j are two consecutive slots. Wherein SS block1 and SS block2 are transmitted on 8 continuous symbols on slot i, and SS block 3 and SS block4 are transmitted on 8 continuous symbols on slot j. Optionally, SS block1 is sent on the 3 rd to 6 th symbols of slot i, and SS block2 is sent on the 7 th to 10 th symbols of slot i. SS block 3 is sent on the 4 th to 7 th symbols of slot j, and SS block4 is sent on the 8 th to 11 th symbols of slot j.
PSS, SSs and PBCH are included in one SS block. Optionally, there may be multiple ways to order the OFDM symbols respectively corresponding to PSS, SSS and PBCH.
As shown in fig. 24, PSS in SS block1 is transmitted on the 3 rd symbol of slot i, SSs of SS block1 is transmitted on the 4 th symbol of slot i, and PBCH of SS block1 is transmitted on the 5 th to 6 th symbols of slot i. PSS in SS block2 is sent on the 7 th symbol of slot i, SSS of SS block1 is sent on the 8 th symbol of slot i, and PBCH of SS block1 is sent on the 9 th to 10 th symbols of slot i.
PSS in SS block 3 is sent on the 4 th symbol of slot j, SSS of SS block 3 is sent on the 5 th symbol of slot i, and PBCH of SS block 3 is sent on the 6 th-7 th symbol of slot i. PSS in SS block4 is sent on the 8 th symbol of slot j, SSS of SS block4 is sent on the 9 th symbol of slot i, and PBCH of SS block4 is sent on the 10 th-11 th symbol of slot i.
The resource mapping of 4 SS blocks in SS burst k +1 is substantially similar to that of SS burst k, please refer to fig. 24.
Therefore, when the UE detects the synchronization signal blocks, it can determine whether different synchronization signal blocks belong to the same SS burst according to the symbol positions between different synchronization signal blocks. Still taking the resource mapping manner of fig. 24 as an example, the PSS in SS burst1 in SS burst k is 4 symbols away from the PSS in SS burst 2 in SS burst k, the PSS in SS burst1 in SS burst k is 15 symbols away from the PSS in SS burst 3 in SS burst k, and the PSS in SS burst1 in SS burst k is 19 symbols away from the PSS in SS burst 4 in SS burst k. The PSS in SS burst 2 in SS burst k is 11 symbols away from the PSS in SS burst 3 in SS burst k. In other words, two sync signal blocks belong to the same SS burst if they differ by 4, 11, 15, or 19 symbols. Two synchronization signal blocks belong to different SS bursts if the number of symbols apart between the two synchronization signal blocks is not any of 4, 11, 15, 19.
Again taking the resource mapping scheme of fig. 24 as an example, the above conclusion is verified by the number of symbols spaced between the sync signal blocks in different SS bursts. The PSS in SS burst 3 in SS burst k is 13 symbols away from the PSS in SS burst1 in SS burst k +1, the PSS in SS burst 3 in SS burst k is 17 symbols away from the PSS in SS burst 2 in SS burst k +1, the PSS in SS burst 4 in SS burst k is 9 symbols away from the PSS in SS burst1 in SS burst k +1, and the PSS in SS burst 4 in SS burst k is 13 symbols away from the PSS in SS burst 2 in SS burst k + 1. It can be seen that in fig. 24, the sync signal blocks in different SS bursts are separated by 9, 13, 17, which is different from any of the above 4, 11, 15, 19.
FIG. 24 is a schematic diagram of a resource mapping method provided by taking the first sorting method as an example. The first sorting mode is that in one SS block, PSS occupies the 1 st symbol, SSS occupies the 2 nd symbol, and PBCH occupies the 3 rd to 4 th symbols.
FIG. 25 is a schematic diagram of a resource mapping method provided by taking a second sorting method as an example. The second sorting mode is that in one SS block, PSS occupies the 1 st symbol, SSs occupies the 3 rd symbol, and PBCH occupies the 2 nd and 4 th symbols. Fig. 25 is different from fig. 24 in the way of ordering the symbols occupied by various signals in only one SS block, and the mapping way of each SS block in the same SS burst and the number of symbols spaced between each SS block are the same as those in fig. 24, and are not repeated here.
FIG. 26 is a schematic diagram of a resource mapping method provided by taking a third sorting method as an example. The third sorting mode is that in one SS block, PSS occupies the 2 nd symbol, SSs occupies the 3 rd symbol, and PBCH occupies the 1 st and 4 th symbols. Fig. 26 is different from fig. 24 in the way of ordering the symbols occupied by various signals in only one SS block, and the mapping way of each SS block in the same SS burst and the number of symbols spaced between each SS block are the same as those in fig. 24, and are not repeated here.
FIG. 27 is a schematic diagram of a resource mapping method provided by taking a fourth sorting method as an example. The fourth ordering mode is that in one SS block, PSS occupies the 1 st symbol, SSs occupies the 4 th symbol, and PBCH occupies the 2 nd and 3 rd symbols. Fig. 27 is different from fig. 24 in the way of ordering the symbols occupied by various signals in only one SS block, and the mapping way of each SS block in the same SS burst and the number of symbols spaced between each SS block are the same as those in fig. 24, and are not repeated here.
Fig. 28 is a flowchart of a method for transmitting a synchronization signal according to an embodiment of the present application. The flowchart describes a procedure of receiving a synchronization signal by a terminal device, taking the UE as an example, from the perspective of the UE. In the following embodiments of the present application, a base station is taken as an example to introduce the working principle and function of a network device.
In step 281, the UE detects a synchronization signal pulse, wherein the synchronization signal pulse includes a first synchronization signal block, a second synchronization signal block, a third synchronization signal block, and a fourth synchronization signal block.
The first and second synchronization signal blocks are transmitted continuously over a first time slot, and the third and fourth synchronization signal blocks are transmitted continuously over a second time slot. In this application, continuous transmission refers to transmission through consecutive OFDM symbols.
Wherein the first synchronization signal block is mapped to a first resource, the second synchronization signal block is mapped to a second resource, the third synchronization signal block is mapped to a third resource, the fourth synchronization signal block is mapped to a fourth resource, the first resource is located in a first time slot at a different position than the third resource is located in a second time slot, and the second resource is located in the first time slot at a different position than the fourth resource is located in the second time slot.
Optionally, the first time slot and the second time slot are consecutive time slots.
For the specific resource mapping manner of each synchronization signal block in the SS burst, please refer to the description in the previous embodiment, which is not repeated here.
In step 282, the UE acquires the signal in the synchronization signal pulse.
Optionally, the UE determines whether two synchronization signal blocks belong to the same SS burst according to the number of symbols separated between different synchronization signal blocks when receiving the synchronization signal blocks, so as to obtain multiple synchronization signal blocks belonging to the same SS burst. The simplified processing is performed on a plurality of synchronization signal blocks belonging to the same SS burst, for example, each synchronization signal block is demodulated separately, soft bit data obtained by demodulation is combined, and the combined result is decoded, thereby obtaining information included in each synchronization signal block, such as system information, sequencing of the synchronization signal blocks, and the like. The ordering here may be a sequence number in the SS burst.
The UE determines whether two synchronization signal blocks belong to SS burst or not, please refer to the description in the previous embodiment. For example, assuming that the resource mapping manner is shown in fig. 20, if the difference between two synchronization signal blocks is 4, 9, 13, or 17 symbols, the two synchronization signal blocks belong to the same SS burst; two synchronization signal blocks belong to different SS bursts if the number of symbols of the phase difference between the two synchronization signal blocks is not any of 4, 9, 13, or 17. For example, assuming that the resource mapping manner is shown in fig. 24, if the difference between two synchronization signal blocks is 4, 11, 15, or 19 symbols, the two synchronization signal blocks belong to the same SS burst; two synchronization signal blocks belong to different SS bursts if the number of symbols of the phase difference between the two synchronization signal blocks is not any of 4, 11, 15, 19.
In the method for transmitting synchronization signals provided in the embodiment of the present application, when receiving multiple SS blocks, a UE determines whether two synchronization signal blocks belong to the same SS burst according to a resource location between any two synchronization signal blocks, for example, a number of symbols that differ between any two synchronization signal blocks. So that the UE can perform subsequent simplified signal processing according to the confirmation result, thereby improving the performance of the communication system.
The resource mapping scheme shown in fig. 20 to 27 is applied to communication systems with various frequency points, for example, a communication system with a subcarrier spacing of 15kHz, a communication system with a subcarrier spacing of 30kHz, a communication system with a subcarrier spacing of 120kHz, and a communication system with a subcarrier spacing of 240 kHz. Further, the resource mapping schemes shown in fig. 20-27 are preferably applicable to communication systems where the subcarrier spacing is 120kHz and the time slot contains 14 symbols. This is because in a scenario where the subcarrier spacing is 120kHz and the slot contains 14 symbols, at least 2 symbols need to be reserved at the beginning and end of the slot in order to guarantee uplink and downlink control. However, as shown in fig. 29, in order to avoid uplink and downlink interference between data with a subcarrier spacing of 60kHz and a synchronization signal with a subcarrier spacing of 120kHz in the same frequency band, at least 3 slots need to be reserved at the end of a slot with a subcarrier spacing of 120 kHz. Thus for the resource mapping scheme of 5 sync signal blocks in a slot containing 14 symbols as shown in fig. 10-14, the scheme shown in fig. 12-14 satisfies this requirement. Furthermore, the schemes shown in fig. 13-14 further meet the power saving requirements since power can be saved by transmitting two synchronization signal blocks in series. Therefore, the resource mapping schemes shown in fig. 20 to 27 obtained by applying the resource mapping schemes in the time slots shown in fig. 13 to 14 to the synchronization signal pulse including a plurality of time slots are the resource mapping schemes meeting the requirements of interference resistance and energy saving at the same time.
Further, referring to fig. 30, after the network device performs resource mapping on the synchronization signal block packets by using the resource mapping method shown in fig. 20 to 27, when the network device transmits the synchronization signal burst set, the network device transmits the 4 consecutive time slots for transmitting the first synchronization signal block packet and the second synchronization signal block packet in the first 1 microsecond of the synchronization signal burst set, as shown by the hatching. Fig. 30 illustrates an example of a transmission period of ss burst set as 20ms, and it is understood that the transmission period of ss burst set can be configured as 5ms, 10ms, 40ms, 80ms, or 160 ms.
EXAMPLE III
The embodiment of the application also provides network equipment. Illustratively, the network device may be a base station. The structure and function of the network device will be described with reference to fig. 31 as an example of a base station. Fig. 31 is a schematic structural diagram of a network device that implements the functions of the network devices in the above embodiments and the fourth embodiment as the network device in fig. 4. As shown in fig. 31, the network device includes a transceiver 311 and a processor 312.
Alternatively, the transceiver 311 may be referred to as a Remote Radio Unit (RRU), a transceiver unit, a transceiver, or a transceiver circuit, etc. The transceiver 311 may include at least one antenna 3111 and a radio frequency unit 3112, and the transceiver 311 may be used for transceiving radio frequency signals and converting the radio frequency signals to baseband signals.
Optionally, the network device includes one or more baseband units (BBU) 313. The baseband unit includes a processor 312. The baseband unit 313 is mainly used for performing baseband processing, such as channel coding, multiplexing, modulation, spreading, and the like, and controlling the base station. The transceiver 311 and the baseband unit 313 may be physically located together or may be physically located separately, i.e., distributed base stations.
In an example, the baseband unit 313 may be formed by one or more boards, and the boards may support a radio access network of a single access system together, or may support radio access networks of different access systems respectively. The baseband unit 313 includes a processor 312. The processor 312 may be used to control the network device to perform the corresponding operations in the foregoing method embodiments. Optionally, the baseband unit 313 may further include a memory 314 to store necessary instructions and data.
The processor 312 is configured to generate a first synchronization signal block packet and a second synchronization signal block packet, where the first synchronization signal block packet includes m synchronization signal blocks, and the second synchronization signal block packet includes n synchronization signal blocks, where m and n are positive integers greater than or equal to 2.
The processor 312 is further configured to map m synchronization signal blocks in the first synchronization signal block packet into x symbols, where x is 7m, and the number of symbols that are different between any two synchronization signal blocks in the mapped first synchronization signal block packet belongs to a first set.
And mapping n synchronization signal blocks in the second synchronization signal block group to another y symbols, wherein y is 7n, the number of symbols which are different between any two synchronization signal blocks in the mapped second synchronization signal block group belongs to the first set, the number of symbols which are different between one synchronization signal block in the mapped second synchronization signal block group and one synchronization signal block in the mapped first synchronization signal block group belongs to a second set, and the numerical value in the second set is not overlapped with the numerical value in the first set.
The transceiver 311 is configured to transmit the synchronization signal blocks in the first synchronization signal block packet and the synchronization signal blocks in the second synchronization signal block packet through the time-frequency resources mapped by the processor.
Optionally, m and n have values of 4, and x and y have values of 28.
Optionally, when the number included in the first set is an even number and the number included in the second set is an odd number, the processor 312 performs resource mapping on the synchronization signal blocks in the first synchronization signal block group and the synchronization signal blocks in the second synchronization signal block group by using the uniform mapping manner shown in fig. 6 or fig. 7. With specific reference to the description of the previous method embodiments, it is not repeated here.
Alternatively, when the first set may include both even numbers and odd numbers, the second set may include both even numbers and odd numbers, but the first set and the second set do not include the same values, for example, the first set includes {4, 9, 13, 17}, and the second set includes {11, 15, 19}, the processor 312 performs resource mapping on the synchronization signal blocks in the first synchronization signal block group and the synchronization signal blocks in the second synchronization signal block group by using the resource mapping manner shown in fig. 20 to 27 in the second embodiment of the above method. With specific reference to the description of the previous method embodiments, it is not repeated here.
Alternatively, when the first set may include both even numbers and odd numbers, the second set may include both even numbers and odd numbers, and the values included in the first set are smaller than the predetermined threshold and the values included in the second set are larger than the predetermined threshold, the processor 312 performs resource mapping on the synchronization signal blocks in the first synchronization signal block group and the synchronization signal blocks in the second synchronization signal block group by using the resource mapping manner shown in fig. 9-14. With specific reference to the description of the previous method embodiments, it is not repeated here.
For a more detailed procedure of sending the synchronization signal by the network device, please refer to the foregoing method embodiments and the description in the fourth embodiment, which are not repeated here.
The embodiment of the present application further provides a network device, which is illustratively a base station. The structure and function of the network device will be described with reference to fig. 32, which is taken as an example of a base station. Fig. 32 is a schematic structural diagram of a network device, which serves as the network device in fig. 4 and has the functions of the network device in the method embodiment. As shown in fig. 32, the network device includes a transceiving unit 321 and a processing unit 322. The transceiver 321 and the processing unit 322 may be implemented by software or hardware. In the case of a hardware implementation, the transceiver 321 may be the transceiver 311 in fig. 31, and the processing unit 322 may be the processor 312 in fig. 31.
The embodiment of the application provides a network device taking a base station as an example, and the network device performs resource mapping on two synchronous signal blocks by adopting a preset resource mapping mode after generating a first synchronous signal block packet and a second synchronous signal block packet. After mapping, the number of symbols that differ between two synchronization signal blocks in the same synchronization signal block grouping in the time domain belongs to the first set, while the number of symbols that differ between two synchronization signal blocks in different synchronization signal block groupings does not belong to the first set. Therefore, when the terminal equipment receives the synchronous signals and detects a plurality of synchronous signal blocks, whether the two synchronous signal blocks belong to the same synchronous signal block group or not can be confirmed according to the number of the symbols with the phase difference between the two synchronous signal blocks. The terminal equipment can then obtain a plurality of synchronous signal blocks belonging to the same synchronous signal block group and carry out simplified processing on the plurality of synchronous signal blocks belonging to the same synchronous signal block group, thereby simplifying the signal processing flow and shortening the time and processing resources consumed by processing the synchronous signal blocks. The terminal equipment can obtain the system information carried in the synchronous signal block more quickly, and the network access time is shortened.
The embodiment of the application also provides the terminal equipment. It should be understood that the terminal device may be the UE in the above method embodiments, and may have any functions of the UE in the method embodiments. Fig. 33 is a schematic structural diagram of a terminal device that implements the functions of the terminal devices shown in the above embodiments, and the fourth embodiment as the terminal device in fig. 5. As shown in fig. 33, the terminal device includes a processor 331 and a transceiver 332.
Optionally, the transceiver 332 may include a control circuit and an antenna, wherein the control circuit may be used for conversion of baseband signals and radio frequency signals and processing of radio frequency signals, and the antenna may be used for transceiving radio frequency signals.
Optionally, the apparatus may also comprise other main components of the terminal device, such as memory, input output means, etc.
The processor 331 is configured to process the communication protocol and the communication data, and control the entire terminal device, execute a software program, and process data of the software program, for example, to support the terminal device to perform corresponding operations in the foregoing method embodiments. The memory 333 is primarily used to store software programs and data. When the terminal device is powered on, the processor 331 can read the software program in the memory, interpret and execute the instructions of the software program, and process the data of the software program.
In one embodiment, the transceiver 332 is configured to detect the first synchronization signal block and the second synchronization signal block during a transmission period of one set of synchronization signal pulses.
The processor 331 is configured to determine a number of symbols of a phase difference between a time domain resource occupied by the first synchronization signal block and a time domain resource occupied by the second synchronization signal block. Determining that the first synchronization signal block and the second synchronization signal block belong to the same synchronization signal block group if the number of symbols that differ belongs to a predetermined set.
Optionally, the first and second synchronization signal blocks are determined to belong to different synchronization signal block groups if the number of symbols that differ does not belong to a predetermined set.
Optionally, corresponding to the resource mapping manners shown in fig. 6 to fig. 7 of the above method embodiments, the predetermined set is the first set in the method embodiments described in fig. 6 to fig. 7, and the value included in the predetermined set is an even number. Correspondingly, after determining the number of phase-difference symbols, the processor 331 may adopt a simplified determination manner, that is, determine whether the number of phase-difference symbols is an even number. If the number of symbols of the difference is even, the terminal device determines that the first synchronization signal block and the second synchronization signal block belong to the same synchronization signal block group. If the number of symbols that differ is not even, it is determined that the first synchronization signal block and the second synchronization signal block belong to different synchronization signal block groups.
Optionally, corresponding to the resource mapping manners shown in fig. 9-14 and 18 of the method embodiments, the predetermined set is the first set in the method embodiments described in fig. 9-14 and 18, and a value included in the predetermined set is smaller than the predetermined threshold. Correspondingly, the processor 331 may employ a simplified determination after determining the number of symbols that differ, i.e., determine whether the number of symbols that differ exceeds a predetermined threshold. If the number of symbols that differ does not exceed a predetermined threshold, the terminal device determines that the first synchronization signal block and the second synchronization signal block belong to the same synchronization signal block group. If the number of symbols that differ exceeds a predetermined threshold, it is determined that the first and second synchronization signal blocks belong to different synchronization signal block groups.
For a more detailed process of receiving the synchronization signal by the terminal device, please refer to the foregoing method embodiment and the description in the fourth embodiment, which are not repeated here.
The embodiment of the application also provides the terminal equipment. It should be understood that the terminal device may be the terminal device in each of the above method embodiments, and may have any function of the terminal device in each of the method embodiments. Fig. 34 is a schematic structural diagram of a terminal device, the base station processing unit 341 and the transceiver unit 342. The processing unit 341 and the transceiving unit 342 may be implemented by software or hardware. In the case of a hardware implementation, the processing unit 341 may be the processor 331 in fig. 33, and the transceiving unit 342 may be the transceiver 332 in fig. 33.
The embodiment of the application provides a terminal device, and when the terminal device detects a plurality of synchronous signal blocks in a sending period of a synchronous signal pulse set, whether the two synchronous signal blocks belong to the same synchronous signal block group can be determined according to whether the number of symbols with a phase difference between the two synchronous signal blocks belongs to a preset set, so that the plurality of synchronous signal blocks belonging to the same synchronous signal block group can be further obtained. The terminal device can perform a simplified signal processing flow for a plurality of subsequent synchronization signal blocks belonging to the same synchronization signal block group. Because the signal processing flow is simplified, the time and the processing resource for processing the synchronous signal block are shortened, the system information carried in the synchronous signal block can be obtained more quickly, and the network access time is shortened.
The embodiment of the invention also provides a communication system which comprises the network equipment and the terminal equipment in the embodiment. Please refer to the description in the previous embodiment for the functions of the network device and the terminal device and the detailed process of mutual information interaction.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
Example four
The first embodiment and the second embodiment provide a method for propagating a synchronization signal, and specifically provide a plurality of resource mapping modes of the synchronization signal block when the synchronization signal is transmitted and the first synchronization signal block packet and the second synchronization signal block packet respectively include 4 synchronization signal blocks. Namely, when the values of m and n are 4, the resource mapping modes of the synchronous signal block are multiple.
As described in the first and second embodiments, the method for propagating the synchronization signal shown in fig. 4 and 5 in the first embodiment is applicable to the case where m and n take other positive integers. In this embodiment, a resource mapping manner of a synchronization signal block when m and n take other values, for example, m and n take 8 values, will be described with reference to a plurality of drawings.
In step 42 of fig. 4, when m and n have values of 8, x and y have values of 56. In the case that the time slot used by the communication system is a time slot containing 14 symbols, when the network device transmits the first synchronization signal block packet and the second synchronization signal block packet, the first synchronization signal block packet is mapped onto 4 continuous time slots, and the second synchronization signal block packet is mapped onto another 4 continuous time slots, wherein the two groups of continuous 2 time slots are at least 1 time slot apart. The specific resource mapping is shown in fig. 35, fig. 36 and fig. 37.
In the case that 4 consecutive slots to which the first synchronization signal block packet is mapped are separated from 4 consecutive slots to which the second synchronization signal block packet is mapped by 1 slot, in order to ensure that after the resource mapping is completed, the number of symbols that are different between any 2 synchronization signal blocks in the same mapped synchronization signal block packet belongs to a first set, and the number of symbols that are different between synchronization signal blocks in different synchronization signal block packets belongs to a second set that does not overlap with the first set, as shown in fig. 35 and fig. 36.
One possible specific resource mapping manner is described below with ss burst as an example of a synchronization signal block packet, with reference to fig. 35. In this embodiment, the arrangement of the OFDM symbols in the SS block corresponding to the PSS, the SSS, and the PBCH respectively adopts the arrangement of the 2 nd in fig. 2, that is, the PSS occupies the 1 st symbol in the SS block, the SSS occupies the 3 rd symbol in the SS block, and the PBCH occupies the 2 nd and 4 th symbols in the SS block. Obviously, the arrangement of the OFDM symbols in the SS block corresponding to the PSS, the SSS, and the PBCH may adopt other arrangements shown in fig. 2, which is not illustrated here.
slots j to j +8 represent consecutive 9 slots. The network equipment maps ss burst k in 4 continuous time slots from slot j to slot j +3, and maps ss burst k +1 in 4 continuous time slots from slot j +5 to slot j + 8.
The network equipment maps ss block1 in ss burst k to the 3 rd to 6 th symbols of the 1 st slot j in the continuous 9 time slots, and maps ss block2 in ss burst k to the 7 th to 10 th symbols of the 1 st slot j in the continuous 9 time slots.
And mapping ss block 3 in ss burst k to the 3 rd to 6 th symbols of the 2 nd slot j +1 in the continuous 9 time slots, and mapping ss block4 in ss burst k to the 7 th to 10 th symbols of the 2 nd slot j +1 in the continuous 9 time slots.
And mapping ss block 5 in ss burst k to the 3 rd to 6 th symbols of the 3 rd slot j +2 in the 9 continuous slots, and mapping ss block 6 in ss burst k to the 7 th to 10 th symbols of the 3 rd slot j +2 in the 9 continuous slots.
The ss block7 in ss burst k is mapped on the 3 rd to 6 th symbols of the 4 th slot j +3 in the 9 consecutive slots, and the ss block 8 in ss burst k is mapped on the 7 th to 10 th symbols of the 4 th slot j +3 in the 9 consecutive slots.
The network equipment maps ss block1 in ss burst k +1 to the 4 th-7 th symbol of the 6 th slot j +5 in the continuous 9 time slots, and maps ss block2 in ss burst k +1 to the 8 th-11 th symbol of the 6 th slot j +5 in the continuous 9 time slots.
And mapping ss block 3 in ss burst k +1 to the 4 th-7 th symbol of the 7 th slot j +6 in the continuous 9 time slots, and mapping ss block4 in ss burst k +1 to the 8 th-11 th symbol of the 7 th slot j +6 in the continuous 9 time slots.
And mapping the ss block 5 in the ss burst k +1 to the 4 th-7 th symbol of the 8 th slot j +7 in the continuous 9 time slots, and mapping the ss block 6 in the ss burst k +1 to the 8 th-11 th symbol of the 8 th slot j +7 in the continuous 9 time slots.
And mapping the ss block7 in the ss burst k +1 to the 4 th-7 th symbol of the 9 th slot j +8 in the continuous 9 time slots, and mapping the ss block 8 in the ss burst k +1 to the 8 th-11 th symbol of the 9 th slot j +8 in the continuous 9 time slots.
As can be seen from the mapping manner shown in fig. 35, after the resource mapping is completed, the number of symbols of the phase difference between the synchronization signal blocks belonging to the same synchronization signal block group is even.
For example, for ss burst k in FIG. 35, ss block1 differs from ss block2 by 4 symbols, ss block1 differs from ss block 3 by 14 symbols, and ss block1 differs from ss block4 by 18 symbols. ss block2 differs from ss block4 by 10 symbols. ss block1 differs from ss block 5 by 28 symbols, and ss block1 differs from ss block 6 by 32 symbols. ss block1 differs from ss block7 by 42 symbols and ss block1 differs from ss block 8 by 46 symbols.
The number of symbols of the phase difference between each ss block in ss burst k +1 is similar to that of ss burst k, and is not repeated one by one.
However, the number of symbols of the phase difference between the respective sync signal blocks belonging to different sync signal block groups is odd. For example, ss block 5 in ss burst k differs from ss block1 in ss burst k +1 by 43 symbols, ss block1 in ss burst k differs from ss block2 in ss burst k +1 by 47 symbols, ss block7 in ss burst k differs from ss block1 in ss burst k +1 by 29 symbols, ss block 8 in ss burst k differs from ss block1 in ss burst k +1 by 25 symbols, ss block7 in ss burst k differs from ss block2 in ss burst k +1 by 33 symbols, ss block7 in ss burst k differs from block 3 in ss burst k +1 by 43 symbols, and ss block7 in ss burst k differs from ss block4 in ss burst k +1 by 47 symbols. Of course, the number of symbols of the phase difference between the synchronization signal blocks in different synchronization signal block groups may also be an odd number with a larger value, for example, ss block7 in ss burst k differs from ss block 5 in ss burst k +1 by 57 symbols, which is not further listed here.
In the resource mapping scheme shown in fig. 35, the number of symbols that differ between the synchronization signal blocks in the same synchronization signal block group belongs to a first set, and values of the first set include: {4, 10, 14, 18, 28, 32, 42, 46 }. The number of symbols of the phase difference between the synchronization signal blocks in different synchronization signal block groups belongs to a second set, and the values of the second set comprise: {25, 29, 33, 43, 47, 57 }.
For the terminal device, if the network device adopts the resource mapping manner shown in fig. 35, after determining the number of symbols that are different between the time domain resource in which the first synchronization signal block is detected and the time domain resource in which the second synchronization signal block is detected in step 52 in fig. 5, the terminal device determines that the first synchronization signal block and the second synchronization signal block belong to the same synchronization signal block group if the number of symbols that are different belongs to the first set. The values in the first set are all even. Optionally, after determining the number of the phase difference symbols, the terminal device may adopt a simplified determination manner, that is, determine whether the number of the phase difference symbols is an even number. If the number of symbols of the difference is even, the terminal device determines that the first synchronization signal block and the second synchronization signal block belong to the same synchronization signal block group. If the number of symbols that differ is not even, it is determined that the first synchronization signal block and the second synchronization signal block belong to different synchronization signal block groups.
Fig. 36 is a schematic diagram of another resource mapping manner provided in the embodiment of the present application. Unlike fig. 35, the first and second sets each contain an even number, but the values in the first and second sets do not overlap.
slots j to j +8 represent consecutive 9 slots. The network equipment maps ss burst k in 4 continuous time slots from slot j to slot j +3, and maps ss burst k +1 in 4 continuous time slots from slot j +5 to slot j + 8.
The network equipment maps ss block1 in ss burst k to the 7 th to 10 th symbols of the 1 st slot j in the continuous 9 time slots, and maps ss block2 in ss burst k to the 11 th to 14 th symbols of the 1 st slot j in the continuous 9 time slots.
And mapping ss block 3 in ss burst k to the 1 st to 4 th symbols of the 2 nd slot j +1 in the 9 continuous slots, and mapping ss block4 in ss burst k to the 5 th to 8 th symbols of the 2 nd slot j +1 in the 9 continuous slots.
And mapping ss block 5 in ss burst k to the 7 th-10 th symbol of the 3 rd slot j +2 in the continuous 9 time slots, and mapping ss block 6 in ss burst k to the 11 th-14 th symbol of the 3 rd slot j +2 in the continuous 9 time slots.
The ss block7 in ss burst k is mapped on the 1 st to 4 th symbols of the 4 th slot j +3 in the 9 consecutive slots, and the ss block 8 in ss burst k is mapped on the 5 th to 8 th symbols of the 4 th slot j +3 in the 9 consecutive slots.
The network equipment maps ss block1 in ss burst k +1 to the 7 th-10 th symbol of the 6 th slot j +5 in the continuous 9 time slots, and maps ss block2 in ss burst k +1 to the 11 th-14 th symbol of the 6 th slot j +5 in the continuous 9 time slots.
And mapping ss block 3 in ss burst k +1 to the 1-4 th symbol of the 7 th slot j +6 in the continuous 9 time slots, and mapping ss block4 in ss burst k +1 to the 5-8 th symbol of the 7 th slot j +6 in the continuous 9 time slots.
And mapping the ss block 5 in the ss burst k +1 to the 7 th-10 th symbol of the 8 th slot j +7 in the continuous 9 time slots, and mapping the ss block 6 in the ss burst k +1 to the 11 th-14 th symbol of the 8 th slot j +7 in the continuous 9 time slots.
And mapping the ss block7 in the ss burst k +1 to the 1-4 th symbol of the 9 th slot j +8 in the continuous 9 time slots, and mapping the ss block 8 in the ss burst k +1 to the 5-8 th symbol of the 9 th slot j +8 in the continuous 9 time slots.
As can be seen from the mapping manner shown in fig. 36, after the resource mapping is completed, the number of symbols of the phase difference between the synchronization signal blocks belonging to the same synchronization signal block group belongs to the first set.
For example, for ss burst k in fig. 36, ss block1 and ss block2 differ by 4 symbols, ss block1 and ss block 3 differ by 8 symbols, ss block1 and ss block4 differ by 12 symbols, ss block4 and ss block 5 differ by 16 symbols, ss block 3 and ss block7 differ by 28 symbols, ss block 3 and ss block 8 differ by 32 symbols, ss block1 and ss block7 differ by 36 symbols, and the distance between ss block1 and ss block 8 is farthest and differs by 40 symbols.
The number of symbols of the phase difference between each ss block in ss burst k +1 is similar to that of ss burst k, and is not repeated one by one.
The number of symbols belonging to the phase difference between the synchronization signal blocks in the different synchronization signal block groups belongs to the second set. For example, ss block 5 in ss burst k differs from ss block1 in ss burst k +1 by 42 symbols, ss block 6 in ss burst k differs from ss block1 in ss burst k +1 by 38 symbols, ss block7 in ss burst k differs from ss block1 in ss burst k +1 by 34 symbols, and ss block 8 in ss burst k differs from ss block1 in ss burst k +1 by 30 symbols. Of course, the number of symbols of the difference between the synchronization signal blocks in different synchronization signal block groups may also be other values larger than the above value, for example, ss block 5 in ss burst k is different from ss block2 in ss burst k +1 by 46 symbols, which is not listed here.
In the resource mapping shown in fig. 36, the number of symbols that differ between the synchronization signal blocks in the same synchronization signal block group belongs to a first set, and values of the first set include: {4, 8, 12, 16, 36, 40 }. The number of symbols of the phase difference between the synchronization signal blocks in different synchronization signal block groups belongs to a second set, and the values of the second set comprise: {30, 34, 38, 42 }.
For the terminal device, if the network device adopts the resource mapping manner shown in fig. 36, after determining the number of symbols that are different between the time domain resource in which the first synchronization signal block is detected and the time domain resource in which the second synchronization signal block is detected in step 52 in fig. 5, the terminal device determines that the first synchronization signal block and the second synchronization signal block belong to the same synchronization signal block group if the number of symbols that are different belongs to the first set.
Under the condition that a plurality of time slots are arranged between 4 continuous time slots mapped by a first synchronous signal block group and 4 continuous time slots mapped by a second synchronous signal block group, the number of symbols which are different between any 2 synchronous signal blocks in the same mapped synchronous signal block group belongs to a first set, the number of symbols which are different between the synchronous signal blocks in different synchronous signal block groups belongs to a second set which is not overlapped with the first set, the value in the first set is smaller than a set threshold value, and the value in the second set is larger than the set threshold value. The mapping manner of the first synchronization signal block grouping in 4 continuous time slots and the mapping manner of the second synchronization signal block grouping in the other 4 continuous time slots may not be limited. In other words, the first synchronization signal block in the first synchronization signal block packet may start at any symbol position in the first slot of the 4 consecutive slots, of which fig. 37 is only one example.
One possible specific resource mapping manner is described below with ss burst as an example of the synchronization signal block grouping, with reference to fig. 37. In this embodiment, the arrangement of the OFDM symbols in the SS block corresponding to the PSS, the SSS, and the PBCH respectively adopts the arrangement of the 2 nd in fig. 2, that is, the PSS occupies the 1 st symbol in the SS block, the SSS occupies the 3 rd symbol in the SS block, and the PBCH occupies the 2 nd and 4 th symbols in the SS block. Obviously, the arrangement of the OFDM symbols in the SS block corresponding to the PSS, the SSS, and the PBCH may adopt other arrangements shown in fig. 2, which is not illustrated here.
slots j to j +9 represent consecutive 10 slots. The network equipment maps ss burst k in 4 continuous time slots from slot j to slot j +3, and maps ss burst k +1 in 4 continuous time slots from slot j +6 to slot j + 9.
The network equipment maps ss block1 in ss burst k to the 7 th to 10 th symbols of the 1 st slot j in the 10 continuous slots, and maps ss block2 in ss burst k to the 11 th to 14 th symbols of the 1 st slot j in the 10 continuous slots.
And mapping ss block 3 in ss burst k to the 1 st to 4 th symbols of the 2 nd slot j +1 in the 10 continuous slots, and mapping ss block4 in ss burst k to the 5 th to 8 th symbols of the 2 nd slot j +1 in the 10 continuous slots.
And mapping ss block 5 in ss burst k to the 7 th to 10 th symbols of the 3 rd slot j +2 in the 10 continuous slots, and mapping ss block 6 in ss burst k to the 11 th to 14 th symbols of the 3 rd slot j +2 in the 10 continuous slots.
Ss block7 in ss burst k is mapped on the 1 st to 4 th symbols of the 4 th slot j +3 in 10 consecutive slots, and ss block 8 in ss burst k is mapped on the 5 th to 8 th symbols of the 4 th slot j +3 in 10 consecutive slots.
The network equipment maps ss block1 in ss burst k +1 to the 7 th-10 th symbol of the 7 th slot j +6 in the continuous 10 time slots, and maps ss block2 in ss burst k +1 to the 11 th-14 th symbol of the 7 th slot j +6 in the continuous 10 time slots.
And mapping ss block 3 in ss burst k +1 to the 1-4 th symbol of the 8 th slot j +7 in the 10 continuous slots, and mapping ss block4 in ss burst k +1 to the 5-8 th symbol of the 8 th slot j +7 in the 10 continuous slots.
And mapping the ss block 5 in the ss burst k +1 to the 7 th to 10 th symbols of the 9 th slot j +8 in the 10 continuous slots, and mapping the ss block 6 in the ss burst k +1 to the 11 th to 14 th symbols of the 9 th slot j +8 in the 10 continuous slots.
And mapping the ss block7 in the ss burst k +1 to the 1-4 th symbol of the 10 th slot j +9 in the 10 continuous slots, and mapping the ss block 8 in the ss burst k +1 to the 5-8 th symbol of the 10 th slot j +9 in the 10 continuous slots.
As can be seen from the mapping shown in fig. 37, the predetermined threshold may be set to a positive integer greater than 40 and less than 44, for example, 41. After the resource mapping is completed, the number of symbols of the phase difference between the synchronous signal blocks belonging to the same synchronous signal block group is less than a preset threshold value. For example, for each sync signal block in ss burst k in FIG. 37, ss block1 differs from ss block2 by 4 symbols, ss block1 differs from ss block 3 by 8 symbols, ss block1 differs from ss block4 by 12 symbols, ss block4 differs from ss block 5 by 16 symbols, ss block1 differs from ss block7 by 36 symbols, and the distance between ss block1 and ss block 8 is farthest by 40 symbols. That is, the values of the first set include: {4, 8, 12, 16, 36, 40}, each being less than a predetermined threshold 41.
For each sync signal block in ss burst k +1 in fig. 37, the number of symbols that differ between each ss block in ss burst k +1 is similar to ss burst k, and is not repeated here.
However, the number of symbols that differ between the synchronization signal blocks belonging to different synchronization signal block groups exceeds a predetermined threshold. For example, ss block7 in ss burst k in FIG. 37 differs by 48 symbols from ss block1 in ss burst k +1, and ss block 8 in ss burst k in FIG. 37 is closest to ss block1 in ss burst k +1, and both differ by 44 symbols. That is, the values of the second set include: 44, 48, both exceeding a predetermined threshold 41.
For the terminal device, if the network device adopts the resource mapping manner shown in fig. 37, after determining the number of symbols that are different between the time domain resource in which the first synchronization signal block is detected and the time domain resource in which the second synchronization signal block is detected in step 52 in fig. 5, the terminal device determines that the first synchronization signal block and the second synchronization signal block belong to the same synchronization signal block group if the number of symbols that are different belongs to the first set. And all the numerical values in the first set are smaller than a preset threshold value. Therefore, after determining the number of the symbols with the phase difference, the terminal device may adopt a simplified judgment manner, that is, judge whether the number of the symbols with the phase difference exceeds a predetermined threshold. Since the threshold 41 is predetermined in the resource mapping scheme shown in fig. 37, accordingly, if the number of symbols that differ does not exceed the predetermined threshold, the terminal device determines that the first synchronization signal block and the second synchronization signal block belong to the same synchronization signal block group. If the number of symbols that differ exceeds a predetermined threshold, it is determined that the first and second synchronization signal blocks belong to different synchronization signal block groups.
In the schemes of fig. 36 and 37, energy can be saved by continuously transmitting two synchronization signal blocks, and the energy saving requirement is further met.
The synchronization signal transmission methods shown in fig. 35, 36, and 37 are applicable to communication systems with various frequency points, for example, a communication system with a subcarrier spacing of 15kHz, a communication system with a subcarrier spacing of 30kHz, a communication system with a subcarrier spacing of 120kHz, and a communication system with a subcarrier spacing of 240 kHz.
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the invention to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website site, computer, server, or data center to another website site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (74)

1. A method of transmitting a synchronization signal, comprising:
the network equipment generates a first synchronous signal block packet and a second synchronous signal block packet, wherein the first synchronous signal block packet comprises m synchronous signal blocks, the second synchronous signal block packet comprises n synchronous signal blocks, and m and n are positive integers greater than or equal to 2;
mapping m synchronization signal blocks in the first synchronization signal block group into x symbols, wherein x is 7m, and the number of symbols with a difference between any two synchronization signal blocks in the mapped first synchronization signal block group belongs to a first set;
mapping n synchronization signal blocks in the second synchronization signal block group to y other symbols, where y is 7n, the number of symbols that are different between any two synchronization signal blocks in the mapped second synchronization signal block group belongs to the first set, the number of symbols that are different between one synchronization signal block in the mapped second synchronization signal block group and one synchronization signal block in the mapped first synchronization signal block group belongs to a second set, and a value in the second set does not overlap with a value in the first set;
and the network equipment transmits the synchronous signal blocks in the first synchronous signal block group and the synchronous signal blocks in the second synchronous signal block group through the mapped time-frequency resources.
2. The method of claim 1, wherein the values included in the first set are even numbers and the values included in the second set are odd numbers.
3. The method of claim 2, wherein m and n are 4 and x and y are 28.
4. The method of claim 3, wherein each slot comprises 7 symbols, and wherein mapping the m synchronization signal blocks in the first synchronization signal block grouping into x symbols comprises:
mapping a first synchronization signal block in the first synchronization signal block grouping on the 2 nd-5 th symbol of the 1 st slot in the continuous 8 slots, mapping a second synchronization signal block in the first synchronization signal block grouping on the 2 nd-5 th symbol of the 3 rd slot in the continuous 8 slots, mapping a third synchronization signal block in the first synchronization signal block grouping on the 2 nd-5 th symbol of the 5 th slot in the continuous 8 slots, mapping a fourth synchronization signal block in the first synchronization signal block grouping on the 2 nd-5 th symbol of the 7 th slot in the continuous 8 slots;
the mapping n synchronization signal blocks in the second synchronization signal block grouping into y further symbols comprises:
mapping a first synchronization signal block of the second synchronization signal block grouping on the 2 nd-5 th symbol of the 2 nd slot of the consecutive 8 slots, mapping a second synchronization signal block of the second synchronization signal block grouping on the 2 nd-5 th symbol of the 4 th slot of the consecutive 8 slots, mapping a third synchronization signal block of the second synchronization signal block grouping on the 2 nd-5 th symbol of the 6 th slot of the consecutive 8 slots, and mapping a fourth synchronization signal block of the second synchronization signal block grouping on the 2 nd-5 th symbol of the 8 th slot of the consecutive 8 slots.
5. The method of claim 3, wherein each slot comprises 14 symbols, and wherein mapping the m synchronization signal blocks in the first synchronization signal block grouping into x symbols comprises:
mapping a first synchronization signal block in the first synchronization signal block grouping on the 2 nd-5 th symbol of the 1 st slot in the consecutive 4 slots, mapping a second synchronization signal block in the first synchronization signal block grouping on the 2 nd-5 th symbol of the 2 nd slot in the consecutive 4 slots, mapping a third synchronization signal block in the first synchronization signal block grouping on the 2 nd-5 th symbol of the 3 rd slot in the consecutive 4 slots, mapping a fourth synchronization signal block in the first synchronization signal block grouping on the 2 nd-5 th symbol of the 4 th slot in the consecutive 4 slots;
the mapping n synchronization signal blocks in the second synchronization signal block grouping into y further symbols comprises:
mapping a first synchronization signal block of the second synchronization signal block grouping on the 9 th-12 th symbols of the 1 st slot of the consecutive 4 slots, mapping a second synchronization signal block of the second synchronization signal block grouping on the 9 th-12 th symbols of the 2 nd slot of the consecutive 4 slots, mapping a third synchronization signal block of the second synchronization signal block grouping on the 9 th-12 th symbols of the 3 rd slot of the consecutive 4 slots, and mapping a fourth synchronization signal block of the second synchronization signal block grouping on the 9 th-12 th symbols of the 4 th slot of the consecutive 4 slots.
6. The method according to claim 4 or 5, characterized in that the following values 14, 28, 42 are comprised in the first set and the following values 7, 21, 35, 49 are comprised in the second set.
7. The method of claim 2, wherein m and n are 8 and x and y are 56.
8. The method of claim 7, wherein each slot comprises 14 symbols, and wherein mapping the m synchronization signal blocks in the first synchronization signal block grouping into x symbols comprises:
mapping a first synchronization signal block in the first synchronization signal block packet on the 3 rd to 6 th symbols of the 1 st slot of the consecutive 9 slots, mapping a second synchronization signal block in the first synchronization signal block packet on the 7 th to 10 th symbols of the 1 st slot of the consecutive 9 slots, mapping a third synchronization signal block in the first synchronization signal block packet on the 3 rd to 6 th symbols of the 2 nd slot of the consecutive 9 slots, mapping a fourth synchronization signal block in the first synchronization signal block packet on the 7 th to 10 th symbols of the 2 nd slot of the consecutive 9 slots;
mapping a fifth synchronization signal block of the first synchronization signal block packet on the 3 rd to 6 th symbols of the 3 rd slot of the consecutive 9 slots, mapping a sixth synchronization signal block of the first synchronization signal block packet on the 7 th to 10 th symbols of the 3 rd slot of the consecutive 9 slots, mapping a seventh synchronization signal block of the first synchronization signal block packet on the 3 rd to 6 th symbols of the 4 th slot of the consecutive 9 slots, mapping an eighth synchronization signal block of the first synchronization signal block packet on the 7 th to 10 th symbols of the 4 th slot of the consecutive 9 slots;
mapping a first synchronization signal block of the second synchronization signal block packet on 4-7 symbols of a 6 th slot of the consecutive 9 slots, mapping a second synchronization signal block of the second synchronization signal block packet on 8-11 symbols of a 6 th slot of the consecutive 9 slots, mapping a third synchronization signal block of the second synchronization signal block packet on 4-7 symbols of a 7 th slot of the consecutive 9 slots, mapping a fourth synchronization signal block of the second synchronization signal block packet on 8-11 symbols of a 7 th slot of the consecutive 9 slots;
mapping a fifth synchronization signal block of the second synchronization signal block packet on 4-7 symbols of an 8 th slot of the consecutive 9 slots, mapping a sixth synchronization signal block of the second synchronization signal block packet on 8-11 symbols of an 8 th slot of the consecutive 9 slots, mapping a seventh synchronization signal block of the second synchronization signal block packet on 4-7 symbols of a 9 th slot of the consecutive 9 slots, mapping an eighth synchronization signal block of the second synchronization signal block packet on 8-11 symbols of a 9 th slot of the consecutive 9 slots.
9. The method of claim 8, wherein the first set comprises the following values 4, 10, 14, 18, 28, 32, 42, 46, and wherein the second set comprises the following values 25, 29, 33, 43, 47, 57.
10. The method of claim 1, wherein m and n are 4 and x and y are 28.
11. The method of claim 1, wherein each slot comprises 14 symbols, and wherein mapping m synchronization signal blocks in the first synchronization signal block grouping into x symbols comprises:
mapping a first synchronization signal block in the first synchronization signal block grouping on the 4 th-7 th symbols of a first time slot, mapping a second synchronization signal block in the first synchronization signal block grouping on the 8 th-11 th symbols of the first time slot, mapping a third synchronization signal block in the first synchronization signal block grouping on the 3 rd-6 th symbols of a second time slot, and mapping a fourth synchronization signal block in the first synchronization signal block grouping on the 7 th-10 th symbols of the second time slot;
the mapping n synchronization signal blocks in the second synchronization signal block grouping into y further symbols comprises:
mapping a first synchronization signal block in the second synchronization signal block packet on the 4 th-7 th symbols of a third slot, mapping a second synchronization signal block in the second synchronization signal block packet on the 8 th-11 th symbols of the third slot, mapping a third synchronization signal block in the second synchronization signal block packet on the 3 rd-6 th symbols of a fourth slot, and mapping a fourth synchronization signal block in the second synchronization signal block packet on the 7 th-10 th symbols of the fourth slot, the first slot, the second slot, the third slot, and the fourth slot being 4 consecutive slots.
12. The method of claim 11, wherein the first set comprises the following values: 4. 9, 13, 17, the second set comprising the following values: 11. 15 and 19.
13. The method of claim 1, wherein each slot comprises 14 symbols, and wherein mapping m synchronization signal blocks in the first synchronization signal block grouping into x symbols comprises:
mapping a first synchronization signal block in the first synchronization signal block grouping on the 3 rd to 6 th symbols of a first time slot, mapping a second synchronization signal block in the first synchronization signal block grouping on the 7 th to 10 th symbols of the first time slot, mapping a third synchronization signal block in the first synchronization signal block grouping on the 4 th to 7 th symbols of a second time slot, and mapping a fourth synchronization signal block in the first synchronization signal block grouping on the 8 th to 11 th symbols of the second time slot;
the mapping n synchronization signal blocks in the second synchronization signal block grouping into y further symbols comprises:
mapping a first synchronization signal block in the second synchronization signal block packet on the 3 rd to 6 th symbols of a third slot, mapping a second synchronization signal block in the second synchronization signal block packet on the 7 th to 10 th symbols of the third slot, mapping a third synchronization signal block in the second synchronization signal block packet on the 4 th to 7 th symbols of a fourth slot, and mapping a fourth synchronization signal block in the second synchronization signal block packet on the 8 th to 11 th symbols of the fourth slot, the first slot, the second slot, the third slot, and the fourth slot being 4 consecutive slots.
14. The method of claim 13, wherein the first set comprises the following values: 4. 11, 15, 19, the second set comprising the following values: 9. 13 and 17.
15. The method of claim 1, wherein m and n are 8 and x and y are 56.
16. The method of claim 15, wherein each slot comprises 14 symbols, and wherein mapping the m synchronization signal blocks in the first synchronization signal block grouping into x symbols comprises:
mapping a first synchronization signal block in the first synchronization signal block packet on the 7 th-10 th symbols of the 1 st slot of the consecutive 9 slots, mapping a second synchronization signal block in the first synchronization signal block packet on the 11 th-14 th symbols of the 1 st slot of the consecutive 9 slots, mapping a third synchronization signal block in the first synchronization signal block packet on the 1 st-4 th symbols of the 2 nd slot of the consecutive 9 slots, mapping a fourth synchronization signal block in the first synchronization signal block packet on the 5 th-8 th symbols of the 2 nd slot of the consecutive 9 slots;
mapping a fifth synchronization signal block of the first synchronization signal block grouping on the 7 th-10 th symbols of the 3 rd time slot of the continuous 9 time slots, and mapping a sixth synchronization signal block of the first synchronization signal block grouping on the 11 th-14 th symbols of the 3 rd time slot of the continuous 9 time slots; mapping a seventh synchronization signal block in the first synchronization signal block packet on 1 st to 4 th symbols of a 4 th slot of the consecutive 9 slots, and mapping an eighth synchronization signal block in the first synchronization signal block packet on 5 th to 8 th symbols of a 4 th slot of the consecutive 9 slots;
mapping a first synchronization signal block of the second synchronization signal block packet on the 7 th-10 th symbols of the 6 th slot of the consecutive 9 slots, mapping a second synchronization signal block of the second synchronization signal block packet on the 11 th-14 th symbols of the 6 th slot of the consecutive 9 slots, mapping a third synchronization signal block of the second synchronization signal block packet on the 1 st-4 th symbols of the 7 th slot of the consecutive 9 slots, mapping a fourth synchronization signal block of the second synchronization signal block packet on the 5 th-8 th symbols of the 7 th slot of the consecutive 9 slots;
mapping a fifth synchronization signal block of the second synchronization signal block packet on the 7 th-10 th symbols of the 8 th slot of the consecutive 9 slots, mapping a sixth synchronization signal block of the second synchronization signal block packet on the 11 th-14 th symbols of the 8 th slot of the consecutive 9 slots, mapping a seventh synchronization signal block of the second synchronization signal block packet on the 1 st-4 th symbols of the 9 th slot of the consecutive 9 slots, mapping an eighth synchronization signal block of the second synchronization signal block packet on the 5 th-8 th symbols of the 9 th slot of the consecutive 9 slots.
17. The method of claim 16, wherein the first set comprises the following values 4, 8, 12, 16, 36, 40, and wherein the second set comprises the following values 30, 34, 38, 42.
18. The method of claim 1, wherein the first set comprises values less than a predetermined threshold and the second set comprises values greater than a predetermined threshold.
19. The method of claim 18, wherein m and n are 4 and x and y are 28.
20. The method of claim 19, wherein the predetermined threshold is a positive integer greater than or equal to 21.
21. The method of claim 19 or 20, wherein each slot comprises 7 symbols, and wherein mapping the m synchronization signal blocks in the first synchronization signal block packet into x symbols comprises:
mapping a first synchronization signal block in the first synchronization signal block group on the 2 nd-5 th symbol of a first time slot, mapping a second synchronization signal block in the first synchronization signal block group on the 1 st-4 th symbol of a second time slot, mapping a third synchronization signal block in the first synchronization signal block group on the 2 nd-5 th symbol of a third time slot, and mapping a fourth synchronization signal block in the first synchronization signal block group on the 1 st-4 th symbol of a fourth time slot, wherein the first time slot, the second time slot, the third time slot and the fourth time slot are continuous time slots;
the mapping n synchronization signal blocks in the second synchronization signal block grouping into y further symbols comprises:
mapping a first synchronization signal block in the second synchronization signal block packet on the 2 nd to 5 th symbols of a fifth slot, mapping a second synchronization signal block in the second synchronization signal block packet on the 1 st to 4 th symbols of a sixth slot, mapping a third synchronization signal block in the second synchronization signal block packet on the 2 nd to 5 th symbols of a seventh slot, and mapping a fourth synchronization signal block in the second synchronization signal block packet on the 1 st to 4 th symbols of an eighth slot, wherein the fifth slot, the sixth slot, the seventh slot and the eighth slot are consecutive slots, and the fourth slot and the fifth slot are separated by at least 2 slots.
22. The method of claim 19 or 20, wherein each slot comprises 14 symbols, and wherein mapping the m synchronization signal blocks in the first synchronization signal block packet into x symbols comprises:
mapping a first synchronization signal block in the first synchronization signal block group on the 2 nd to 5 th symbols of a first time slot, mapping a second synchronization signal block in the first synchronization signal block group on the 8 th to 11 th symbols of the first time slot, mapping a third synchronization signal block in the first synchronization signal block group on the 2 nd to 5 th symbols of a second time slot, and mapping a fourth synchronization signal block in the first synchronization signal block group on the 8 th to 11 th symbols of the second time slot, wherein the first time slot and the second time slot are continuous time slots;
the mapping n synchronization signal blocks in the second synchronization signal block grouping into y further symbols comprises:
mapping a first synchronization signal block in the second synchronization signal block packet on the 2 nd-5 th symbol of a third slot, mapping a second synchronization signal block in the second synchronization signal block packet on the 8 th-11 th symbol of the third slot, mapping a third synchronization signal block in the second synchronization signal block packet on the 2 nd-5 th symbol of a fourth slot, and mapping a fourth synchronization signal block in the second synchronization signal block packet on the 8 th-11 th symbol of the fourth slot, wherein the third slot and the fourth slot are consecutive slots and the second slot and the third slot are separated by at least 1 slot.
23. The method of claim 19 or 20, wherein if each slot comprises 14 symbols, said mapping m synchronization signal blocks in the first synchronization signal block packet into x symbols comprises:
mapping a first synchronization signal block in the first synchronization signal block grouping on the 2 nd to 5 th symbols of a first time slot, mapping a second synchronization signal block in the first synchronization signal block grouping on the 7 th to 10 th symbols of the first time slot, mapping a third synchronization signal block in the first synchronization signal block grouping on the 2 nd to 5 th symbols of a second time slot, and mapping a fourth synchronization signal block in the first synchronization signal block grouping on the 7 th to 10 th symbols of the second time slot, wherein the first time slot and the second time slot are continuous time slots;
the mapping n synchronization signal blocks in the second synchronization signal block grouping into y further symbols comprises:
mapping a first synchronization signal block in the second synchronization signal block group on the 2 nd to 5 th symbols of a third time slot, mapping a second synchronization signal block in the second synchronization signal block group on the 7 th to 10 th symbols of the third time slot, mapping a third synchronization signal block in the second synchronization signal block group on the 2 nd to 5 th symbols of a fourth time slot, and mapping a fourth synchronization signal block in the second synchronization signal block group on the 7 th to 10 th symbols of the fourth time slot, wherein the third time slot and the fourth time slot are consecutive time slots, and the second time slot and the third time slot are separated by at least 1 time slot.
24. The method of claim 19 or 20, wherein if each slot comprises 14 symbols, said mapping m synchronization signal blocks in the first synchronization signal block packet into x symbols comprises:
mapping a first synchronization signal block in the first synchronization signal block group on the 3 rd to 6 th symbols of a first time slot, mapping a second synchronization signal block in the first synchronization signal block group on the 8 th to 11 th symbols of the first time slot, mapping a third synchronization signal block in the first synchronization signal block group on the 3 rd to 6 th symbols of a second time slot, and mapping a fourth synchronization signal block in the first synchronization signal block group on the 8 th to 11 th symbols of the second time slot, wherein the first time slot and the second time slot are continuous time slots;
the mapping n synchronization signal blocks in the second synchronization signal block grouping into y further symbols comprises:
mapping a first synchronization signal block in the second synchronization signal block packet on the 3 rd to 6 th symbols of a third slot, mapping a second synchronization signal block in the second synchronization signal block packet on the 8 th to 11 th symbols of the third slot, mapping a third synchronization signal block in the second synchronization signal block packet on the 3 rd to 6 th symbols of a fourth slot, and mapping a fourth synchronization signal block in the second synchronization signal block packet on the 8 th to 11 th symbols of the fourth slot, wherein the third slot and the fourth slot are consecutive slots and the second slot and the third slot are separated by at least 1 slot.
25. The method of claim 19 or 20, wherein if each slot comprises 14 symbols, said mapping m synchronization signal blocks in the first synchronization signal block packet into x symbols comprises:
mapping a first synchronization signal block in the first synchronization signal block grouping on the 3 rd to 6 th symbols of a first time slot, mapping a second synchronization signal block in the first synchronization signal block grouping on the 7 th to 10 th symbols of the first time slot, mapping a third synchronization signal block in the first synchronization signal block grouping on the 3 rd to 6 th symbols of a second time slot, and mapping a fourth synchronization signal block in the first synchronization signal block grouping on the 7 th to 10 th symbols of the second time slot, wherein the first time slot and the second time slot are continuous time slots;
the mapping n synchronization signal blocks in the second synchronization signal block grouping into y further symbols comprises:
mapping a first synchronization signal block in the second synchronization signal block packet on the 3 rd to 6 th symbols of a third slot, mapping a second synchronization signal block in the second synchronization signal block packet on the 7 th to 10 th symbols of the third slot, mapping a third synchronization signal block in the second synchronization signal block packet on the 3 rd to 6 th symbols of a fourth slot, and mapping a fourth synchronization signal block in the second synchronization signal block packet on the 7 th to 10 th symbols of the fourth slot, wherein the third slot and the fourth slot are consecutive slots and the second slot and the third slot are separated by at least 1 slot.
26. The method of claim 19 or 20, wherein if each slot comprises 14 symbols, said mapping m synchronization signal blocks in the first synchronization signal block packet into x symbols comprises:
mapping a first synchronization signal block in the first synchronization signal block grouping on the 4 th-7 th symbols of a first time slot, mapping a second synchronization signal block in the first synchronization signal block grouping on the 8 th-11 th symbols of the first time slot, mapping a third synchronization signal block in the first synchronization signal block grouping on the 4 th-7 th symbols of a second time slot, and mapping a fourth synchronization signal block in the first synchronization signal block grouping on the 8 th-11 th symbols of the second time slot, wherein the first time slot and the second time slot are continuous time slots;
the mapping n synchronization signal blocks in the second synchronization signal block grouping into y further symbols comprises:
mapping a first synchronization signal block in the second synchronization signal block packet on the 4 th-7 th symbols of a third slot, mapping a second synchronization signal block in the second synchronization signal block packet on the 8 th-11 th symbols of the third slot, mapping a third synchronization signal block in the second synchronization signal block packet on the 4 th-7 th symbols of a fourth slot, and mapping a fourth synchronization signal block in the second synchronization signal block packet on the 8 th-11 th symbols of the fourth slot, wherein the third slot and the fourth slot are consecutive slots and the second slot and the third slot are separated by at least 1 slot.
27. The method of claim 19, wherein the predetermined threshold is a positive integer greater than 12 and less than 18.
28. The method of claim 27, wherein each slot comprises 14 symbols, and wherein mapping m synchronization signal blocks in the first synchronization signal block grouping into x symbols comprises:
mapping a first synchronization signal block in the first synchronization signal block packet on the 5 th to 8 th symbols of a first slot, mapping a second synchronization signal block in the first synchronization signal block packet on the 9 th to 12 th symbols of the first slot, mapping a third synchronization signal block in the first synchronization signal block packet on the 13 th to 14 th symbols of the first slot and the 1 st to 2 nd symbols of a second slot, and mapping a fourth synchronization signal block in the first synchronization signal block packet on the 3 rd to 6 th symbols of the second slot;
the mapping n synchronization signal blocks in the second synchronization signal block grouping into y further symbols comprises:
mapping a first synchronization signal block in the second synchronization signal block packet on the 7 th-10 th symbols of a third slot, mapping a second synchronization signal block in the second synchronization signal block packet on the 11 th-14 th symbols of the third slot, mapping a third synchronization signal block in the second synchronization signal block packet on the 1 st-4 th symbols of a fourth slot, and mapping a fourth synchronization signal block in the second synchronization signal block packet on the 5 th-8 th symbols of the fourth slot, wherein the first slot, the second slot, the third slot and the fourth slot are consecutive slots.
29. The method of claim 18, wherein m and n are 8 and x and y are 56.
30. The method of claim 29, wherein the predetermined threshold is a positive integer greater than 40 and less than 44.
31. The method of claim 29 or 30, wherein each slot comprises 14 symbols, and wherein mapping the m synchronization signal blocks in the first synchronization signal block packet into x symbols comprises:
mapping a first synchronization signal block in the first synchronization signal block packet on the 7 th-10 th symbols of the 1 st slot of the consecutive 10 slots, mapping a second synchronization signal block in the first synchronization signal block packet on the 11 th-14 th symbols of the 1 st slot of the consecutive 10 slots, mapping a third synchronization signal block in the first synchronization signal block packet on the 1 st-4 th symbols of the 2 nd slot of the consecutive 10 slots, mapping a fourth synchronization signal block in the first synchronization signal block packet on the 5 th-8 th symbols of the 2 nd slot of the consecutive 10 slots;
mapping a fifth synchronization signal block of the first synchronization signal block packet on the 7 th-10 th symbols of the 3 rd slot of the consecutive 10 slots, mapping a sixth synchronization signal block of the first synchronization signal block packet on the 11 th-14 th symbols of the 3 rd slot of the consecutive 10 slots, mapping a seventh synchronization signal block of the first synchronization signal block packet on the 1 st-4 th symbols of the 4 th slot of the consecutive 10 slots, mapping an eighth synchronization signal block of the first synchronization signal block packet on the 5 th-8 th symbols of the 4 th slot of the consecutive 10 slots;
mapping a first synchronization signal block of the second synchronization signal block packet on the 7 th-10 th symbols of the 7 th slot of the consecutive 10 slots, mapping a second synchronization signal block of the second synchronization signal block packet on the 11 th-14 th symbols of the 7 th slot of the consecutive 10 slots, mapping a third synchronization signal block of the second synchronization signal block packet on the 1 st-4 th symbols of the 8 th slot of the consecutive 10 slots, mapping a fourth synchronization signal block of the second synchronization signal block packet on the 5 th-8 th symbols of the 8 th slot of the consecutive 10 slots;
mapping a fifth synchronization signal block of the second synchronization signal block packet on the 7 th-10 th symbols of the 9 th slot of the consecutive 10 slots, mapping a sixth synchronization signal block of the second synchronization signal block packet on the 11 th-14 th symbols of the 9 th slot of the consecutive 10 slots, mapping a seventh synchronization signal block of the second synchronization signal block packet on the 1 st-4 th symbols of the 10 th slot of the consecutive 10 slots, mapping an eighth synchronization signal block of the second synchronization signal block packet on the 5 th-8 th symbols of the 10 th slot of the consecutive 10 slots.
32. The method of claim 31, wherein the first set comprises the following values: 4. 8, 12, 16, 36, 40, the second set comprising the following values: 30. 34, 38, 42.
33. The method of claim 1, wherein the symbols mapped by the first and second synchronization signal block packets occupy the first 5 milliseconds of a synchronization signal burst set transmission period in which the first and second synchronization signal block packets are located, and wherein the transmission period of the synchronization signal burst set is configured as one of: 5 milliseconds, 10 milliseconds, 20 milliseconds, 40 milliseconds, 80 milliseconds, 160 milliseconds.
34. A method of transmitting a synchronization signal, comprising:
the terminal equipment detects a first synchronous signal block and a second synchronous signal block in a sending period of a synchronous signal pulse set;
the terminal equipment determines the number of symbols of a phase difference between the time domain resource occupied by the first synchronous signal block and the time domain resource occupied by the second synchronous signal block;
if the number of symbols differing by the phase belongs to a predetermined set, the terminal device determines that the first synchronization signal block and the second synchronization signal block belong to the same synchronization signal block group.
35. The method of claim 34, wherein the values included in the predetermined set are even numbers.
36. The method of claim 34, wherein the values included in the predetermined set are less than a predetermined threshold.
37. The method of claim 34, wherein a transmission period of the set of synchronization signal pulses is configured as one of: 5 milliseconds, 10 milliseconds, 20 milliseconds, 40 milliseconds, 80 milliseconds, 160 milliseconds, the first and second synchronization signal blocks being detected by the terminal device in the first 5 milliseconds of the synchronization signal pulse set transmission period.
38. A network device comprising a transceiver and a processor, wherein
The processor is used for generating a first synchronous signal block packet and a second synchronous signal block packet, wherein the first synchronous signal block packet comprises m synchronous signal blocks, the second synchronous signal block packet comprises n synchronous signal blocks, and m and n are positive integers greater than or equal to 2;
mapping m synchronization signal blocks in the first synchronization signal block group into x symbols, wherein x is 7m, and the number of symbols with a difference between any two synchronization signal blocks in the mapped first synchronization signal block group belongs to a first set;
mapping n synchronization signal blocks in the second synchronization signal block group to y other symbols, where y is 7n, the number of symbols that are different between any two synchronization signal blocks in the mapped second synchronization signal block group belongs to the first set, the number of symbols that are different between one synchronization signal block in the mapped second synchronization signal block group and one synchronization signal block in the mapped first synchronization signal block group belongs to a second set, and a value in the second set does not overlap with a value in the first set;
the transceiver is configured to send the synchronization signal blocks in the first synchronization signal block packet and the synchronization signal blocks in the second synchronization signal block packet through the time-frequency resources mapped by the processor.
39. The network device of claim 38, wherein the values included in the first set are even numbers and the values included in the second set are odd numbers.
40. The network device of claim 39, wherein m and n have values of 4 and x and y have values of 28.
41. The network device of claim 40, wherein each slot includes 7 symbols,
the processor is configured to map a first synchronization signal block in the first synchronization signal block grouping onto 2-5 symbols of a 1 st slot of the consecutive 8 slots, map a second synchronization signal block in the first synchronization signal block grouping onto 2-5 symbols of a 3 rd slot of the consecutive 8 slots, map a third synchronization signal block in the first synchronization signal block grouping onto 2-5 symbols of a 5 th slot of the consecutive 8 slots, and map a fourth synchronization signal block in the first synchronization signal block grouping onto 2-5 symbols of a 7 th slot of the consecutive 8 slots;
mapping a first synchronization signal block of the second synchronization signal block grouping on the 2 nd-5 th symbol of the 2 nd slot of the consecutive 8 slots, mapping a second synchronization signal block of the second synchronization signal block grouping on the 2 nd-5 th symbol of the 4 th slot of the consecutive 8 slots, mapping a third synchronization signal block of the second synchronization signal block grouping on the 2 nd-5 th symbol of the 6 th slot of the consecutive 8 slots, and mapping a fourth synchronization signal block of the second synchronization signal block grouping on the 2 nd-5 th symbol of the 8 th slot of the consecutive 8 slots.
42. The network device of claim 40, wherein each slot includes 14 symbols,
the processor is configured to map a first synchronization signal block in the first synchronization signal block grouping onto 2-5 symbols of a 1 st slot of consecutive 4 slots, map a second synchronization signal block in the first synchronization signal block grouping onto 2-5 symbols of a 2 nd slot of the consecutive 4 slots, map a third synchronization signal block in the first synchronization signal block grouping onto 2-5 symbols of a 3 rd slot of the consecutive 4 slots, and map a fourth synchronization signal block in the first synchronization signal block grouping onto 2-5 symbols of a 4 th slot of the consecutive 4 slots;
mapping a first synchronization signal block of the second synchronization signal block grouping on the 9 th-12 th symbols of the 1 st slot of the consecutive 4 slots, mapping a second synchronization signal block of the second synchronization signal block grouping on the 9 th-12 th symbols of the 2 nd slot of the consecutive 4 slots, mapping a third synchronization signal block of the second synchronization signal block grouping on the 9 th-12 th symbols of the 3 rd slot of the consecutive 4 slots, and mapping a fourth synchronization signal block of the second synchronization signal block grouping on the 9 th-12 th symbols of the 4 th slot of the consecutive 4 slots.
43. A network device according to claim 41 or 42, characterized in that the following values 14, 28, 42 are included in the first set and the following values 7, 21, 35, 49 are included in the second set.
44. The network device of claim 39, wherein m and n have values of 8 and x and y have values of 56.
45. The network device of claim 44,
the processor is configured to map a first synchronization signal block in the first synchronization signal block packet on the 3 rd to 6 th symbols of the 1 st slot of the consecutive 9 slots, map a second synchronization signal block in the first synchronization signal block packet on the 7 th to 10 th symbols of the 1 st slot of the consecutive 9 slots, map a third synchronization signal block in the first synchronization signal block packet on the 3 rd to 6 th symbols of the 2 nd slot of the consecutive 9 slots, and map a fourth synchronization signal block in the first synchronization signal block packet on the 7 th to 10 th symbols of the 2 nd slot of the consecutive 9 slots;
mapping a fifth synchronization signal block of the first synchronization signal block packet on the 3 rd to 6 th symbols of the 3 rd slot of the consecutive 9 slots, mapping a sixth synchronization signal block of the first synchronization signal block packet on the 7 th to 10 th symbols of the 3 rd slot of the consecutive 9 slots, mapping a seventh synchronization signal block of the first synchronization signal block packet on the 3 rd to 6 th symbols of the 4 th slot of the consecutive 9 slots, mapping an eighth synchronization signal block of the first synchronization signal block packet on the 7 th to 10 th symbols of the 4 th slot of the consecutive 9 slots;
mapping a first synchronization signal block of the second synchronization signal block packet on 4-7 symbols of a 6 th slot of the consecutive 9 slots, mapping a second synchronization signal block of the second synchronization signal block packet on 8-11 symbols of a 6 th slot of the consecutive 9 slots, mapping a third synchronization signal block of the second synchronization signal block packet on 4-7 symbols of a 7 th slot of the consecutive 9 slots, mapping a fourth synchronization signal block of the second synchronization signal block packet on 8-11 symbols of a 7 th slot of the consecutive 9 slots;
mapping a fifth synchronization signal block of the second synchronization signal block packet on 4-7 symbols of an 8 th slot of the consecutive 9 slots, mapping a sixth synchronization signal block of the second synchronization signal block packet on 8-11 symbols of an 8 th slot of the consecutive 9 slots, mapping a seventh synchronization signal block of the second synchronization signal block packet on 4-7 symbols of a 9 th slot of the consecutive 9 slots, mapping an eighth synchronization signal block of the second synchronization signal block packet on 8-11 symbols of a 9 th slot of the consecutive 9 slots.
46. The network device of claim 45, wherein the first set comprises the following values 4, 10, 14, 18, 28, 32, 42, 46, and wherein the second set comprises the following values 25, 29, 33, 43, 47, 57.
47. The network device of claim 38, wherein m and n have values of 4 and x and y have values of 28.
48. The network device of claim 38, wherein each slot includes 14 symbols,
the processor is configured to map a first synchronization signal block in the first synchronization signal block packet on the 4 th to 7 th symbols of a first slot, map a second synchronization signal block in the first synchronization signal block packet on the 8 th to 11 th symbols of the first slot, map a third synchronization signal block in the first synchronization signal block packet on the 3 rd to 6 th symbols of a second slot, and map a fourth synchronization signal block in the first synchronization signal block packet on the 7 th to 10 th symbols of the second slot;
mapping a first synchronization signal block in the second synchronization signal block packet on the 4 th-7 th symbols of a third slot, mapping a second synchronization signal block in the second synchronization signal block packet on the 8 th-11 th symbols of the third slot, mapping a third synchronization signal block in the second synchronization signal block packet on the 3 rd-6 th symbols of a fourth slot, and mapping a fourth synchronization signal block in the second synchronization signal block packet on the 7 th-10 th symbols of the fourth slot, the first slot, the second slot, the third slot, and the fourth slot being 4 consecutive slots.
49. The network device of claim 48, wherein the first set comprises the following values: 4. 9, 13, 17, the second set comprising the following values: 11. 15 and 19.
50. The network device of claim 38, wherein each slot includes 14 symbols,
the processor is configured to map a first synchronization signal block in the first synchronization signal block packet on 3 rd to 6 th symbols of a first slot, map a second synchronization signal block in the first synchronization signal block packet on 7 th to 10 th symbols of the first slot, map a third synchronization signal block in the first synchronization signal block packet on 4 th to 7 th symbols of a second slot, and map a fourth synchronization signal block in the first synchronization signal block packet on 8 th to 11 th symbols of the second slot;
mapping a first synchronization signal block in the second synchronization signal block packet on the 3 rd to 6 th symbols of a third slot, mapping a second synchronization signal block in the second synchronization signal block packet on the 7 th to 10 th symbols of the third slot, mapping a third synchronization signal block in the second synchronization signal block packet on the 4 th to 7 th symbols of a fourth slot, and mapping a fourth synchronization signal block in the second synchronization signal block packet on the 8 th to 11 th symbols of the fourth slot, the first slot, the second slot, the third slot, and the fourth slot being 4 consecutive slots.
51. The network device of claim 50, wherein the first set comprises the following values: 4. 11, 15, 19, the second set comprising the following values: 9. 13 and 17.
52. The network device of claim 38, wherein m and n have values of 8 and x and y have values of 56.
53. The network device of claim 52,
the processor is configured to map a first synchronization signal block in the first synchronization signal block packet on the 7 th to 10 th symbols of the 1 st slot of the consecutive 9 slots, map a second synchronization signal block in the first synchronization signal block packet on the 11 th to 14 th symbols of the 1 st slot of the consecutive 9 slots, map a third synchronization signal block in the first synchronization signal block packet on the 1 st to 4 th symbols of the 2 nd slot of the consecutive 9 slots, and map a fourth synchronization signal block in the first synchronization signal block packet on the 5 th to 8 th symbols of the 2 nd slot of the consecutive 9 slots;
mapping a fifth synchronization signal block of the first synchronization signal block grouping on the 7 th-10 th symbols of the 3 rd time slot of the continuous 9 time slots, and mapping a sixth synchronization signal block of the first synchronization signal block grouping on the 11 th-14 th symbols of the 3 rd time slot of the continuous 9 time slots; mapping a seventh synchronization signal block in the first synchronization signal block packet on 1 st to 4 th symbols of a 4 th slot of the consecutive 9 slots, and mapping an eighth synchronization signal block in the first synchronization signal block packet on 5 th to 8 th symbols of a 4 th slot of the consecutive 9 slots;
mapping a first synchronization signal block of the second synchronization signal block packet on the 7 th-10 th symbols of the 6 th slot of the consecutive 9 slots, mapping a second synchronization signal block of the second synchronization signal block packet on the 11 th-14 th symbols of the 6 th slot of the consecutive 9 slots, mapping a third synchronization signal block of the second synchronization signal block packet on the 1 st-4 th symbols of the 7 th slot of the consecutive 9 slots, mapping a fourth synchronization signal block of the second synchronization signal block packet on the 5 th-8 th symbols of the 7 th slot of the consecutive 9 slots;
mapping a fifth synchronization signal block of the second synchronization signal block packet on the 7 th-10 th symbols of the 8 th slot of the consecutive 9 slots, mapping a sixth synchronization signal block of the second synchronization signal block packet on the 11 th-14 th symbols of the 8 th slot of the consecutive 9 slots, mapping a seventh synchronization signal block of the second synchronization signal block packet on the 1 st-4 th symbols of the 9 th slot of the consecutive 9 slots, mapping an eighth synchronization signal block of the second synchronization signal block packet on the 5 th-8 th symbols of the 9 th slot of the consecutive 9 slots.
54. The network device of claim 53, wherein the first set comprises the following values 4, 8, 12, 16, 36, 40, and wherein the second set comprises the following values 30, 34, 38, 42.
55. The network device of claim 38, wherein the values included in the first set are less than a predetermined threshold and the values included in the second set are greater than a predetermined threshold.
56. The network device of claim 55, wherein m and n have values of 4 and x and y have values of 28.
57. The network device of claim 56, wherein the predetermined threshold is a positive integer greater than or equal to 21.
58. The network device of claim 56 or 57, wherein each slot comprises 7 symbols,
the processor is configured to map a first synchronization signal block in the first synchronization signal block packet on 2 nd to 5 th symbols of a first slot, map a second synchronization signal block in the first synchronization signal block packet on 1 st to 4 th symbols of a second slot, map a third synchronization signal block in the first synchronization signal block packet on 2 nd to 5 th symbols of a third slot, and map a fourth synchronization signal block in the first synchronization signal block packet on 1 st to 4 th symbols of a fourth slot, where the first slot, the second slot, the third slot, and the fourth slot are consecutive slots;
mapping a first synchronous signal block in the first synchronous signal block group on the 2 nd to 5 th symbols of a fifth time slot, mapping a second synchronous signal block in the first synchronous signal block group on the 1 st to 4 th symbols of a sixth time slot, mapping a third synchronous signal block in the first synchronous signal block group on the 2 nd to 5 th symbols of a seventh time slot, and mapping a fourth synchronous signal block in the first synchronous signal block group on the 1 st to 4 th symbols of an eighth time slot, wherein the fifth time slot, the sixth time slot, the seventh time slot and the eighth time slot are continuous time slots, and the fourth time slot and the fifth time slot are separated by at least 2 time slots.
59. The network device of claim 56 or 57, wherein each slot comprises 14 symbols,
the processor is configured to map a first synchronization signal block in the first synchronization signal block packet on 2 nd to 5 th symbols of a first slot, map a second synchronization signal block in the first synchronization signal block packet on 8 th to 11 th symbols of the first slot, map a third synchronization signal block in the first synchronization signal block packet on 2 nd to 5 th symbols of a second slot, map a fourth synchronization signal block in the first synchronization signal block packet on 8 th to 11 th symbols of the second slot, where the first slot and the second slot are consecutive slots;
mapping a first synchronization signal block in the second synchronization signal block packet on the 2 nd-5 th symbol of a third slot, mapping a second synchronization signal block in the second synchronization signal block packet on the 8 th-11 th symbol of the third slot, mapping a third synchronization signal block in the second synchronization signal block packet on the 2 nd-5 th symbol of a fourth slot, and mapping a fourth synchronization signal block in the second synchronization signal block packet on the 8 th-11 th symbol of the fourth slot, wherein the third slot and the fourth slot are consecutive slots and the second slot and the third slot are separated by at least 1 slot.
60. A network device as claimed in claim 56 or 57, wherein if each slot comprises 14 symbols,
the processor is configured to map a first synchronization signal block in the first synchronization signal block packet on 2 nd to 5 th symbols of a first slot, map a second synchronization signal block in the first synchronization signal block packet on 7 th to 10 th symbols of the first slot, map a third synchronization signal block in the first synchronization signal block packet on 2 nd to 5 th symbols of a second slot, map a fourth synchronization signal block in the first synchronization signal block packet on 7 th to 10 th symbols of the second slot, where the first slot and the second slot are consecutive slots;
mapping a first synchronization signal block in the second synchronization signal block group on the 2 nd to 5 th symbols of a third time slot, mapping a second synchronization signal block in the second synchronization signal block group on the 7 th to 10 th symbols of the third time slot, mapping a third synchronization signal block in the second synchronization signal block group on the 2 nd to 5 th symbols of a fourth time slot, and mapping a fourth synchronization signal block in the second synchronization signal block group on the 7 th to 10 th symbols of the fourth time slot, wherein the third time slot and the fourth time slot are consecutive time slots, and the second time slot and the third time slot are separated by at least 1 time slot.
61. A network device as claimed in claim 56 or 57, wherein if each slot comprises 14 symbols,
the processor is configured to map a first synchronization signal block in the first synchronization signal block packet on 3 rd to 6 th symbols of a first slot, map a second synchronization signal block in the first synchronization signal block packet on 8 th to 11 th symbols of the first slot, map a third synchronization signal block in the first synchronization signal block packet on 3 rd to 6 th symbols of a second slot, map a fourth synchronization signal block in the first synchronization signal block packet on 8 th to 11 th symbols of the second slot, where the first slot and the second slot are consecutive slots;
mapping a first synchronization signal block in the second synchronization signal block packet on the 3 rd to 6 th symbols of a third slot, mapping a second synchronization signal block in the second synchronization signal block packet on the 8 th to 11 th symbols of the third slot, mapping a third synchronization signal block in the second synchronization signal block packet on the 3 rd to 6 th symbols of a fourth slot, and mapping a fourth synchronization signal block in the second synchronization signal block packet on the 8 th to 11 th symbols of the fourth slot, wherein the third slot and the fourth slot are consecutive slots and the second slot and the third slot are separated by at least 1 slot.
62. A network device as claimed in claim 56 or 57, wherein if each slot comprises 14 symbols,
the processor is configured to map a first synchronization signal block in the first synchronization signal block packet on 3 rd to 6 th symbols of a first slot, map a second synchronization signal block in the first synchronization signal block packet on 7 th to 10 th symbols of the first slot, map a third synchronization signal block in the first synchronization signal block packet on 3 rd to 6 th symbols of a second slot, map a fourth synchronization signal block in the first synchronization signal block packet on 7 th to 10 th symbols of the second slot, where the first slot and the second slot are consecutive slots;
mapping a first synchronization signal block in the second synchronization signal block packet on the 3 rd to 6 th symbols of a third slot, mapping a second synchronization signal block in the second synchronization signal block packet on the 7 th to 10 th symbols of the third slot, mapping a third synchronization signal block in the second synchronization signal block packet on the 3 rd to 6 th symbols of a fourth slot, and mapping a fourth synchronization signal block in the second synchronization signal block packet on the 7 th to 10 th symbols of the fourth slot, wherein the third slot and the fourth slot are consecutive slots and the second slot and the third slot are separated by at least 1 slot.
63. A network device as claimed in claim 56 or 57, wherein if each slot comprises 14 symbols,
the processor is configured to map a first synchronization signal block in the first synchronization signal block packet on 4 th to 7 th symbols of a first slot, map a second synchronization signal block in the first synchronization signal block packet on 8 th to 11 th symbols of the first slot, map a third synchronization signal block in the first synchronization signal block packet on 4 th to 7 th symbols of a second slot, map a fourth synchronization signal block in the first synchronization signal block packet on 8 th to 11 th symbols of the second slot, where the first slot and the second slot are consecutive slots;
mapping a first synchronization signal block in the second synchronization signal block packet on the 4 th-7 th symbols of a third slot, mapping a second synchronization signal block in the second synchronization signal block packet on the 8 th-11 th symbols of the third slot, mapping a third synchronization signal block in the second synchronization signal block packet on the 4 th-7 th symbols of a fourth slot, and mapping a fourth synchronization signal block in the second synchronization signal block packet on the 8 th-11 th symbols of the fourth slot, wherein the third slot and the fourth slot are consecutive slots and the second slot and the third slot are separated by at least 1 slot.
64. The network device of claim 56, wherein the predetermined threshold is a positive integer greater than 12 and less than 18.
65. The network device of claim 64,
the processor is configured to map a first synchronization signal block in the first synchronization signal block packet on the 5 th to 8 th symbols of a first slot, map a second synchronization signal block in the first synchronization signal block packet on the 9 th to 12 th symbols of the first slot, map a third synchronization signal block in the first synchronization signal block packet on the 13 th to 14 th symbols of the first slot and the 1 st to 2 nd symbols of a second slot, and map a fourth synchronization signal block in the first synchronization signal block packet on the 3 rd to 6 th symbols of the second slot;
mapping a first synchronization signal block in the second synchronization signal block packet on the 7 th-10 th symbols of a third slot, mapping a second synchronization signal block in the second synchronization signal block packet on the 11 th-14 th symbols of the third slot, mapping a third synchronization signal block in the second synchronization signal block packet on the 1 st-4 th symbols of a fourth slot, and mapping a fourth synchronization signal block in the second synchronization signal block packet on the 5 th-8 th symbols of the fourth slot, wherein the first slot, the second slot, the third slot and the fourth slot are consecutive slots.
66. The network device of claim 55, wherein m and n have values of 8 and x and y have values of 56.
67. The network device of claim 66, wherein the predetermined threshold is a positive integer greater than 40 and less than 44.
68. The network device of claim 66 or 67,
the processor is configured to map a first synchronization signal block in the first synchronization signal block packet on the 7 th to 10 th symbols of the 1 st slot of the consecutive 10 slots, map a second synchronization signal block in the first synchronization signal block packet on the 11 th to 14 th symbols of the 1 st slot of the consecutive 10 slots, map a third synchronization signal block in the first synchronization signal block packet on the 1 st to 4 th symbols of the 2 nd slot of the consecutive 10 slots, and map a fourth synchronization signal block in the first synchronization signal block packet on the 5 th to 8 th symbols of the 2 nd slot of the consecutive 10 slots;
mapping a fifth synchronization signal block of the first synchronization signal block packet on the 7 th-10 th symbols of the 3 rd slot of the consecutive 10 slots, mapping a sixth synchronization signal block of the first synchronization signal block packet on the 11 th-14 th symbols of the 3 rd slot of the consecutive 10 slots, mapping a seventh synchronization signal block of the first synchronization signal block packet on the 1 st-4 th symbols of the 4 th slot of the consecutive 10 slots, mapping an eighth synchronization signal block of the first synchronization signal block packet on the 5 th-8 th symbols of the 4 th slot of the consecutive 10 slots;
mapping a first synchronization signal block of the second synchronization signal block packet on the 7 th-10 th symbols of the 7 th slot of the consecutive 10 slots, mapping a second synchronization signal block of the second synchronization signal block packet on the 11 th-14 th symbols of the 7 th slot of the consecutive 10 slots, mapping a third synchronization signal block of the second synchronization signal block packet on the 1 st-4 th symbols of the 8 th slot of the consecutive 10 slots, mapping a fourth synchronization signal block of the second synchronization signal block packet on the 5 th-8 th symbols of the 8 th slot of the consecutive 10 slots;
mapping a fifth synchronization signal block of the second synchronization signal block packet on the 7 th-10 th symbols of the 9 th slot of the consecutive 10 slots, mapping a sixth synchronization signal block of the second synchronization signal block packet on the 11 th-14 th symbols of the 9 th slot of the consecutive 10 slots, mapping a seventh synchronization signal block of the second synchronization signal block packet on the 1 st-4 th symbols of the 10 th slot of the consecutive 10 slots, mapping an eighth synchronization signal block of the second synchronization signal block packet on the 5 th-8 th symbols of the 10 th slot of the consecutive 10 slots.
69. The network device of claim 68, wherein the first set comprises the following values: 4. 8, 12, 16, 36, 40, the second set comprising the following values: 30. 34, 38, 42.
70. The network device of claim 38,
the symbols mapped by the first and second synchronization signal block packets occupy the first 5 milliseconds of a synchronization signal pulse set transmission period in which the first and second synchronization signal block packets are located, and the transmission period of the synchronization signal pulse set is configured as one of: 5 milliseconds, 10 milliseconds, 20 milliseconds, 40 milliseconds, 80 milliseconds, 160 milliseconds.
71. A terminal device comprising a transceiver and a processor, wherein
The transceiver is used for detecting a first synchronization signal block and a second synchronization signal block in a transmission period of a synchronization signal pulse set;
the processor is configured to determine a number of symbols of a phase difference between a time domain resource occupied by the first synchronization signal block and a time domain resource occupied by the second synchronization signal block;
determining that the first synchronization signal block and the second synchronization signal block belong to the same synchronization signal block group if the number of symbols that differ belongs to a predetermined set.
72. A terminal device according to claim 71, wherein the values comprised in the predetermined set are even numbers.
73. A terminal device according to claim 71, wherein the values comprised in the predetermined set are smaller than a predetermined threshold.
74. The terminal device of claim 71, wherein a transmission period of the set of synchronization signal pulses is configured to be one of: 5ms, 10ms, 20ms, 40ms, 80ms, 160ms, the synchronization signal block and second synchronization signal block being detected by the terminal device in the first 5ms of the set of synchronization signal pulses transmission period.
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