CN108880293B

CN108880293B - Secondary controller applied to secondary side of power converter and operation method thereof

Info

Publication number: CN108880293B
Application number: CN201710333994.2A
Authority: CN
Inventors: 陈耀宗; 李茂仕; 李三益; 李弘庆
Original assignee: Leadtrend Technology Corp
Current assignee: Leadtrend Technology Corp
Priority date: 2017-05-12
Filing date: 2017-05-12
Publication date: 2021-01-05
Anticipated expiration: 2037-05-12
Also published as: CN108880293A

Abstract

The invention discloses a secondary controller applied to a secondary side of a power converter and an operation method thereof. The secondary controller includes a detector and a standby signal generating circuit. The detector is used for detecting a first signal and a second signal of a universal serial bus and the frequency of a synchronous signal corresponding to the primary side of the power converter. The standby signal generating circuit is coupled to the detector, and configured to delay a first predetermined time to generate a standby signal to a primary controller of a primary side of the power converter when the detector does not detect the first signal and the second signal and the frequency is less than a first predetermined frequency, wherein the primary controller enters a standby mode according to the standby signal. Therefore, when the universal serial bus device and the secondary controller are disconnected, the standby mode can be utilized by the invention to reduce the power consumption of the power converter, the primary controller and the secondary controller.

Description

Secondary controller applied to secondary side of power converter and operation method thereof

Technical Field

The present invention relates to a secondary controller applied to a secondary side of a power converter and an operating method thereof, and more particularly, to a secondary controller and an operating method thereof, which can reduce power consumption of the power converter, the primary controller, and a secondary controller applied to a primary side of the power converter using a standby mode when a universal serial bus device and the secondary controller are disconnected.

Background

When the secondary controller applied to the secondary side of the power converter is coupled with a universal serial bus device, the power converter, the secondary controller and the primary controller applied to the primary side of the power converter operate in a normal mode. However, when the usb device and the secondary controller are disconnected, although the primary controller may operate the power converter at a lower switching frequency, the secondary controller and the primary controller still operate in the normal mode, so the power consumption of the secondary controller and the primary controller is not reduced due to the disconnection of the usb device and the secondary controller. Therefore, how to reduce the power consumption of the secondary controller and the primary controller after the usb device and the secondary controller are disconnected becomes an important issue for energy saving.

Disclosure of Invention

An embodiment of the invention discloses a secondary controller applied to a secondary side of a power converter. The secondary controller includes a detector and a standby signal generating circuit. The detector is used for detecting a first signal and a second signal of a Universal Serial Bus (USB) and a frequency of a synchronous signal corresponding to a primary side of the power converter. The standby signal generating circuit is coupled to the detector, and configured to delay a first predetermined time to generate a standby signal to a primary controller of a primary side of the power converter when the detector does not detect the first signal and the second signal and the frequency is less than a first predetermined frequency, wherein the primary controller enters a standby mode according to the standby signal.

Another embodiment of the present invention discloses an operation method of a secondary controller applied to a secondary side of a power converter, wherein the secondary controller comprises a detector, a standby signal generating circuit and a comparator. The method includes the detector detecting a first signal and a second signal of a universal serial bus and a frequency of a synchronous signal corresponding to a primary side of the power converter; when the detector does not detect the first signal and the second signal and the frequency is less than a first predetermined frequency, the standby signal generating circuit delays for a first predetermined time to generate a standby signal to the primary controller of the primary side of the power converter, wherein the primary controller enters a standby mode according to the standby signal.

The invention discloses a secondary controller applied to a secondary side of a power converter and an operation method thereof. The secondary controller and the operation method are used for judging that the universal serial bus device and the secondary controller are disconnected when the detector of the secondary controller does not detect a first signal and a second signal of a universal serial bus device and the detector of the secondary controller detects that the frequency of a synchronous signal corresponding to the primary side of the power converter is smaller than a first preset frequency. After the secondary controller and the operation method judge that the universal serial bus device and the secondary controller are disconnected, the secondary controller and the operation method enable the secondary controller and the primary controller to enter a standby mode, wherein after the secondary controller and the primary controller enter the standby mode, the secondary controller and the primary controller only start circuits related to the standby mode. Therefore, compared with the prior art, since the secondary controller and the primary controller only turn on the circuits related to the standby mode after the secondary controller and the primary controller enter the standby mode, the power consumption of the power converter, the primary controller and the secondary controller can be reduced by using the standby mode when the universal serial bus device and the secondary controller are disconnected.

Drawings

Fig. 1 is a schematic diagram of a secondary controller applied to a secondary side of a power converter according to a first embodiment of the present invention.

Fig. 2 is a schematic diagram illustrating the operation timing of the primary controller and the secondary controller entering the standby mode from the normal mode.

Fig. 3 is an operation timing diagram illustrating the primary controller and the secondary controller operating in a standby mode.

Fig. 4-8 are schematic diagrams illustrating operational timing of the primary controller and the secondary controller entering the normal mode from the standby mode.

Fig. 9A and 9B are flowcharts of an operation method of a secondary controller applied to a secondary side of a power converter according to a second embodiment of the present invention.

Wherein the reference numerals are as follows:

100 power converter

102 synchronous switch

104 power switch

106 optical coupler

108 winding

200 secondary controller

202. 306 detector

204 standby signal generating circuit

206 comparator

208. 210, 212, 214, 216, 302 pins

300 primary controller

304 grid control signal generating circuit

CS current detection pin

COMP compensation pin

FB feedback pin

FS first signal

FCS comparison signal

FPF first predetermined frequency

FPT for the first predetermined time

FVREF first reference voltage

GND1, GND2 ground terminal

GCS Gate control Signal

IOUT output current

LS leaving signal

OTP over-temperature protection pin

PRI Primary side

Rising edge of QRD

QRDR descent edge

SEC Secondary side

SS second signal

SYN synchronization signal

STS Standby Signal

SVREF second reference voltage

SPT second predetermined time

TPT third predetermined time

TVREF third reference voltage

TS enable signal

T1, T2, T3, T4, T5 time

UVLOOFF low voltage lockout turn-off voltage

UVLOON low voltage lock-on voltage

VOUT output voltage

VCS detection voltage

900 step and 920 step

Detailed Description

Referring to fig. 1, fig. 1 is a schematic diagram of a secondary controller 200 applied to a secondary side SEC of a power converter 100 according to a first embodiment of the present invention, wherein the power converter 100 is an ac/dc power converter. As shown in fig. 1, the secondary controller 200 includes a detector 202, a standby signal generating circuit 204 and a comparator 206, wherein the standby signal generating circuit 204 is coupled to the detector 202, and the comparator 206 is coupled to the detector 202 and the standby signal generating circuit 204. As shown in fig. 1, the detector 202 is used for detecting a first signal FS and a second signal SS of a Universal Serial Bus (USB) device through

pins

208 and 210 of the secondary controller 200, respectively, wherein the first signal FS and the second signal SS are differential pair signals, for example, the first signal FS and the second signal SS can be differential pair signals Data +, Data-of a type or B type of Universal Serial Bus version 2.0, respectively. However, in another embodiment of the present invention, the first signal FS and the second signal SS may be a universal serial bus 3.x version of a-type or B-type differential pair signal Data +, Data-, or a super speed transmitter differential pair signal (super receiver differential pair) StdB _ SSTX +, StdB _ SSTX-, or a super speed receiver differential pair signal (super receiver differential pair) StdB _ SSRX +, StdB _ SSRX-, respectively, where x is 0 or 1. In addition, in another embodiment of the present invention, the first signal FS and the second signal SS may be a C-type differential pair signal Dp1, Dn1 of usb version 3.1, or a super high speed transmitter differential pair signal SSTXp1, SSTXn1, or a super high speed receiver differential pair signal SSRXp1, SSRXn1, respectively. In addition, as shown in fig. 1, the detector 202 is also used for detecting the frequency of the synchronization signal SYN corresponding to the primary side PRI of the power converter 100 by coupling the pin 212 of the secondary controller 200 to the drain of a synchronization switch 102 on the secondary side SEC of the power converter 100, wherein the synchronization switch 102 can ensure that the primary side PRI of the power converter 100 and the secondary side SEC of the power converter 100 are not turned on simultaneously.

As shown in fig. 1, when the secondary controller 200 is coupled to the usb device (not shown in fig. 1), the secondary controller 200 and the primary controller 300 applied to the primary side PRI of the power converter 100 can enable the power converter 100 to operate in a normal mode. However, as shown in fig. 2, when the usb device is disconnected from the secondary controller 200 at time T1, the first signal FS and the second signal SS of the usb device will not be detected by the detector 202. At this time, since the secondary side SEC of the power converter 100 is not coupled to the usb device, the frequency of a gate control signal GCS for controlling the power switch 104 of the primary side PRI of the power converter 100 to turn on and off is reduced, and since the synchronization signal SYN is corresponding to the gate control signal GCS, the frequency of the synchronization signal SYN is also reduced as the frequency of the gate control signal GCS is reduced. As shown in fig. 2, when the detector 200 detects that the frequency of the synchronization signal SYN is less than a first predetermined frequency FPF, the standby signal generating circuit 204 delays a first predetermined time FPT to generate a standby signal STS at a time T2, wherein the standby signal STS is transmitted to the primary controller 300 through the pin 214 of the secondary controller 200 and an optocoupler 106, the first predetermined time FPT is used to prevent the standby signal generating circuit 204 from generating the standby signal STS due to false triggering, and the standby signal STS is a digital signal. In another embodiment of the present invention, however, the standby signal STS is an analog signal or a mixed-mode (mixed-mode) signal. In addition, as shown in fig. 2, since the standby signal STS is transmitted to the primary controller 300 through the pin 214 and the optocoupler 106, the pin 302 of the primary controller 300 receives a corresponding signal corresponding to the standby signal STS. As shown in fig. 2, after the secondary controller 200 generates the standby signal STS, the secondary controller 200 enters a standby mode at time T3, and when the secondary controller 200 enters the standby mode, the secondary controller 200 turns off the circuits in the secondary controller 200 except the detector 202, the standby signal generating circuit 204 and the comparator 206. In addition, the first predetermined frequency FPF may be determined by a minimum operating frequency of the gate control signal GCS of the power converter 100 in the normal mode, for example, the first predetermined frequency FPF may be 1.5-2 times the minimum operating frequency (e.g., 1.5KHz) of the gate control signal GCS, where the minimum operating frequency of the gate control signal GCS is used to improve the problem that the output voltage of the secondary side SEC of the power converter 100 is floated when the secondary side SEC of the power converter 100 is not coupled to a load. The present invention is not limited to the minimum operating frequency of the gate control signal GCS being 1.5 KHz.

In addition, as shown in fig. 2, after the standby signal generating circuit 204 generates the standby signal STS, since the output voltage VOUT of the secondary side SEC of the power converter 100 is controlled by the secondary controller 200, the gate control signal generating circuit 304 of the primary controller 300 generates the gate control signal GCS to boost the output voltage VOUT before the primary controller 300 enters the standby mode according to the standby signal STS, wherein the gate control signal GCS is transmitted to the power switch 104 through the pin of the primary controller 300. Therefore, as shown in fig. 2, the primary controller 300 enters the standby mode at time T4.

Referring to fig. 3, fig. 3 is a schematic diagram illustrating an operation timing sequence after the primary controller 300 and the secondary controller 200 enter the standby mode. As shown in fig. 3, after the secondary controller 200 enters the standby mode, the comparator 206 may compare the output voltage VOUT with a first reference voltage FVREF (e.g., 4.9V or 5.1V) and compare the output voltage VOUT with a second reference voltage SVREF (e.g., 4.8V) after the detector 202 detects the rising edge QRD of the synchronization signal SYN until the detector 200 detects the falling edge QRDR of the synchronization signal SYN. However, the present invention is not limited to the first reference voltage FVREF being 4.9V or 5.1V and the second reference voltage SVREF being 4.8V. Therefore, as shown in fig. 3, at time T1, when the output voltage VOUT is smaller than the first reference voltage FVREF and larger than the second reference voltage SVREF, the comparator 206 generates a comparison signal FCS to the standby signal generating circuit 204, and the standby signal generating circuit 204 generates an on signal TS according to the comparison signal FCS, wherein the on signal TS is transmitted to the primary controller 300 through the pin 214 of the secondary controller 200 and the optocoupler 106, and the on signal TS has a predetermined duty cycle as shown in fig. 3. In addition, the purpose of the turn-on signal TS is to maintain the output voltage VOUT of the secondary side SEC of the power converter 100. As shown in fig. 3, after the pin 302 of the primary controller 300 receives the corresponding signal corresponding to the turn-on signal TS, when the corresponding signal corresponding to the turn-on signal TS on the pin 302 is smaller than a third reference voltage TVREF (time T2), the gate control signal generating circuit 304 generates the gate control signal GCS to the power switch 104, wherein the enabling time of the gate control signal GCS corresponding to the time T2 of fig. 3 makes the detection voltage VCS of the primary side PRI of the power converter 100 reach a minimum value (e.g., 0.3V), and the frequency of the gate control signal GCS is tens of hertz (Hz) in the standby mode.

Referring to fig. 4, fig. 4 is a schematic diagram illustrating an operation timing sequence of the primary controller 300 and the secondary controller 200 entering the normal mode from the standby mode. As shown in fig. 4, after the primary controller 300 and the secondary controller 200 enter the standby mode, if the output voltage VOUT is lower than a low voltage lock out (undervoltage lock out) UVLOOFF at time T1, the secondary controller 200 is turned off. Therefore, as shown in fig. 4, after the gate control signal generating circuit 304 generates the gate control signal GCS to the power switch 104 at time T2 (because the corresponding signal corresponding to the turn-on signal TS on the pin 302 is smaller than the third reference voltage TVREF), if a detector 306 in the primary controller 300 does not detect the corresponding signal corresponding to the turn-on signal TS generated by the standby signal generating circuit 204 within a second predetermined time SPT (e.g., 1 second) after the gate control signal GCS, the primary controller 300 will actively leave the standby mode to enter the normal mode at time T3, wherein the second predetermined time SPT can be determined by the winding 108 of the secondary side SEC of the power converter 100, the output voltage VOUT and the output current IOUT. As shown in fig. 4, after the primary controller 300 enters the normal mode, the output voltage VOUT starts to increase. At time T4, secondary controller 200 restarts entering the normal mode when output voltage VOUT is greater than a low-voltage lockout turn-on voltage uvlon. In addition, after the primary controller 300 enters the standby mode, the primary controller 300 turns off the circuits outside the detector 306 and the gate control signal generating circuit 304 in the primary controller 300, that is, the primary controller 300 turns off the circuits in the primary controller 300 that are not related to the standby mode. For example, as shown in fig. 1, the primary controller 300 will turn off a circuit (not shown in fig. 1) coupled to a feedback pin FB, a compensation pin COMP, an over-temperature protection pin OTP and a current detection pin CS in the primary controller 300, wherein the level of the ground terminal GND2 of the primary controller 300 and the level of the ground terminal GND1 of the secondary controller 200 may be the same or different.

Referring to fig. 5, fig. 5 is a schematic diagram illustrating an operation timing sequence of the primary controller 300 and the secondary controller 200 entering the normal mode from the standby mode. As shown in fig. 5, after the primary controller 300 and the secondary controller 200 enter the standby mode, when the output voltage VOUT is between the first reference voltage FVREF and the second reference voltage SVREF and the frequency of the synchronization signal SYN is greater than a second predetermined frequency (e.g., 10KHz), because the frequency of the synchronization signal SYN is greater than the second predetermined frequency indicating that the secondary side SEC of the power converter 100 is coupled to a load, the standby signal generating circuit 204 of the secondary controller 200 generates a leaving signal LS at a time T3, wherein the leaving signal LS is transmitted to the primary controller 300 through the pin 214 of the secondary controller 200 and the optocoupler 106, the second predetermined frequency may be determined by a time T1 and a time T2, and as shown in fig. 5, the leaving signal LS has a maximum enabling time and the enabling time of the leaving signal LS is greater than the enabling time of the turn-on signal TS. The invention is not limited to the second predetermined frequency being 10 KHz. As shown in fig. 5, after the pin 302 of the primary controller 300 receives the corresponding signal corresponding to the leaving signal LS, the gate control signal generating circuit 304 generates the gate control signal GCS to the power switch 104 when the corresponding signal corresponding to the leaving signal LS on the pin 302 is less than the third reference voltage TVREF (time T4). As shown in fig. 5, when the corresponding signal corresponding to the leaving signal LS is less than the third reference voltage TVREF for a third predetermined time TPT (wherein the third predetermined time TPT is less than the maximum enabling time of the leaving signal LS and is not less than the length of the turn-on signal TS), the gate control signal generating circuit 304 generates the gate control signal GCS at time T4 and the primary controller 300 leaves the standby mode to enter the normal mode according to the gate control signal GCS corresponding to time T4. At this time, since the detector 202 of the secondary controller 200 also detects the synchronization signal SYN corresponding to the time T4, the standby signal generating circuit 204 turns off the leaving signal LS according to the synchronization signal SYN corresponding to the time T4 at the time T5. In addition, after the standby signal generating circuit 204 turns off the leaving signal LS, the secondary controller 200 leaves the standby mode to enter the normal mode.

Referring to fig. 6, fig. 6 is a schematic diagram illustrating an operation timing sequence of the primary controller 300 and the secondary controller 200 entering the normal mode from the standby mode. As shown in fig. 6, after the primary controller 300 and the secondary controller 200 enter the standby mode, if the output voltage VOUT is less than the second reference voltage SVREF in the turn-on signal TS, the standby signal generating circuit 204 of the secondary controller 200 generates the leaving signal LS to the primary controller 300 after the turn-on signal TS (i.e., at time T1) because the output voltage VOUT is less than the second reference voltage SVREF indicating that the secondary side SEC of the power converter 100 is coupled to a heavy load (because the heavy load may cause the output voltage VOUT to rapidly drop), that is, if the output voltage VOUT is less than the second reference voltage SVREF in the turn-on signal TS, the standby signal generating circuit 204 still generates the leaving signal LS to the primary controller 300 after the turn-on signal TS (i.e., at time T1). As shown in fig. 6, after the pin 302 of the primary controller 300 receives the corresponding signal corresponding to the leaving signal LS, the gate control signal generating circuit 304 generates the gate control signal GCS to the power switch 104 when the corresponding signal corresponding to the leaving signal LS on the pin 302 is less than the third reference voltage TVREF (time T2). As shown in fig. 6, when the corresponding signal corresponding to the leaving signal LS is less than the third reference voltage TVREF for the third predetermined time TPT, the gate control signal generating circuit 304 generates the gate control signal GCS at time T3 and the primary controller 300 leaves the standby mode to enter the normal mode according to the gate control signal GCS at time T3. At this time, since the detector 202 of the secondary controller 200 also detects the synchronization signal SYN corresponding to the time T3, the standby signal generating circuit 204 turns off the leaving signal LS according to the synchronization signal SYN corresponding to the time T3 at the time T4. In addition, after the standby signal generating circuit 204 turns off the leaving signal LS, the secondary controller 200 leaves the standby mode to enter the normal mode.

Referring to fig. 7, fig. 7 is a schematic diagram illustrating an operation timing sequence of the primary controller 300 and the secondary controller 200 entering the normal mode from the standby mode. As shown in fig. 7, after the primary controller 300 and the secondary controller 200 enter the standby mode, when the detector 202 detects the first signal FS and the second signal SS at time T1, the standby signal generating circuit 204 generates the leaving signal LS to the primary controller 300 at time T1 because the time T1 is after the turn-on signal TS. As shown in fig. 7, after the pin 302 of the primary controller 300 receives the corresponding signal corresponding to the leaving signal LS, the gate control signal generating circuit 304 generates the gate control signal GCS to the power switch 104 when the corresponding signal corresponding to the leaving signal LS on the pin 302 is less than the third reference voltage TVREF (time T2). As shown in fig. 7, when the corresponding signal corresponding to the leaving signal LS is less than the third reference voltage TVREF for the third predetermined time TPT, the gate control signal generating circuit 304 generates the gate control signal GCS at time T3 and the primary controller 300 leaves the standby mode to enter the normal mode according to the gate control signal GCS at time T3. At this time, since the detector 202 of the secondary controller 200 also detects the synchronization signal SYN corresponding to the time T3, the standby signal generating circuit 204 turns off the leaving signal LS according to the synchronization signal SYN corresponding to the time T3 at the time T4. In addition, after the standby signal generating circuit 204 turns off the leaving signal LS, the secondary controller 200 leaves the standby mode to enter the normal mode.

Referring to fig. 8, fig. 8 is a schematic diagram illustrating an operation timing sequence of the primary controller 300 and the secondary controller 200 entering the normal mode from the standby mode. As shown in fig. 8, after the primary controller 300 and the secondary controller 200 enter the standby mode, when the detector 202 detects the first signal FS and the second signal SS at time T1, but since the time T1 is within the turn-on signal TS, the standby signal generating circuit 204 generates the leaving signal LS to the primary controller 300 after the turn-on signal TS (i.e., at time T2). As shown in fig. 8, after the pin 302 of the primary controller 300 receives the corresponding signal corresponding to the leaving signal LS, the gate control signal generating circuit 304 generates the gate control signal GCS to the power switch 104 when the corresponding signal corresponding to the leaving signal LS on the pin 302 is less than the third reference voltage TVREF (time T3). As shown in fig. 8, when the corresponding signal corresponding to the leaving signal LS is less than the third reference voltage TVREF for the third predetermined time TPT, the gate control signal generating circuit 304 generates the gate control signal GCS at time T4 and the primary controller 300 leaves the standby mode to enter the normal mode according to the gate control signal GCS at time T4. At this time, since the detector 202 of the secondary controller 200 also detects the synchronization signal SYN corresponding to the time T4, the standby signal generating circuit 204 turns off the leaving signal LS according to the synchronization signal SYN corresponding to the time T4 at the time T5. In addition, after the standby signal generating circuit 204 turns off the leaving signal LS, the secondary controller 200 leaves the standby mode to enter the normal mode.

Referring to fig. 1-2, 4-8, 9A, and 9B, fig. 9A and 9B are flowcharts illustrating an operation method of a secondary controller applied to a secondary side of a power converter according to a second embodiment of the present invention. The operation method illustrated in fig. 9A and 9B is explained by using the power converter 100, the secondary controller 200, and the primary controller 300 of fig. 1, and the detailed steps are as follows:

step 900: starting;

step 902: the secondary controller 200 is coupled to the universal serial bus device;

step 904: the secondary controller 200 and the primary controller 300 operate in the normal mode;

step 906: whether the detector 202 does not detect the first signal FS and the second signal SS of the usb device and whether the frequency of the synchronization signal SYN is detected to be less than the first predetermined frequency FPF; if so, go to step 908; if not, jump back to step 904;

step 908: the secondary controller 200 and the primary controller 300 operate in the standby mode accordingly, and perform

steps

910, 914, 916, and 918;

step 910: whether the detector 306 does not detect the corresponding signal corresponding to the turn-on signal TS generated by the standby signal generating circuit 204 within a second predetermined time SPT after the gate control signal GCS; if so, go to step 912; if not, jump back to step 908;

step 912: the primary controller 300 actively leaves the standby mode to enter the normal mode, and the secondary controller 200 enters the normal mode after the primary controller 300 re-operates in the normal mode;

step 914: when the output voltage VOUT is between the first reference voltage FVREF and the second reference voltage SVREF, the detector 202 detects whether the frequency of the synchronization signal SYN is greater than a second predetermined frequency; if yes, go to step 920; if not, jump back to step 908;

step 916: whether the detector 202 detects that the output voltage VOUT is less than the second reference voltage SVREF; if yes, go to step 920; if not, jump back to step 908;

step 918: whether the detector 202 detects the first signal FS and the second signal SS of the universal serial bus device; if yes, go to step 920; if not, jump back to step 908;

step 920: the standby signal generating circuit 204 generates an exit signal LS to the primary controller 300, and the primary controller 300 exits the standby mode accordingly to enter the normal mode, wherein the secondary controller 200 enters the normal mode after the primary controller 300 operates in the normal mode again.

In

steps

902 and 904, the secondary controller 200 and the primary controller 300 may enable the power converter 100 to operate in the normal mode when the secondary controller 200 is coupled to the usb device (not shown in fig. 1).

In step 908, however, as shown in fig. 2, when the usb device is turned off at time T1 and the secondary controller 200 is turned off, the detector 202 will not detect the first signal FS and the second signal SS of the usb device. At this time, since the secondary side SEC of the power converter 100 is not coupled to the usb device, the frequency of the gate control signal GCS is decreased, and since the synchronization signal SYN is the corresponding gate control signal GCS, the frequency of the synchronization signal SYN is also decreased as the frequency of the gate control signal GCS is decreased. As shown in fig. 2, when the detector 200 detects that the frequency of the synchronization signal SYN is less than the first predetermined frequency FPF, the standby signal generating circuit 204 delays by a first predetermined time FPT at a time T2 to generate a standby signal STS, wherein the standby signal STS is transmitted to the primary controller 300 through the pin 214 of the secondary controller 200 and the optical coupler 106, and the standby signal STS is a digital signal. In another embodiment of the present invention, however, the standby signal STS is an analog signal or a mixed mode signal. In addition, as shown in fig. 2, since the standby signal STS is transmitted to the primary controller 300 through the pin 214 and the optocoupler 106, the pin 302 of the primary controller 300 receives a corresponding signal corresponding to the standby signal STS. As shown in fig. 2, after the secondary controller 200 generates the standby signal STS, the secondary controller 200 enters the standby mode at time T3, and after the secondary controller 200 enters the standby mode, the secondary controller 200 turns off the circuits other than the detector 202, the standby signal generating circuit 204 and the comparator 206 in the secondary controller 200.

In step 912, as shown in fig. 4, after the primary controller 300 and the secondary controller 200 enter the standby mode, if the output voltage VOUT is lower than a low voltage lock out (undervoltage lock out) UVLOOFF at time T1, the secondary controller 200 is turned off. Therefore, as shown in fig. 4, after the gate control signal generating circuit 304 generates the gate control signal GCS to the power switch 104 at time T2 (because the corresponding signal corresponding to the turn-on signal TS on the pin 302 is smaller than the third reference voltage TVREF), if the detector 306 in the primary controller 300 does not detect the corresponding signal corresponding to the turn-on signal TS generated by the standby signal generating circuit 204 within the second predetermined time SPT (e.g., 1 second) after the gate control signal GCS, the primary controller 300 will actively leave the standby mode to enter the normal mode at time T3. As shown in fig. 4, after the primary controller 300 enters the normal mode, the output voltage VOUT starts to increase. At time T4, secondary controller 200 restarts entering the normal mode when output voltage VOUT is greater than a low-voltage lockout turn-on voltage uvlon. In addition, after the primary controller 300 enters the standby mode, the primary controller 300 turns off the circuits other than the detector 306 and the gate control signal generating circuit 304 in the primary controller 300.

In step 914, as shown in fig. 5, after the primary controller 300 and the secondary controller 200 enter the standby mode, when the detector 202 detects that the output voltage VOUT is between the first reference voltage FVREF and the second reference voltage SVREF and the frequency of the synchronization signal SYN is greater than a second predetermined frequency (e.g., 10KHz), because the frequency of the synchronization signal SYN is greater than the second predetermined frequency indicating that the secondary side SEC of the power converter 100 is coupled to a load, the standby signal generating circuit 204 of the secondary controller 200 will generate the leaving signal LS at time T3, wherein the leaving signal LS is transmitted to the primary controller 300 through the pin 214 of the secondary controller 200 and the optocoupler 106. As shown in fig. 5, after the pin 302 of the primary controller 300 receives the corresponding signal corresponding to the leaving signal LS, the gate control signal generating circuit 304 generates the gate control signal GCS to the power switch 104 when the corresponding signal corresponding to the leaving signal LS on the pin 302 is less than the third reference voltage TVREF (time T4). As shown in FIG. 5, the gate control signal generating circuit 304 generates the gate control signal GCS at time T4 and the primary controller 300 leaves the standby mode to enter the normal mode according to the gate control signal GCS corresponding to time T4. At this time, the standby signal generating circuit 204 turns off the leaving signal LS at time T5 according to the synchronization signal SYN corresponding to time T4. In addition, after the standby signal generating circuit 204 turns off the leaving signal LS, the secondary controller 200 leaves the standby mode to enter the normal mode.

In step 916, as shown in fig. 6, after the primary controller 300 and the secondary controller 200 enter the standby mode, if the output voltage VOUT is less than the second reference voltage SVREF in the turn-on signal TS, the standby signal generating circuit 204 of the secondary controller 200 generates the leaving signal LS to the primary controller 300 after the turn-on signal TS (i.e. at time T1) because the output voltage VOUT is less than the second reference voltage SVREF indicates that the secondary side SEC of the primary controller 300 is heavily loaded (because the output voltage VOUT is rapidly dropped by the heavy load), that is, if the output voltage VOUT is less than the second reference voltage SVREF in the turn-on signal TS, the standby signal generating circuit 204 still generates the leaving signal LS to the primary controller 300 after the turn-on signal TS (i.e. at time T1). As shown in fig. 6, after the pin 302 of the primary controller 300 receives the corresponding signal corresponding to the leaving signal LS, the gate control signal generating circuit 304 generates the gate control signal GCS to the power switch 104 when the corresponding signal corresponding to the leaving signal LS on the pin 302 is less than the third reference voltage TVREF (time T2). As shown in fig. 6, when the corresponding signal corresponding to the leaving signal LS is less than the third reference voltage TVREF for the third predetermined time TPT, the gate control signal generating circuit 304 generates the gate control signal GCS at time T3 and the primary controller 300 leaves the standby mode to enter the normal mode according to the gate control signal GCS at time T3. At this time, since the detector 202 of the secondary controller 200 also detects the synchronization signal SYN corresponding to the time T3, the standby signal generating circuit 204 turns off the leaving signal LS according to the synchronization signal SYN corresponding to the time T3 at the time T4. In addition, after the standby signal generating circuit 204 turns off the leaving signal LS, the secondary controller 200 leaves the standby mode to enter the normal mode.

In step 918, as shown in fig. 7, after the primary controller 300 and the secondary controller 200 enter the standby mode, when the detector 202 detects the first signal FS and the second signal SS at time T1, the standby signal generating circuit 204 generates the leaving signal LS to the primary controller 300 at time T1 because the time T1 is after the turn-on signal TS. As shown in fig. 7, after the pin 302 of the primary controller 300 receives the corresponding signal corresponding to the leaving signal LS, the gate control signal generating circuit 304 generates the gate control signal GCS to the power switch 104 when the corresponding signal corresponding to the leaving signal LS on the pin 302 is less than the third reference voltage TVREF (time T2). As shown in fig. 7, when the corresponding signal corresponding to the leaving signal LS is less than the third reference voltage TVREF for the third predetermined time TPT, the gate control signal generating circuit 304 generates the gate control signal GCS at time T3 and the primary controller 300 leaves the standby mode to enter the normal mode according to the gate control signal GCS at time T3. At this time, since the detector 202 of the secondary controller 200 also detects the synchronization signal SYN corresponding to the time T3, the standby signal generating circuit 204 turns off the leaving signal LS according to the synchronization signal SYN corresponding to the time T3 at the time T4. In addition, after the standby signal generating circuit 204 turns off the leaving signal LS, the secondary controller 200 leaves the standby mode to enter the normal mode.

In addition, as shown in fig. 8, after the primary controller 300 and the secondary controller 200 enter the standby mode, when the detector 202 detects the first signal FS and the second signal SS at time T1, but since the time T1 is within the turn-on signal TS, the standby signal generating circuit 204 generates the leaving signal LS to the primary controller 300 after the turn-on signal TS (i.e., at time T2). After the standby signal generating circuit 204 generates the leaving signal LS to the primary controller 300, the operation principle of the primary controller 300 and the secondary controller 200 is the same as that of fig. 7, and will not be described again.

In summary, the secondary controller applied to the secondary side of the power converter and the operating method thereof disclosed by the present invention determine that the usb device and the secondary controller are disconnected when the detector of the secondary controller does not detect the first signal and the second signal of the usb device, and the detector of the secondary controller detects that the frequency of the synchronization signal corresponding to the primary side of the power converter is less than the first predetermined frequency. After the secondary controller and the operation method judge that the universal serial bus device and the secondary controller are disconnected, the secondary controller and the operation method enable the secondary controller and the primary controller to enter the standby mode, wherein after the secondary controller and the primary controller enter the standby mode, the secondary controller and the primary controller only start circuits related to the standby mode. Therefore, compared with the prior art, since the secondary controller and the primary controller only turn on the circuits related to the standby mode after the secondary controller and the primary controller enter the standby mode, the power consumption of the power converter, the primary controller and the secondary controller can be reduced by using the standby mode when the universal serial bus device and the secondary controller are disconnected.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A secondary controller for use on a secondary side of a power converter, comprising:

a detector for detecting a first signal and a second signal of a universal serial bus device and a frequency of a synchronous signal corresponding to a primary side of the power converter; and

it is characterized by also comprising:

and a standby signal generating circuit, coupled to the detector, for delaying a first predetermined time to generate a standby signal to the primary controller of the primary side of the power converter when the detector does not detect the first signal and the second signal and the frequency is less than a first predetermined frequency, wherein the primary controller enters a standby mode according to the standby signal.

2. The secondary controller of claim 1, wherein: after the secondary controller generates the standby signal, the secondary controller enters the standby mode, and after the secondary controller enters the standby mode, the secondary controller closes circuits in the secondary controller except the detector, the standby signal generation circuit and a comparator additionally included in the secondary controller.

3. The secondary controller of claim 1, wherein: the first signal and the second signal are a differential pair signal.

4. The secondary controller of claim 1, wherein: the standby signal is an analog signal, a digital signal, or a mixed mode signal.

5. The secondary controller of claim 1, further comprising:

a comparator, configured to compare the output voltage of the secondary side of the power converter with a first reference voltage and compare the output voltage with a second reference voltage until the detector detects a falling edge of the synchronization signal after the detector detects the rising edge of the synchronization signal.

6. The secondary controller of claim 5, wherein: when the output voltage is between the first reference voltage and the second reference voltage, the comparator generates a comparison signal to the standby signal generating circuit, and the standby signal generating circuit generates a turn-on signal to the primary controller according to the comparison signal.

7. The secondary controller of claim 6, wherein: after the standby signal generating circuit generates the starting signal to the primary controller, a grid control signal generating circuit in the primary controller generates a grid control signal to a power switch on the primary side of the power converter according to the starting signal, and the power switch is turned on and off according to the grid control signal.

8. The secondary controller of claim 7, wherein: after the gate control signal generating circuit generates the gate control signal, if a detector in the primary controller does not detect a corresponding signal corresponding to the turn-on signal within a second predetermined time, the primary controller actively leaves the standby mode.

9. The secondary controller of claim 8, wherein: and when the primary controller enters the standby mode, the primary controller shuts down circuits except the detector and the grid control signal generating circuit in the primary controller.

10. The secondary controller of claim 5, wherein: when the output voltage is smaller than the second reference voltage, the standby signal generating circuit generates a leaving signal to the primary controller after a starting signal generated by the standby signal generating circuit, and the primary controller leaves the standby mode according to the leaving signal, wherein the secondary controller leaves the standby mode along with the fact that the primary controller leaves the standby mode.

11. The secondary controller of claim 5, wherein: when the output voltage is between the first reference voltage and the second reference voltage and the frequency is greater than a second predetermined frequency, the standby signal generating circuit generates a leaving signal to the primary controller after a turn-on signal generated by the standby signal generating circuit, and the primary controller leaves the standby mode accordingly, wherein the secondary controller leaves the standby mode as the primary controller leaves the standby mode.

12. The secondary controller of claim 1, wherein: when the detector detects the first signal and the second signal, the standby signal generating circuit generates an exit signal to the primary controller after a start signal generated by the detector, and the primary controller exits the standby mode accordingly, wherein the secondary controller exits the standby mode as the primary controller exits the standby mode.

13. A method of operating a secondary controller applied to a secondary side of a power converter, wherein the secondary controller includes a detector, a standby signal generating circuit, and a comparator, the method comprising:

the detector detects a first signal and a second signal of a universal serial bus device and the frequency of a synchronous signal corresponding to the primary side of the power converter; and

it is characterized by also comprising:

when the detector does not detect the first signal and the second signal and the frequency is less than a first predetermined frequency, the standby signal generating circuit delays for a first predetermined time to generate a standby signal to the primary controller of the primary side of the power converter, wherein the primary controller enters a standby mode according to the standby signal.

14. The method of operation of claim 13, wherein: after the secondary controller generates the standby signal, the secondary controller enters the standby mode, and after the secondary controller enters the standby mode, the secondary controller closes circuits except the detector, the standby signal generating circuit and the comparator in the secondary controller.

15. The method of operation of claim 13, wherein: the first signal and the second signal are a differential pair signal.

16. The method of operation of claim 13, further comprising:

when the detector detects the rising edge of the synchronous signal, the comparator compares the output voltage of the secondary side of the power converter with a first reference voltage and compares the output voltage with a second reference voltage until the detector detects the falling edge of the synchronous signal.

17. The method of operation of claim 16 wherein: when the output voltage is between the first reference voltage and the second reference voltage, the comparator generates a comparison signal to the standby signal generating circuit, and the standby signal generating circuit generates a turn-on signal to the primary controller according to the comparison signal.

18. The method of operation of claim 17 wherein: after the standby signal generating circuit generates the starting signal to the primary controller, a grid control signal generating circuit in the primary controller generates a grid control signal to a power switch on the primary side of the power converter according to the starting signal, and the power switch is turned on and off according to the grid control signal.

19. The method of operation of claim 18 wherein: after the gate control signal generating circuit generates the gate control signal, if a detector in the primary controller does not detect a corresponding signal corresponding to the turn-on signal within a second predetermined time, the primary controller actively leaves the standby mode.

20. The method of operation of claim 19, wherein: and when the primary controller enters the standby mode, the primary controller shuts down circuits except the detector and the grid control signal generating circuit in the primary controller.

21. The method of operation of claim 16 wherein: when the output voltage is smaller than the second reference voltage, the standby signal generating circuit generates a leaving signal to the primary controller after a starting signal generated by the standby signal generating circuit, and the primary controller leaves the standby mode according to the leaving signal, wherein the secondary controller leaves the standby mode along with the fact that the primary controller leaves the standby mode.

22. The method of operation of claim 16 wherein: when the output voltage is between the first reference voltage and the second reference voltage and the frequency is greater than a second predetermined frequency, the standby signal generating circuit generates a leaving signal to the primary controller after a turn-on signal generated by the standby signal generating circuit, and the primary controller leaves the standby mode accordingly, wherein the secondary controller leaves the standby mode as the primary controller leaves the standby mode.

23. The method of operation of claim 13, wherein: when the detector detects the first signal and the second signal, the secondary controller generates a leaving signal to the primary controller after a starting signal generated by the secondary controller, and the primary controller leaves the standby mode according to a corresponding signal corresponding to the leaving signal, wherein the secondary controller leaves the standby mode along with the leaving of the primary controller from the standby mode.