CN108878432A - Memory and process - Google Patents
Memory and process Download PDFInfo
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- CN108878432A CN108878432A CN201810697558.8A CN201810697558A CN108878432A CN 108878432 A CN108878432 A CN 108878432A CN 201810697558 A CN201810697558 A CN 201810697558A CN 108878432 A CN108878432 A CN 108878432A
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- oxide
- layer
- polysilicon
- gate
- side wall
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- 230000015654 memory Effects 0.000 title claims abstract description 33
- 238000000034 method Methods 0.000 title claims description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 50
- 229920005591 polysilicon Polymers 0.000 claims abstract description 48
- 238000007667 floating Methods 0.000 claims abstract description 29
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 21
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 claims abstract description 4
- 230000002093 peripheral effect Effects 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 238000002347 injection Methods 0.000 claims description 10
- 239000007924 injection Substances 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 229910003978 SiClx Inorganic materials 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 230000000717 retained effect Effects 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005265 energy consumption Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000011435 rock Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
Abstract
The invention discloses a kind of memories, there is source region in the trap of substrate, substrate surface has gate oxide, on gate oxide, with the symmetrical structure centered on wordline polysilicon, in the symmetrical two sides of wordline polysilicon, floating gate, insulating medium layer, control gate and silicon nitride layer are up followed successively by from gate oxide；Horizontally, tunnel oxide and offset oxide layer are separated between going back between control gate and silicon nitride layer, with wordline polysilicon；Tunnel oxide is linked together U-shaped that wordline polysilicon is fully wrapped around with gate oxide, is isolated with peripheral structure；Between the tunnel oxide and offset oxide layer, it is separated with one layer of third oxide side wall between going back, is symmetrically distributed in the two sides of wordline polysilicon.The invention also discloses the manufacturing methods of the memory.
Description
Technical field
The present invention relates to semiconductor fields, particularly relate to a kind of non-volatile memory, deposit the invention further relates to described
The manufacturing method of reservoir.
Background technique
In current semiconductor industry, IC products can be divided mainly into three categories type, respectively logic circuit, deposit
Reservoir, analog circuit, wherein memory accounts for sizable ratio in IC products.And in memory, NVM
(Non-volatile Memory), the development of nonvolatile memory is especially rapid.It has it is non-volatile, by byte access, deposit
Store up the characteristics of high and low energy consumption of density, readwrite performance are close to DRAM.Electronic equipment can rapidly access the memory storage space
(in most cases such equipment is all with byte mode to access these contents, and can also save it after power down to content
).It does not have to regularly refresh memory content.This includes the read-only memory (ROM) of form of ownership, seem may be programmed it is read-only
Memory (PROM), erasable programmable read-only memory (EPROM), electricallyerasable ROM (EEROM) (EEPROM) and flash memory.It
Also include battery powered random access memory (RAM) it be mainly characterized by can keep depositing for a long time in the case where not powered
The information of storage, thus had a wide range of applications in multiple fields such as microcomputer, automation controls.As the development of semiconductor technology needs
It wants, it is desirable that be formed simultaneously memory and other devices on the same chip, to form in-line memory.
As shown in Figure 1, be the schematic diagram of the section structure of the memory of a routine, each storage unit include cell1 and
Two units of cell2, when being programmed using SSI (Source Side Injection) programmed method to Cell1, wordline WL and floating
Channel between grid 3 is weak unlatching (Weak inversion), i.e., circle identifies place in figure.Weak length, that is, the word for opening channel
The distance between line WL and floating gate are determined by the thickness of tunnel oxide 11.And high pressure is loaded on control gate 7 at the same time
Cell1 is opened by force, this causes the voltage at the end bit line BL1 to pass to herein, therefore the voltage of BL1 is mainly by this weak conducting
Channel is born by Cell1, thus (Cell1 source side) generates huge peak value electric field at this.Therefore it programs
When thermoelectron injection HCI occur mainly in source (Source Side Injection).
Summary of the invention
Technical problem to be solved by the present invention lies in a kind of memory is provided, enhance the degree of weak unlatching, enhancing storage
The intensity of source power plant when device tube core programs.
Another technical problem to be solved by this invention is to provide the manufacturing method of the memory.
To solve the above problems, memory of the present invention, cross-section structure is that have source region in the trap of substrate, lining
Bottom surface has gate oxide, on gate oxide, has the symmetrical structure centered on wordline polysilicon, in word
The symmetrical two sides of line polysilicon, floating gate, insulating medium layer, control gate and silicon nitride are up followed successively by from gate oxide
Layer；Horizontally, tunnel oxide and offset oxidation are separated between going back between control gate and silicon nitride layer, with wordline polysilicon
Layer；Tunnel oxide is linked together U-shaped that wordline polysilicon is fully wrapped around with gate oxide, is isolated with peripheral structure.
Between the tunnel oxide and offset oxide layer, it is separated with one layer of third oxide side wall between going back, it is symmetrical
In the two sides of wordline polysilicon.
Further, the third oxide side wall between the tunnel oxide and offset oxide layer, thickness is adjustable, and
And the size of different thickness makes to generate different spacing between tunnel oxide and offset oxide layer, for adjusting wordline polycrystalline
Channel region length between silicon and floating gate.
Further, the offset oxide layer is two layers, is formed by depositing superposition twice.
To solve the above problems, the present invention provides the process of the memory, include following processing step：
Step 1 forms trap in the substrate, and in the silicon face of trap, successively deposit covering forms gate oxide, grid polycrystalline silicon
Layer, coating, control gate polysilicon layer and silicon nitride layer, form multilayered structure；
Step 2 defines die region with photoresist, and etch silicon nitride opens silicon nitride layer and forms window；Then oxygen is deposited
SiClx layer and etch form side wall；
Step 3 deposits two layers of silicon oxide dielectric layer and then etches, and forms offset oxide layer；
Step 4 continues to etch down in open window, by coating, floating gate polysilicon layer and the grid oxygen in window
Change layer to etch away, exposes substrate surface；
Step 5 deposits layer of oxide layer, and etching forms third oxide side wall, and the third oxide side wall is attached to
It deviates in oxide layer, the third oxide side wall of the bottom in window is also etched, and exposes substrate surface；
Step 6 deposits one layer of tunnel oxide, and carries out thermal annealing；Tunnel oxide is covered on third oxide side wall
On silicon substrate in upper and window；
Open window remaining space is full of by step 7, depositing polysilicon, return carve polysilicon only retain it is more in window
Crystal silicon；Injection is doped to the polysilicon in window, forms wordline polysilicon；
Step 8 forms floating gate, control gate, makes side wall；Progress LDD, which injects to be formed, after side wall is formed is lightly doped drift
Then area carries out source and drain injection, then carries out thermal anneal process, form device.
Further, the step 1, gate oxide are formed with thermal oxidation method.
Further, the step 2, window are that etching opens silicon nitride layer, and bottom-exposed goes out to control gate polysilicon layer；Oxygen
Change after layer deposit is completed and carry out dry etching, removes the oxide layer in bottom of window and silicon nitride surface, only retain window side
The oxide layer of wall forms side wall.
Further, the thickness of the window sidewall oxide, for defining the length of control gate, the i.e. length of control gate
It is adjusted by the thickness of sidewall oxide.
Further, in the step 3, by depositing two layers of silicon oxide dielectric layer, total thickness of formation is for controlling
Difference in length between subsequent floating gate and control gate, i.e. lower layer's floating gate exceed the length of top level control grid.
Memory of the present invention is programmed using the method for source injection, by tunnel oxide and partially
It moves between oxide layer, increases one layer of third oxide side wall dielectric layer, increase the weak length for opening channel, i.e. wordline polycrystalline
The distance between silicon and floating gate further increase the degree of weak unlatching, the peak value electric field of source when enhancing programming, improve programming
Efficiency.Process of the present invention, simple process are easy to implement.
Detailed description of the invention
Fig. 1 is the sectional structure chart of existing memory.
Fig. 2-9 is present invention process step schematic diagram.
Figure 10 is present invention process flow chart of steps.
Description of symbols
1 is NWELL (N trap), and 2 be floating gate oxide layers, and 3 be the first floating gate/floating gate polysilicon, and 4 be the second floating gate, and 5 be to cover
Cap rock, 6 be side wall, and 7 be the first control gate/control gate polysilicon, and 8 be the second control gate, and 9 be silicon nitride/floating gate side wall, and 10 are
Oxide layer is deviated, 11 be tunnel oxide, and 12 be third oxide side wall, and 13 be wordline (polysilicon).
Specific embodiment
Memory of the present invention is as shown in figure 9, its cross-section structure is that have source region, substrate surface in the trap of substrate
With floating gate oxide layers, on floating gate oxide layers, there is the symmetrical structure centered on wordline polysilicon, in wordline
The symmetrical two sides of polysilicon, floating gate layer, insulating medium layer, control grid layer and nitridation are up followed successively by from gate oxide
Silicon layer；Horizontally, tunnel oxide and offset oxygen are separated between going back between control grid layer and silicon nitride layer, with wordline polysilicon
Change layer, offset oxide layer is two layers, is formed by depositing superposition twice；Tunnel oxide and gate oxide are linked together in U-shaped
Type is fully wrapped around by wordline polysilicon, is isolated with peripheral structure.
Between the tunnel oxide and offset oxide layer, it is separated with one layer of third oxide side wall between going back, it is symmetrical
In the two sides of wordline polysilicon.
Third oxide side wall between the tunnel oxide and offset oxide layer, thickness is adjustable, and different
The size of thickness makes to generate different spacing between tunnel oxide and offset oxide layer, for adjusting wordline polysilicon and floating gate
Between channel region length.
The process that the present invention provides the memory is divided into 8 steps, respective figure 2 comprising following processing step
~9：
Step 1 forms trap in the substrate, and in the silicon face of trap, successively deposit covering forms gate oxide, grid polycrystalline silicon
Layer, coating, control gate polysilicon layer and silicon nitride layer, form multilayered structure.Such as Fig. 2.
Step 2 defines die region with photoresist, and etch silicon nitride opens silicon nitride layer and forms window, the window bottom
Portion exposes control gate polysilicon layer；Then silicon oxide deposition layer, oxide layer deposit carry out dry etching after completing, remove window
Oxide layer on mouth bottom and silicon nitride surface only retains the oxide layer of window side wall, forms side wall.Such as Fig. 3.Window side wall oxygen
Change the thickness of layer, for defining the length of control gate, i.e. the length of control gate is adjusted by the thickness of sidewall oxide.
Step 3 deposits two layers of silicon oxide dielectric layer and then etches, and forms offset oxide layer；By depositing two layers of silica
Dielectric layer, total thickness of formation are used to control the difference in length between subsequent floating gate and control gate, i.e., lower layer's floating gate is beyond upper
The length of layer control gate.Such as Fig. 4.
Step 4 continues to etch down in open window, by coating, floating gate polysilicon layer and the grid oxygen in window
Change layer to etch away, exposes substrate surface.Such as Fig. 5.
Step 5 deposits layer of oxide layer, and etching forms third oxide side wall, and the third oxide side wall is attached to
It deviates in oxide layer, the third oxide side wall of the bottom in window is also etched, and exposes substrate surface.Such as Fig. 6.
Step 6 deposits one layer of tunnel oxide, and carries out thermal annealing；Tunnel oxide is covered on third oxide side wall
On silicon substrate in upper and window.Such as Fig. 7.
Open window remaining space is full of by step 7, depositing polysilicon, return carve polysilicon only retain it is more in window
Crystal silicon；Injection is doped to the polysilicon in window, forms wordline polysilicon.Such as Fig. 8.
Step 8 forms floating gate, control gate, makes side wall；Progress LDD, which injects to be formed, after side wall is formed is lightly doped drift
Then area carries out source and drain injection, then carries out thermal anneal process, form device.Such as Fig. 9.
The above is only a preferred embodiment of the present invention, is not intended to limit the present invention.Come for those skilled in the art
It says, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any modification, equivalent
Replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (8)
1. a kind of memory has source region in the trap of substrate, substrate surface has gate oxide, on gate oxide, tool
There is the symmetrical structure centered on wordline polysilicon, in the symmetrical two sides of wordline polysilicon, from gate oxide
Up it is followed successively by floating gate, insulating medium layer, control gate and silicon nitride layer；Horizontally, control gate and silicon nitride layer, with wordline
Tunnel oxide and offset oxide layer are separated between going back between polysilicon；Tunnel oxide and gate oxide are linked together in U-shaped
Type is fully wrapped around by wordline polysilicon, is isolated with peripheral structure；
It is characterized in that：Between the tunnel oxide and offset oxide layer, it is separated with one layer of third oxide side wall between going back, it is right
Claim the two sides for being distributed in wordline polysilicon.
2. memory as described in claim 1, it is characterised in that：Third between the tunnel oxide and offset oxide layer
Oxide side wall, thickness is adjustable, and the size of different thickness makes to generate not between tunnel oxide and offset oxide layer
Same spacing, for adjusting the channel region length between wordline polysilicon and floating gate.
3. memory as described in claim 1, it is characterised in that：The offset oxide layer is two layers, by depositing twice
Superposition is formed.
4. a kind of process for manufacturing memory as described in claim 1, it is characterised in that：It is walked comprising following technique
Suddenly：
Step 1 forms trap in the substrate, in the silicon face of trap, successively deposit covering formed gate oxide, gate polysilicon layer,
Coating, control gate polysilicon layer and silicon nitride layer, form multilayered structure；
Step 2 defines die region with photoresist, and etch silicon nitride opens silicon nitride layer and forms window；Then silicon oxide deposition
Layer and etch form side wall；
Step 3 deposits two layers of silicon oxide dielectric layer and then etches, and forms offset oxide layer；
Step 4 continues to etch down in open window, by coating, floating gate polysilicon layer and the gate oxide in window
It etches away, exposes substrate surface；
Step 5 deposits layer of oxide layer, and etching forms third oxide side wall, and the third oxide side wall is attached to offset
In oxide layer, the third oxide side wall of the bottom in window is also etched, and exposes substrate surface；
Step 6 deposits one layer of tunnel oxide, and carries out thermal annealing；Tunnel oxide is covered on third third oxide side wall
On silicon substrate in upper and window；
Open window remaining space is full of by step 7, depositing polysilicon, is returned quarter polysilicon and is only retained the polysilicon in window；
Injection is doped to the polysilicon in window, forms wordline polysilicon；
Step 8 forms floating gate, control gate, makes side wall；Side wall carries out LDD after being formed and injects to form lightly doped drift zone, so
Source and drain injection is carried out afterwards, then carries out thermal anneal process, forms device.
5. the process of memory as claimed in claim 4, it is characterised in that：The step 1, gate oxide is with thermal oxide
Method is formed.
6. the process of memory as claimed in claim 4, it is characterised in that：The step 2, window are that etching opens nitrogen
SiClx layer, bottom-exposed go out to control gate polysilicon layer；Oxide layer deposit complete after carry out dry etching, remove bottom of window and
Oxide layer in silicon nitride surface only retains the oxide layer of window side wall, forms side wall.
7. the process of memory as claimed in claim 6, it is characterised in that：The thickness of the window sidewall oxide,
For defining the length of control gate, i.e. the length of control gate is adjusted by the thickness of sidewall oxide.
8. the process of memory as claimed in claim 4, it is characterised in that：In the step 3, by depositing two layers of oxygen
SiClx dielectric layer, total thickness of formation is used to control the difference in length between subsequent floating gate and control gate, i.e. lower layer's floating gate
Length exceeds the control gate on its upper layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810697558.8A CN108878432A (en) | 2018-06-29 | 2018-06-29 | Memory and process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810697558.8A CN108878432A (en) | 2018-06-29 | 2018-06-29 | Memory and process |
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| Publication Number | Publication Date |
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| CN108878432A true CN108878432A (en) | 2018-11-23 |
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| CN201810697558.8A Pending CN108878432A (en) | 2018-06-29 | 2018-06-29 | Memory and process |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109817624A (en) * | 2019-01-22 | 2019-05-28 | 上海华虹宏力半导体制造有限公司 | Memory and its operating method |
| CN113488478A (en) * | 2021-06-09 | 2021-10-08 | 华虹半导体(无锡)有限公司 | NORD Flash device and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102005458A (en) * | 2009-09-02 | 2011-04-06 | 台湾积体电路制造股份有限公司 | Integrated circuit device, memory device and manufacturing method thereof |
| CN102938406A (en) * | 2012-11-21 | 2013-02-20 | 上海宏力半导体制造有限公司 | Split gate type flash memory and forming method thereof |
| CN108091659A (en) * | 2017-11-30 | 2018-05-29 | 上海华虹宏力半导体制造有限公司 | Grid-sharing flash memory unit and preparation method thereof |
-
2018
- 2018-06-29 CN CN201810697558.8A patent/CN108878432A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102005458A (en) * | 2009-09-02 | 2011-04-06 | 台湾积体电路制造股份有限公司 | Integrated circuit device, memory device and manufacturing method thereof |
| CN102938406A (en) * | 2012-11-21 | 2013-02-20 | 上海宏力半导体制造有限公司 | Split gate type flash memory and forming method thereof |
| CN108091659A (en) * | 2017-11-30 | 2018-05-29 | 上海华虹宏力半导体制造有限公司 | Grid-sharing flash memory unit and preparation method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109817624A (en) * | 2019-01-22 | 2019-05-28 | 上海华虹宏力半导体制造有限公司 | Memory and its operating method |
| US10957399B2 (en) | 2019-01-22 | 2021-03-23 | Shanghai Huahong Grace Semiconductor Manufacturing Corporation | Memory and operation method thereof |
| CN113488478A (en) * | 2021-06-09 | 2021-10-08 | 华虹半导体(无锡)有限公司 | NORD Flash device and manufacturing method thereof |
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Application publication date: 20181123 |