CN108878431A - A kind of NOR type floating-gate memory and preparation method - Google Patents
A kind of NOR type floating-gate memory and preparation method Download PDFInfo
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- 230000015654 memory Effects 0.000 title claims abstract description 31
- 238000002360 preparation method Methods 0.000 title claims abstract description 21
- 239000010410 layer Substances 0.000 claims abstract description 73
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 239000011229 interlayer Substances 0.000 claims abstract description 35
- 238000009413 insulation Methods 0.000 claims abstract description 22
- 239000000463 material Substances 0.000 claims description 13
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims description 6
- 239000004411 aluminium Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052735 hafnium Inorganic materials 0.000 claims description 6
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 6
- 229910052715 tantalum Inorganic materials 0.000 claims description 6
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical group [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 6
- 229910052726 zirconium Inorganic materials 0.000 claims description 6
- 238000003860 storage Methods 0.000 abstract description 12
- 238000000034 method Methods 0.000 description 6
- 239000012212 insulator Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The embodiment of the invention provides a kind of NOR type floating-gate memory and preparation methods, including：Substrate；It is formed in source electrode, drain electrode and the channel region of the substrate surface, the source electrode and drain electrode is located at the two sides of the channel region；The tunnel oxide and floating gate being formed in above the channel region；It is formed in the side wall insulating layer of the floating gate side walls；The isolated insulation layer being formed in above the source electrode and the drain electrode；The interlayer insulating film being formed in above the isolated insulation layer, the side wall insulating layer and the floating gate；It is formed in the control gate of the top of the interlayer insulating film；It is formed in the wordline of the top of the control gate；The source-drain electrode is multiplexed with bit line.The embodiment of the invention provides a kind of NOR floating-gate memory and preparation method, eliminates active area in traditional structure and simplify device architecture to the contact hole of bit line, reduce the size of each storage unit.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, especially design a kind of NOR type floating-gate memory and preparation method.
Background technique
The advantages that NOR type floating-gate memory is due to high integration, low-power consumption, high reliability and high performance-price ratio, non-volatile
Main share is occupied in property storage market.
But with the development of microelectric technique, NOR type floating-gate memory is also encountered by a series of challenge, such as lower function
Consumption, faster speed, higher integrated level etc..
The most advanced process node of existing NOR type FGS floating gate structure is 45nm process node, each storage under the node
Device cell area is greater than 0.02um2, and each device is at least needed comprising one from active area to bit line metal connecting layer
Metal contact hole.
Summary of the invention
In view of this, eliminating traditional structure the embodiment of the invention provides a kind of NOR floating-gate memory and preparation method
Middle active area simplifies device architecture to the contact hole of bit line, reduces the size of each storage unit.
In a first aspect, the embodiment of the invention provides a kind of NOR type floating-gate memories, including：
Substrate；
It is formed in source electrode, drain electrode and the channel region of the substrate surface, the source electrode and drain electrode is located at the channel
The two sides in area；
The tunnel oxide and floating gate being formed in above the channel region；
It is formed in the side wall insulating layer of the floating gate side walls；
The isolated insulation layer being formed in above the source electrode and the drain electrode；
The interlayer insulating film being formed in above the isolated insulation layer, the side wall insulating layer and the floating gate；
It is formed in the control gate of the top of the interlayer insulating film；
It is formed in the wordline of the top of the control gate；
The source electrode and the drain electrode are multiplexed with bit line.
Optionally, the dielectric constant that the interlayer insulating film is is greater than or equal to 9.
Optionally, the material of the interlayer insulating film is tantalum base oxide film, aluminium base sull, hafnium base oxide
Any one in film and zirconium base sull.
Optionally, the thickness range of the interlayer insulating film be less than or equal to
Second aspect, the embodiment of the invention provides a kind of preparations for preceding claim NOR type floating-gate memory
Method, including：
Substrate is provided；
Source electrode, drain electrode and channel region, the source electrode and drain electrode, which are formed, in the substrate surface is located at the channel region
Two sides；
Side sequentially forms tunnel oxide and floating gate on the channel region；
Side wall insulating layer is formed in the floating gate side walls；
Isolated insulation layer is formed above the source electrode and the drain electrode；
Interlayer insulating film is formed above the isolated insulation layer, the side wall insulating layer and the floating gate；
Control gate is formed above the interlayer insulating film；
Wordline is formed in the top of the control gate；
The source electrode and the drain electrode are multiplexed with bit line.
Optionally, source electrode, drain electrode and channel region are formed in the substrate surface, the source electrode and drain electrode is located at described
The two sides of channel region；Side sequentially forms tunnel oxide and floating gate on the channel region；Side wall is formed in the floating gate side walls
Insulating layer specifically includes：
Channel region is formed in the substrate surface；
Side sequentially forms tunnel oxide, floating gate and protection insulating layer on the channel region；
It etches the tunnel oxide, the floating gate and the protection insulating layer and forms multiple grooves, expose the groove
The channel region of two sides；
Side wall insulating layer is formed in the side wall of the floating gate；
Source electrode and drain electrode is formed on the channel region surface of the groove two sides, the source electrode and drain electrode is located at institute
State the two sides of channel region.
Optionally, source electrode and drain electrode, the source electrode and drain electrode point are formed on the channel region surface of the groove two sides
Wei Yu not further include after the two sides of the channel region：
Isolated insulation layer is formed above the source electrode and the drain electrode；
The protection insulating layer is removed, the floating gate is exposed.
Optionally, source electrode, drain electrode and channel region are formed in the substrate surface, the source electrode and drain electrode is located at described
The two sides of channel region；Side sequentially forms tunnel oxide on the channel region and floating gate specifically includes：
In the substrate, successively top forms tunnel oxide and temporarily isolating insulating layer；
It etches the tunnel oxide and temporarily isolating insulating layer forms multiple grooves, expose the substrate；
Channel region, tunnel oxide and floating gate are sequentially formed in the substrate surface；
The tunnel oxide below the temporarily isolating insulating layer and the temporarily isolating insulating layer is removed, described
Substrate surface forms source electrode and drain electrode, and the source electrode and described drain are located at the two sides of the channel region.
Optionally, the dielectric constant that the interlayer insulating film is is greater than or equal to 9.
Optionally, the material of the interlayer insulating film is tantalum base oxide film, aluminium base sull, hafnium base oxide
Any one in film and zirconium base sull.
Prior art neutrality line is connect by conductive via with source electrode and drain electrode, there are the problem of there are two, in a first aspect,
Due to the presence of conductive via, structure is complicated for device, second aspect, needs to reserve the position of conductive via in the devices,
Increase the size of device.The embodiment of the invention provides a kind of NOR type floating-gate memory and preparation method, by by source electrode and
Drain electrode is multiplexed with bit line (Bit Line, BL), eliminates active area in traditional structure and simplifies device junction to the contact hole of bit line
Structure reduces the size of each storage unit.
Detailed description of the invention
Illustrate made detailed description of non-limiting embodiments referring to the following drawings by reading, it is of the invention
Other features, objects and advantages will become apparent.
Fig. 1 a is a kind of top view for NOR type floating-gate memory that the embodiment of the present invention one provides；
Fig. 1 b is the sectional view in the direction A-A in Fig. 1 a；
Fig. 1 c is the sectional view in the direction B-B in Fig. 1 a；
Fig. 1 d is the sectional view in the direction C-C in Fig. 1 a；
Fig. 1 e is the sectional view in the direction D-D in Fig. 1 a；
Fig. 2 is that second embodiment of the present invention provides a kind of flow diagrams of NOR type floating-gate memory preparation method；
Fig. 3 a- Fig. 3 l is a kind of each step of the preparation method of NOR type floating-gate memory provided by Embodiment 2 of the present invention
Corresponding sectional view.
Specific embodiment
To further illustrate the technical scheme of the present invention below with reference to the accompanying drawings and specific embodiments.It is understood that
It is that specific embodiment described herein is used only for explaining the present invention rather than limiting the invention.It further needs exist for illustrating
, only the parts related to the present invention are shown for ease of description, in attached drawing rather than entire infrastructure.
Embodiment one
Fig. 1 a is a kind of top view for NOR type floating-gate memory that the embodiment of the present invention one provides；Fig. 1 b is A-A in Fig. 1 a
The sectional view in direction；Fig. 1 c is the sectional view in the direction B-B in Fig. 1 a；Fig. 1 d is the sectional view in the direction C-C in Fig. 1 a；Fig. 1 e is figure
The sectional view in the direction D-D in 1a.
Referring to Fig. 1 b, the present invention provides a kind of NOR type floating-gate memory, which includes：Substrate 10；It is formed
In the source electrode 11 on 10 surface of substrate, drain electrode 12 and channel region 13, source electrode 11 is located at the two sides of channel region 13 with drain electrode 12；Shape
At the tunnel oxide 14 and floating gate 15 above channel region 13；It is formed in the side wall insulating layer 16 of 15 side wall of floating gate；It is formed in
The isolated insulation layer 17 of 12 top of source electrode 11 and drain electrode；It is formed in 15 top of isolated insulation layer 17, side wall insulating layer 16 and floating gate
Interlayer insulating film 18；It is formed in the control gate 19 of 18 top of interlayer insulating film；It is formed in the wordline 20 of 19 top of control gate；Source
Pole 11 and drain electrode 12 are multiplexed with bit line.
Prior art neutrality line is connect by conductive via with source electrode and drain electrode, there are the problem of there are two, in a first aspect,
Due to the presence of conductive via between bit line metal layer and source electrode or drain electrode, structure is complicated for device, second aspect, in device
The middle position for needing to reserve conductive via, increases the size of device.The embodiment of the invention provides a kind of NOR type floating gates to deposit
Reservoir eliminates source electrode 11 and drain electrode in traditional structure by the way that source electrode 11 and drain electrode 12 are multiplexed with bit line (Bit Line, BL)
12 arrive the contact hole of bit line, simplify device architecture, reduce the size of each storage unit.
Referring to Fig. 1 a, the present invention provides a kind of NOR type floating-gate memories, it can be seen that the NOR type floating-gate memory packet
Include multiple wordline 20 and multiple spacer insulator layers 21.The setting of spacer insulator layer 21 is to protect exposed source electrode 11 and drain electrode
12.It is the sectional view in the direction B-B in Fig. 1 a referring to Fig. 1 c, from the figure, it can be seen that substrate 10；It is formed in 10 surface of substrate
Source electrode 11 perhaps drain 12 be formed in source electrode 11 or drain electrode 12 top isolated insulation layer 17 and spacer insulator layer 21；It is formed
Interlayer insulating film 18 above isolated insulation layer 17；It is formed in the control gate 19 of the top of interlayer insulating film 18；It is formed in control
The wordline 20 of 19 tops of grid processed.Referring to Fig. 1 d, from the figure, it can be seen that being formed in the channel region 13 on 10 surface of substrate, formed
Tunnel oxide 14, floating gate 15 and spacer insulator layer 21 above channel region 13；It is formed in the layer insulation of 15 top of floating gate
Layer 18；It is formed in the control gate 19 of the top of interlayer insulating film 18；It is formed in the wordline 20 of 19 top of control gate.Referring to Fig. 1 e,
Fig. 1 e is the sectional view in the direction D-D in Fig. 1 a, from the figure, it can be seen that substrate 10, is formed in source electrode 11, the leakage on 10 surface of substrate
Pole 12 and channel region 13, source electrode 11 and drain electrode 12 are located at the two sides of channel region 13；It is formed in source electrode 11, drain electrode 12 and channel
The spacer insulator layer 21 of 13 top of area.
Referring to Fig. 1 a, Fig. 1 b, Fig. 1 c and Fig. 1 d, the NOR type that the embodiment of the present invention schematically illustrates two rows four column is deposited
Reservoir, the structure including 8 storage units, wherein each storage unit is vertically determined by wordline and bit line.Referring in Fig. 1 a
Region 30, the floor map of a storage unit, illustratively, the length of L1 are 50nm, and the length of L2 is 110nm, L3
Length be 25nm, the length of L4 is 30nm, the planar dimension 0.017um of each storage unit 302。
Optionally, based on the above technical solution, the dielectric constant that interlayer insulating film 18 is is greater than or equal to 9.It is high
Dielectric constant material comparison Conventional dielectric constant material can obtain bigger electricity when reducing same physical thickness
Hold density.From the perspective of from another angle, in the case where needing to obtain same capacitance density, high dielectric constant material can be maintained more
The electric leakage rank of big film thickness, corresponding film also will be lower.In NOR type floating-gate memory, floating gate 15 and control gate 19 it
Between using dielectric constant be greater than or equal to 9 interlayer insulating film 18, can satisfy the miniature demand at present to memory device so that
Each storage unit has corresponding Physical scaling down size, but electrical property is kept as far as possible.Optionally, the material of interlayer insulating film 18
It can be any in tantalum base oxide film, aluminium base sull, hafnium base oxide film and zirconium base sull
It is a kind of, it should be noted that be not limited in these materials.Optionally, based on the above technical solution, interlayer insulating film
18 thickness range be less than or equal to
Embodiment two
Fig. 2 is a kind of flow diagram of the preparation method of NOR type floating-gate memory provided by Embodiment 2 of the present invention；Figure
3a- Fig. 3 l is a kind of corresponding section of each step of the preparation method of NOR type floating-gate memory provided by Embodiment 2 of the present invention
Figure.It is invented based on same design, the embodiment of the invention provides a kind of preparation methods of NOR floating-gate memory, with Fig. 1 a, figure
For 1b, Fig. 1 c and NOR floating-gate memory shown in Fig. 1 d, referring to fig. 2, the preparation method of NOR floating-gate memory includes as follows
Step：
Step 110 provides substrate.
Referring to Fig. 3 a, substrate 10 is provided, substrate 10 is provided, the material selection of substrate 10 can be illustratively silicon, nitridation
The semiconductor materials such as gallium GaAs.Its conduction type can be p-type, or N-type.
Step 120 is located at the two of channel region in substrate surface formation source electrode, drain electrode and channel region, source electrode and drain electrode
Side.
Step 130, side sequentially forms tunnel oxide and floating gate over the channel region.
Step 140 forms side wall insulating layer in floating gate side walls.
Step 150 forms isolated insulation layer above source electrode and drain electrode.
Optionally step 120, step 130, step 140 and step 150 specifically comprise the following steps：
Referring to Fig. 3 b, channel region 13 is formed on 10 surface of substrate.
Referring to Fig. 3 c, tunnel oxide 14, floating gate 15 and protection insulating layer 22 are sequentially formed above channel region 13.
Referring to Fig. 3 d, etches tunnel oxide 14, floating gate 15 and protection insulating layer 22 and form multiple grooves 23, expose groove
The channel region 13 of 23 two sides；
Referring to Fig. 3 e, side wall insulating layer 16 is formed in the side wall of floating gate 15.
Referring to Fig. 3 f, source electrode 11 and drain electrode 12, source electrode 11 and drain electrode 12 are formed on 13 surface of channel region of 23 two sides of groove
It is located at the two sides of channel region 13.It should be noted that source electrode 11 and drain 12 ionic type generally with channel region 13
Ionic type, illustratively can be on the contrary, therefore form source electrode 11 and drain electrode 12 on 13 surface of channel region of 23 two sides of groove
The ion opposite with channel region conduction type is injected in the region of the corresponding source electrode 11 of channel region 13 and drain electrode 12.
Optionally, based on the above technical solution, 11 He of source electrode is formed on 13 surface of channel region of 23 two sides of groove
Drain electrode 12, source electrode 11 and drain electrode 12 further include after being located at the two sides of channel region 13：
Referring to Fig. 3 g, isolated insulation layer 17 is formed above source electrode 11 and drain electrode 12；
Referring to Fig. 3 h, removal protection insulating layer 22 exposes floating gate 15.Illustratively, isolated insulation layer 17, floating gate 15 and side
The flush of wall insulating layer 16.
Optionally, step 120 and step 130 can also be formed by following steps：
Referring to Fig. 3 i, in substrate 10, successively top forms tunnel oxide 14 and temporarily isolating insulating layer 24；
Referring to Fig. 3 j, etches tunnel oxide 14 and temporarily isolating insulating layer 24 forms multiple grooves 23, expose substrate 10；
Referring to Fig. 3 k, channel region 13, tunnel oxide 14 and floating gate 15 are sequentially formed on 10 surface of substrate；
Referring to Fig. 3 l, the tunnel oxide 14 of 24 lower section of temporarily isolating insulating layer 24 and temporarily isolating insulating layer is removed,
Source electrode 11 and drain electrode 12 are formed on 10 surface of substrate, source electrode 11 and drain electrode 12 are located at the two sides of channel region 13.
Source electrode 11, drain electrode 12 and channel region 13,12 difference of source electrode 11 and drain electrode are formed in substrate surface by above-mentioned steps
Positioned at the two sides of channel region 13；To sequentially form tunnel oxide 14 and floating gate 15 above channel region 13 for mask plate, in channel
The method that the two sides in area form source electrode 11 and drain electrode 12 advantageously reduces the resistance and junction depth of source electrode 11 and drain electrode 12, more preferable full
Sufficient source electrode 11 and drain electrode 12 are multiplexed with the case where bit line needs alap resistance.
Step 160 forms interlayer insulating film above isolated insulation layer, side wall insulating layer and floating gate；
By taking Fig. 1 b as an example, interlayer insulating film 18 is formed above isolated insulation layer 17, side wall insulating layer 16 and floating gate 15.It can
Selection of land, the dielectric constant that interlayer insulating film 18 is are greater than or equal to 9.Optionally, the material of interlayer insulating film 18 can be tantalum base
Any one in sull, aluminium base sull, hafnium base oxide film and zirconium base sull.
Step 170 forms control gate above interlayer insulating film；
By taking Fig. 1 b as an example, control gate 19 is formed above interlayer insulating film 18.
Step 180 forms wordline in the top of control gate；
By taking Fig. 1 b as an example, wordline 20 is formed above control gate 19.The examples of materials of wordline 20 it can choose metal
Silicide.
It should be noted that source electrode 11 and drain electrode 12 are multiplexed with bit line.Prior art neutrality line passes through conductive via and source
Pole and drain electrode connection, there are the problem of there are two, in a first aspect, due to mistake conductive between bit line metal layer and source electrode or drain electrode
The presence in hole, structure is complicated for device, second aspect, needs to reserve the position of conductive via in the devices, increases device
Size.The embodiment of the invention provides a kind of preparation methods of NOR type floating-gate memory, by answering source electrode 11 and drain electrode 12
With for bit line (Bit Line, BL), eliminates source electrode and drain electrode in traditional structure and simplify device junction to the contact hole of bit line
Structure, reduces the size of each storage unit, to reduce the size of NOR type floating-gate memory.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above embodiments to the present invention
It is described in further detail, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, also
It may include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (10)
1. a kind of NOR type floating-gate memory, which is characterized in that including：
Substrate；
It is formed in source electrode, drain electrode and the channel region of the substrate surface, the source electrode and drain electrode is located at the channel region
Two sides；
The tunnel oxide and floating gate being formed in above the channel region；
It is formed in the side wall insulating layer of the floating gate side walls；
The isolated insulation layer being formed in above the source electrode and the drain electrode；
The interlayer insulating film being formed in above the isolated insulation layer, the side wall insulating layer and the floating gate；
It is formed in the control gate of the top of the interlayer insulating film；
It is formed in the wordline of the top of the control gate；
The source electrode and the drain electrode are multiplexed with bit line.
2. NOR type floating-gate memory according to claim 1, which is characterized in that
The dielectric constant that the interlayer insulating film is is greater than or equal to 9.
3. according to right to go 2 described in NOR type floating-gate memory, which is characterized in that
The material of the interlayer insulating film is tantalum base oxide film, aluminium base sull, hafnium base oxide film and zirconium
Any one in base oxide film.
4. NOR type floating-gate memory according to claim 2, which is characterized in that
The thickness range of the interlayer insulating film be less than or equal to
5. a kind of preparation method of the NOR type floating-gate memory for Claims 1 to 4, which is characterized in that including：
Substrate is provided；
Source electrode, drain electrode and channel region, the source electrode and drain electrode, which are formed, in the substrate surface is located at the two of the channel region
Side；
Side sequentially forms tunnel oxide and floating gate on the channel region；
Side wall insulating layer is formed in the floating gate side walls；
Isolated insulation layer is formed above the source electrode and the drain electrode；
Interlayer insulating film is formed above the isolated insulation layer, the side wall insulating layer and the floating gate；
Control gate is formed above the interlayer insulating film；
Wordline is formed in the top of the control gate；
The source electrode and the drain electrode are multiplexed with bit line.
6. preparation method according to claim 5, which is characterized in that
Source electrode, drain electrode and channel region, the source electrode and drain electrode, which are formed, in the substrate surface is located at the two of the channel region
Side；Side sequentially forms tunnel oxide and floating gate on the channel region；It is specific that side wall insulating layer is formed in the floating gate side walls
Including：
Channel region is formed in the substrate surface；
Side sequentially forms tunnel oxide, floating gate and protection insulating layer on the channel region；
It etches the tunnel oxide, the floating gate and the protection insulating layer and forms multiple grooves, expose the groove two sides
The channel region；
Side wall insulating layer is formed in the side wall of the floating gate；
Source electrode and drain electrode is formed on the channel region surface of the groove two sides, the source electrode and drain electrode is located at the ditch
The two sides in road area.
7. preparation method according to claim 6, which is characterized in that
Source electrode and drain electrode is formed on the channel region surface of the groove two sides, the source electrode and drain electrode is located at the ditch
After the two sides in road area, further include：
Isolated insulation layer is formed above the source electrode and the drain electrode；
The protection insulating layer is removed, the floating gate is exposed.
8. preparation method according to claim 5, which is characterized in that
Source electrode, drain electrode and channel region, the source electrode and drain electrode, which are formed, in the substrate surface is located at the two of the channel region
Side；Side sequentially forms tunnel oxide on the channel region and floating gate specifically includes：
In the substrate, successively top forms tunnel oxide and temporarily isolating insulating layer；
It etches the tunnel oxide and temporarily isolating insulating layer forms multiple grooves, expose the substrate；
Channel region, tunnel oxide and floating gate are sequentially formed in the substrate surface；
The tunnel oxide below the temporarily isolating insulating layer and the temporarily isolating insulating layer is removed, in the substrate
Surface forms source electrode and drain electrode, and the source electrode and described drain are located at the two sides of the channel region.
9. preparation method according to claim 5, which is characterized in that
The dielectric constant that the interlayer insulating film is is greater than or equal to 9.
10. according to right to go 9 described in preparation method, which is characterized in that
The material of the interlayer insulating film is tantalum base oxide film, aluminium base sull, hafnium base oxide film and zirconium
Any one in base oxide film.
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| US20050093079A1 (en) * | 2003-11-01 | 2005-05-05 | Samsung Electronics Co., Ltd. | Erasable and programmable read only memory (EPROM) device and method of manufacturing a semiconductor device having the same |
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