CN108878354A - A kind of production method of cmos tft and LTPS array substrate - Google Patents
A kind of production method of cmos tft and LTPS array substrate Download PDFInfo
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- CN108878354A CN108878354A CN201810697290.8A CN201810697290A CN108878354A CN 108878354 A CN108878354 A CN 108878354A CN 201810697290 A CN201810697290 A CN 201810697290A CN 108878354 A CN108878354 A CN 108878354A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
Abstract
This application discloses a kind of cmos tft and the production method of LTPS array substrate, the method includes：Substrate is provided, active layer, grid layer and photoresist layer are sequentially formed on substrate, wherein active layer includes first area, second area and third region；Photoresist layer is patterned using one of light shield, so that second area is not covered by photoresist layer, first area and third region are covered by remaining photoresist；First degree doping is carried out to second area；Remaining photoresist is removed；Second degree doping is carried out to first area.By the above-mentioned means, the application can reduce the light shield quantity in processing procedure, shorten fabrication cycle, reduces cost of manufacture.
Description
Technical field
This application involves field of display technology, more particularly to a kind of cmos tft and the system of LTPS array substrate
Make method.
Background technique
Thin film transistor (TFT) (Thin-Film Transistor, TFT) technology can be divided into polysilicon (Poly-Si) technology with it is non-
Crystal silicon (a-Si) technology, the difference of the two are that transistor characteristic is different.Compared with traditional A-Si technology, low temperature polycrystalline silicon (Low
Temperature Poly-Silicon, LTPS) although technology complex process, because it is with higher carrier mobility,
It is widely used in the production of small-medium size high-resolution TFT LCD and AMOLED panel.LTPS is according to its production method, mainly
It is divided into N-type metal-oxide semiconductor (MOS) (Negative channel Metal Oxide Semiconductor, NMOS), p-type
Metal-oxide semiconductor (MOS) (Positive channel MetalOxide Semiconductor, PMOS) and complementary metal oxygen
Compound semiconductor (Complementary Metal Oxide Semiconductor, CMOS), wherein NMOS transistor and PMOS
The main distinction of transistor is set source-drain electrode contact zone respectively by N-type ion heavy doping and P-type ion heavy doping institute
It is formed, and NMOS transistor and PMOS transistor collectively constitute CMOS transistor.
For present inventor in long-term R&D process, NMOS and PMOS driving circuit, CMOS driving are compared in discovery
Circuit is more stable, and process window is bigger, but light shield needed for corresponding tft array substrate production is more, production
Period is longer.This is because needing pair nmos transistor and the source-drain electrode contact zone of PMOS transistor to distinguish in CMOS technology
N-type ion heavy doping and P-type ion heavy doping are carried out, and is needed before ion implanting respectively by one of light shield (Mask) technique shape
At photoresist layer pattern, to protect PMOS or NMOS device, avoid phosphonium ion (P+) being mixed to PMOS transistor or by boron ion
(B+) NMOS transistor is mixed.In existing making technology, usually first pair nmos transistor carries out phosphonium ion heavy doping, then shape
Boron ion heavy doping is carried out at gate pattern layer, then pair pmos transistor, specifically please refers to Fig. 1-4, Fig. 1-4 is existing skill
The flow diagram of one embodiment of production method of cmos tft in art.The production method includes：In PMOS device
With photoresist layer is formed on NMOS device, photoresist layer is patterned using light shield, retains the photoresist above PMOS device,
NMOS device is exposed, carries out phosphonium ion heavy doping to NMOS device and forms N-channel.Grid are formed in PMOS device and NMOS device
Pole layer 101 and photoresist layer 102, pattern photoresist layer 102 using light shield, retain the photoresist above grid cabling area
(shown in Fig. 1)；Etching removes exposed grid layer, is formed gate pattern 201 (shown in Fig. 2).Pair nmos transistor and PMOS are brilliant
Body pipe carries out phosphonium ion and is lightly doped (shown in Fig. 3).Photoresist layer is formed in PMOS device and NMOS device, using light shield to photoresist
Layer is patterned, and the photoresist 402 above NMOS device is retained, and PMOS device is exposed, has been formed above PMOS device at this time
Grid, grid, which shelters from middle section, makes the source/drain exposure at both ends, carries out boron ion heavy doping to both ends source-drain electrode contact zone
It is formed P-channel (shown in Fig. 4).
Manufacturing process as above needs multiple tracks light shield technique, and for the processing procedure of amorphous silicon, production technology is complex,
And whole equipment investment is excessive too low with yield, cost of manufacture is increase accordingly, and therefore, how to effectively reduce LTPS CMOS
The fabrication cycle of array substrate promotes production production capacity and reduces cost, is the emphasis of current panel industry concern.
Summary of the invention
The application is mainly solving the technical problems that provide the production of a kind of cmos tft and LTPS array substrate
Method can reduce the light shield quantity in processing procedure, shorten fabrication cycle, reduce cost of manufacture.
In order to solve the above technical problems, the technical solution that the application uses is：A kind of cmos tft is provided
Production method, the method includes：Substrate is provided, active layer, grid layer and photoresist layer are sequentially formed on substrate, wherein having
Active layer includes the of the first area for the doping of the first type, the second area for second type doping and corresponding grid cabling area
Three regions；Photoresist layer is patterned using one of light shield, so that second area is not covered by photoresist layer, first area is by
One remaining photoresist covers, and third region is covered by the second remaining photoresist, wherein the thickness of the second remaining photoresist is greater than the first residue
The thickness of photoresist；First degree doping is carried out to the second area of active layer；First remaining photoresist is removed；To active layer
First area carry out the second degree doping.
In order to solve the above technical problems, another technical solution that the application uses is：A kind of low temperature polycrystalline silicon battle array is provided
The production method of column substrate, the production method include the production method of above-mentioned cmos tft, wherein CMOS film crystal
The production method of pipe includes：Substrate is provided, active layer, grid layer and photoresist layer are sequentially formed on substrate, wherein active layer packet
Include the first area for the doping of the first type, for the second area of second type doping and the third area in corresponding grid cabling area
Domain；Photoresist layer is patterned using one of light shield, so that second area is not covered by photoresist layer, first area is remained by first
Remaining light resistance covering, third region are covered by the second remaining photoresist, wherein the thickness of the second remaining photoresist is greater than the first remaining photoresist
Thickness；First degree doping is carried out to the second area of active layer；First remaining photoresist is removed；To the of active layer
One region carries out the second degree doping.
The beneficial effect of the application is：It is in contrast to the prior art, the application provides a kind of cmos tft
And the production method of LTPS array substrate, this method can be realized two using one of light shield technique by the design of change light shield
Road adulterates process, can reduce the light shield quantity in processing procedure, shortens fabrication cycle, reduces cost of manufacture, improves array substrate
Make production capacity.
Detailed description of the invention
Fig. 1 be cmos tft in the prior art one embodiment of production method in photoresist layer is patterned
Schematic diagram；
Fig. 2 is the signal that gate pattern is formed in one embodiment of production method of cmos tft in the prior art
Figure；
Fig. 3 is that progress phosphonium ion is low-doped in one embodiment of production method of cmos tft in the prior art
Schematic diagram；
Fig. 4 is that boron ion heavy doping is carried out in one embodiment of production method of cmos tft in the prior art
Schematic diagram；
Fig. 5 is the flow diagram of the application cmos tft production method first embodiment；
Fig. 6 is formation active layer, grid layer, photoresist in the application cmos tft production method second embodiment
The schematic diagram of layer；
Fig. 7 is to carry out patterned show to photoresist layer in the application cmos tft production method second embodiment
It is intended to；
Fig. 8 is the schematic diagram that gate pattern is formed in the application cmos tft production method second embodiment；
Fig. 9 is the signal that the first degree doping is carried out in the application cmos tft production method second embodiment
Figure；
Figure 10 is the schematic diagram that remaining photoresist is removed in the application cmos tft production method second embodiment；
Figure 11 is the schematic diagram that gate pattern is formed in the application cmos tft production method second embodiment；
Figure 12 is to carry out showing for the second degree doping in the application cmos tft production method second embodiment
It is intended to.
Specific embodiment
It is right as follows in conjunction with drawings and embodiments to keep the purpose, technical solution and effect of the application clearer, clear
The application is further described.
The application provides a kind of cmos tft and the production method of LTPS array substrate passes through in the method
The design for changing light shield can be realized twice doping process using one of light shield technique, can reduce the light shield quantity in processing procedure,
Shorten fabrication cycle, reduces cost of manufacture, improve the production production capacity of array substrate.
Referring to Fig. 5, Fig. 5 is the flow diagram of the application cmos tft production method first embodiment.
In the embodiment, the production method of cmos tft includes the following steps：
S501：Substrate is provided, active layer, grid layer and photoresist layer are sequentially formed on substrate, wherein active layer includes using
First area in the doping of the first type, the second area for second type doping and the third region for corresponding to grid cabling area.
Wherein, which is transparent substrate, can be glass substrate, quartz base plate or plastic base, in other embodiment party
It can also be other substrates in formula, it is not limited here.Active layer is polysilicon layer；Grid layer is metal layer, such as aluminum metal layer.
S502：Photoresist layer is patterned using one of light shield, so that second area is not covered by photoresist layer, the firstth area
Domain is covered by the first remaining photoresist covering, third region by the second remaining photoresist, wherein the thickness of the second remaining photoresist is greater than the
The thickness of one remaining photoresist.
Wherein it is possible to the different zones in light shield paste the films of different light transmittances, to realize that it is different saturating that different zones have
Photosensitiveness, so as to form different patterns after photoresist layer exposure development.
S503：First degree doping is carried out to the second area of active layer.
Wherein it is possible to carry out the first degree doping by the way of diffusion or ion implanting.At this point, first area is remaining
Photoresist covering, is not influenced by doping.
S504：First remaining photoresist is removed.
Wherein, the first remaining photoresist is removed in the way of dry etching or Ultrasonic Heating.
S505：Second degree doping is carried out to the first area of active layer.
Wherein it is possible to carry out the second degree doping by the way of diffusion or ion implanting.
In this embodiment, by changing the design of light shield, twice doping work can be realized using one of light shield technique
Sequence can reduce the light shield quantity in processing procedure, shorten fabrication cycle, reduce cost of manufacture, improve the production production capacity of array substrate.
Optionally, in one embodiment, the first type is doped to n-type doping, and second type is doped to p-type doping, corresponding
N-type transistor and P-type transistor is made.
Specifically, n-type doping is to make the N of two high-dopant concentrations in one piece of lower P-type silicon substrate of doping concentration
+ area, and two electrodes are drawn with metallic aluminium in the area, make drain electrode d and source electrode s respectively；P-type is doped in N-type silicon substrate
On, the area P+ of two high-dopant concentrations is made, and draw two electrodes with metallic aluminium in the area, makees drain electrode d and source respectively
Pole s.N-type doping further includes low concentration doping, to form LDD (Lightly Doped Drain lightly doped drain) area, by low
Doped in concentrations profiled can improve hot carrier's effect.
Fig. 6-12 is please referred to, Fig. 6-12 is the stream of the application cmos tft production method second embodiment
Journey schematic diagram.In this embodiment, the production method of the application cmos tft is described in detail, is specifically included
Following steps：
Light shield layer 602, buffer layer 603 and polysilicon layer are sequentially formed on substrate 601.
Wherein, using chemical vapor deposition CVD or physical vapour deposition (PVD) PVD method on substrate 601 deposition of amorphous silicon layers and
Molybdenum layer, to form light shield layer 602.
It is deposited on light shield layer 602 using chemical vapor deposition CVD or physical vapour deposition (PVD) PVD method and forms silicon nitride
(SiNx) layer 6031, deposition forms silica (SiOx) layer 6032, silicon nitride (SiNx) layer on silicon nitride (SiNx) layer 6031
6031 and silica (SiOx) layer 6032 constitute buffer layer 603.Wherein, silicon nitride (SiNx) layer 6031 is mainly used for isolation glass
Sodium and potassium plasma in substrate, silica (SiOx) layer 6032 is primarily as insulating layer, to improve and polysilicon layer connects
Touching.
Deposition forms amorphous silicon layer on buffer layer 603, and deposition forms silicon oxide layer, silicon oxide layer point on amorphous silicon layer
Not Dui Ying the first amorphous silicon section and the second amorphous silicon section, using silicon oxide layer as light shield to the first amorphous silicon section and the second amorphous silicon
Duan Jinhang quasi-molecule laser annealing processing forms the first polysilicon layer 6041 of corresponding first transistor npn npn and corresponds to second type
Second polysilicon layer 6042 of transistor, the first polysilicon layer 6041 include the fourth region for the doping of the first type.
The second photoresist layer is formed on the first polysilicon layer 6041 and the second polysilicon layer 6042；Using the second light shield to
Two photoresist layers are patterned, so that the second transistor npn npn is covered by photoresist, the first transistor npn npn is exposed, to the first polysilicon layer
The fourth region carry out the doping of third degree, formed N-channel, be also possible to the heavy doping of other ions of the same clan of phosphonium ion.This
When, the second transistor npn npn is covered by remaining photoresist, is not influenced by doping.Wherein, third degree is doped to phosphonium ion heavy doping, phosphorus
The doping concentration of ion heavy doping is 1x1014~1x1015ions/cm2。
Insulating layer 605, grid layer 606 and light are sequentially formed on the first polysilicon layer 6041 and the second polysilicon layer 6042
Resistance layer 607 (shown in Fig. 6).
Wherein, polysilicon layer include for the first type doping first area, for second type doping second area and
The third region in corresponding grid cabling area；Photoresist layer 607 is patterned using one of light shield 608, so that second area is not
It being covered by photoresist layer, first area is covered by the first remaining photoresist 6071, and third region is covered by the second remaining photoresist 6072,
In the thickness of the second remaining photoresist 6072 be greater than the thickness of the first remaining photoresist 6071 (shown in Fig. 7).Wherein, photoresist layer is positivity
Photoresist layer, light shield 608 include full transparent area 6081, semi-opaque region 6082 and opaque area 6083, accordingly, light shield 608 it is complete
Full-trans-parent film, semi-permeable membrane and impermeable membrane post respectively in transparent area 6081, semi-opaque region 6082 and opaque area 6083, to realize difference
The translucency in region is different.
Exposed grid layer is removed using dry etching and forms gate pattern, specifically can use the mixed of fluorocarbons and chlorine
Gas is closed to be etched (shown in Fig. 8) exposed grid layer.
First degree doping (shown in Fig. 9) is carried out to the second area of polysilicon layer, forms P-channel.Wherein it is possible to using
The mode of diffusion or ion implanting carries out the heavy doping of boron.At this point, the second area of polysilicon layer is covered by remaining photoresist, not by
Doping influences.First degree is doped to boron ion heavy doping, is also possible to the heavy doping of other ions of the same clan of boron ion, mixes
Miscellaneous concentration is 1x1014~1x1015ions/cm2。
First remaining photoresist 6071 is purged, to expose first area (Figure 10 institute for the doping of the first type
Show).Wherein, the first remaining photoresist is etched using dry etching, it is specific that ash is carried out to the first remaining photoresist using oxygen
Change, i.e., removes the first remaining photoresist in such a way that oxygen burns up resistance.It in other embodiments can also be using Ultrasonic Heating
Mode removes the first remaining photoresist.
The grid layer of etching removal covering first area (shown in Figure 11)；Specifically exposed grid is removed using dry etching
Layer forms gate pattern, and the mixed gas that can use fluorocarbons and chlorine is etched exposed grid layer.
Second remaining photoresist is purged；The second remaining photoresist can be removed in such a way that oxygen burns up resistance, it can also be with
Using the remaining photoresist of other modes removing second.
Second degree doping, (shown in Figure 12) are carried out to the first area of polysilicon layer.Wherein, the second degree is doped to phosphorus
Ion is lightly doped, and this time doping concentration is lower, can improve hot carrier's effect.It in other embodiments, can also be in shape
It is lightly doped at phosphonium ion is carried out to the first area of polysilicon layer before grid layer.
The application also provides a kind of production method of low temperature polycrystalline silicon array substrate, and this method includes above-mentioned CMOS film
The production method of transistor, referring specifically to the description of above embodiment, details are not described herein.In this embodiment, lead to
Crossing one of light shield technique can be realized twice doping process, can reduce the light shield quantity in processing procedure, shorten fabrication cycle, reduce
Cost of manufacture improves the production production capacity of array substrate.
The foregoing is merely presently filed embodiments, are not intended to limit the scope of the patents of the application, all to utilize this
Equivalent structure or equivalent flow shift made by application specification and accompanying drawing content, it is relevant to be applied directly or indirectly in other
Technical field similarly includes in the scope of patent protection of the application.
Claims (10)
1. a kind of production method of cmos tft, which is characterized in that the method includes：
Substrate is provided, sequentially forms active layer, grid layer and photoresist layer on the substrate, wherein the active layer includes being used for
The third region of first area, the second area and corresponding grid cabling area that are adulterated for second type that first type adulterates；
The photoresist layer is patterned using one of light shield, so that the second area is not covered by photoresist layer, described
One region is covered by the first remaining photoresist covering, the third region by the second remaining photoresist, wherein the described second remaining photoresist
Thickness be greater than the thickness of the described first remaining photoresist；
First degree doping is carried out to the second area of the active layer；
Described first remaining photoresist is removed；
Second degree doping is carried out to the first area of the active layer.
2. the production method of cmos tft according to claim 1, which is characterized in that described to use one of light shield
The photoresist layer is patterned, so that the second area is not covered by photoresist layer, the first area is by the first residue
Photoresist covering, the third region are covered by the second remaining photoresist, wherein the thickness of the described second remaining photoresist is greater than described the
The thickness of one remaining photoresist includes：
The light shield includes full transparent area, semi-opaque region and opaque area, and the semi-opaque region corresponds to the first area, described
Opaque area corresponds to the third region, and the full transparent area corresponds to the second area and other remaining areas.
3. the production method of cmos tft according to claim 1, which is characterized in that described to the of active layer
Two regions carry out：
Exposed grid layer is etched using the mixed gas of fluorocarbons and chlorine, to form gate pattern.
4. the production method of cmos tft according to claim 1, which is characterized in that described to the first remaining light
Resistance be removed including：
The described first remaining photoresist is ashed using oxygen, to remove the described first remaining photoresist.
5. the production method of cmos tft according to claim 1, which is characterized in that the active layer is polycrystalline
Silicon layer, active layer, grid layer and the photoresist layer of sequentially forming on substrate include：
Light shield layer, buffer layer and amorphous silicon layer are sequentially formed on the substrate；
Excimer laser processing is carried out to the amorphous silicon layer, forms the first polysilicon layer of corresponding first transistor npn npn and right
The second polysilicon layer of the second transistor npn npn is answered, first polysilicon layer includes the fourth region for the doping of the first type；
The second photoresist layer is formed on first polysilicon layer and second polysilicon layer；
Second photoresist layer is patterned using the second light shield, so that the fourth region is not covered by photoresist layer；
The doping of third degree is carried out to the fourth region of first polysilicon layer；
The insulating layer, grid layer and photoresist layer are sequentially formed on first polysilicon layer and second polysilicon layer.
6. the production method of cmos tft according to claim 5, which is characterized in that the third degree doping
Phosphonium ion heavy doping is carried out for the fourth region to first polysilicon layer, the phosphonium ion doping concentration is 1x1014~
1x1015ions/cm2。
7. the production method of cmos tft according to claim 1, which is characterized in that first type is doped to
N-type doping, the second type are doped to p-type doping；The concentration of the first degree doping is greater than second degree doping
Concentration.
8. the production method of cmos tft according to claim 7, which is characterized in that the first degree doping
Boron ion heavy doping is carried out for the second area to the active layer, the boron ion doping concentration is 1x1014~
1x1015ions/cm2, second degree is doped to carry out phosphonium ion to the first area of the active layer to be lightly doped.
9. a kind of production method of low temperature polycrystalline silicon array substrate, which is characterized in that the method includes such as claim 1-8 to appoint
The production method of cmos tft described in one, the production method of the cmos tft include：
Substrate is provided, sequentially forms active layer, grid layer and photoresist layer on the substrate, wherein the active layer includes being used for
The third region of first area, the second area and corresponding grid cabling area that are adulterated for second type that first type adulterates；
The photoresist layer is patterned using one of light shield, so that the second area is not covered by photoresist layer, described
One region is covered by the first remaining photoresist covering, the third region by the second remaining photoresist, wherein the described second remaining photoresist
Thickness be greater than the thickness of the described first remaining photoresist；
First degree doping is carried out to the second area of the active layer；
Described first remaining photoresist is removed；
Second degree doping is carried out to the first area of the active layer.
10. the production method of low temperature polycrystalline silicon array substrate according to claim 9, which is characterized in that described to use one
Road light shield patterns the photoresist layer, so that the second area is not covered by photoresist layer, the first area is by
One remaining photoresist covering, the third region are covered by the second remaining photoresist, wherein the thickness of the described second remaining photoresist is greater than
The thickness of the first remaining photoresist includes：
The light shield includes full transparent area, semi-opaque region and opaque area, and the semi-opaque region corresponds to the first area, described
Opaque area corresponds to the third region, and the full transparent area corresponds to the second area and other remaining areas.
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| CN110047800A (en) * | 2019-04-18 | 2019-07-23 | 武汉华星光电技术有限公司 | Array substrate and preparation method thereof |
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