CN108876736A - A kind of image alias removing method based on FPGA - Google Patents
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Abstract
The present invention discloses a kind of image alias removing method based on FPGA, includes the following steps：Step A, the RGB image that will enter into FPGA carry out gradation conversion, obtain the grey scale signal that value is 0-255；Conversion gained gray level image is carried out the image preprocessing of mean filter, reduces the sharp transformation of the gray value of image by step B；Gray level image is carried out wavelet decomposition by step C, is decomposed into the low frequency component I comprising original image essential informationLLWith the high fdrequency component I comprising original image detailsHH, and to ILLIt decomposes again and obtains its low frequency component ILL；Step D, using Canny operator to ILH1Processing, and image reconstruction is carried out, it is final to obtain the image information for eliminating alias.Such method carries out alias elimination based on FPGA, by the picture signal of input, while guaranteeing the real-time of image processing algorithm, and the customization function that the IP kernel of FPGA can be made full use of to have, meet more specific requirements.
Description
Technical field
The invention belongs to technical field of image processing, are related to a kind of image alias removing method based on FPGA, tool
It says to body, is related to a kind of realizing that the edge thinning processing of image more particularly to wavelet transformation are mutually tied with Canny operator using FPGA
It closes, realizes the elimination of image alias.
Background technique
Denoising is a basic problem of image procossing, general thoughts be by being repaired the characteristics of research specific noise or
Restore noisy acoustic image, image denoising, image segmentation, in terms of have important application.Wherein image
Marginal texture texture information is able to reflect the essential characteristic and important information of picture material, and traditional Filtering Model is in image denoising
It always will lead to the loss of marginal information to a certain extent in treatment process, therefore effective image denoising can be reached by finding one kind
The method of effect and energy Protect edge information information is most important.Due to the shortage of prior information, Denoising Problems often with there is pathosis, because
This needs to be accurately reflected known variables using the mathematical method such as partial differential equation (PDE) and be become about time and space
Restricting relation between the derivative of amount.Eulerian equation is acquired by first establishing " energy function ", then by the calculus of variations, with certain physics
Corresponding PDE is established in process analogy.
With the development of computer technology, traditional images noise-removed technology is realized by PC machine mostly, even if its denoising effect
Fruit is relatively obvious, it is contemplated that it is based on PC machine system operatio, disadvantage is also apparent from for example at high cost, and volume is big, stability difference etc.,
And FPGA has the advantage of parallel pipelining process, this mechanism assigns its higher speed ability, there is logical resource abundant in piece
The performance of unit, FPGA structure design is big, flexible and changeable, it is ensured that requirement of real-time in most cases is based on
The R&D cycle of FPGA is also relatively short, more can be conveniently extended to system structure based on designed, designed special project IP kernel is required,
FPGA and the joint development of High Performance SCM and DSP can take into account processing speed and calculated performance simultaneously, can bring to user
More smooth and high quality sensory experience.
Summary of the invention
The purpose of the present invention is to provide a kind of image alias removing method based on FPGA, based on FPGA,
The picture signal of input is subjected to alias elimination.Image processing algorithm is realized in FPGA hardware platform, is guaranteeing image
While the real-time of Processing Algorithm, and the customization function that the IP kernel of FPGA can be made full use of to have, meet more specific
Demand.The combination of FPGA and image processing techniques improves the practicality of system design, and with the continuous improvement of FPGA performance,
Its processing speed is getting faster, and the functional module being internally integrated is more and more, and the performance of detection method can become better and better.
In order to achieve the above objectives, solution of the invention is：
A kind of image alias removing method based on FPGA, includes the following steps：
Step A, the RGB image that will enter into FPGA carry out gradation conversion, obtain the grey scale signal that value is 0-255；
Conversion gained gray level image is carried out the image preprocessing of mean filter, reduces the point of the gray value of image by step B
Sharp transformation；
Gray level image is carried out wavelet decomposition by step C, is decomposed into the low frequency component I comprising original image essential informationLL
With the high fdrequency component I comprising original image detailsHH, and to ILLIt decomposes again and obtains its low frequency component ILL；
Step D, using Canny operator to ILH1Processing, and image reconstruction is carried out, it is final to obtain the figure for eliminating alias
As information.
In above-mentioned steps A and step B, the input of RGB image signal, the synchronous letter of row clock of going forward side by side are carried out to FPGA from outside
Number；To RGB color image by conversion program, gray level image after conversion is filtered by clock sync signal and image mean value
Wave-path sequence is attached.
The detailed process of above-mentioned steps B is：
Step B1, input data is cached, and two-dimensional transform processor reads data, and selected ruler from FIFO caching
The very little mask for being 5 × 5, and slide mask and carry out image traversal to realize filtering；
Step B2 regards 5 × 5 masks as a two-dimensional array, the continuous row based on row data, carries out 5 line numbers first
According to sum operation, input data is continuously made a call to 4 bats, and current data form 5 beat of data, by two two-phases of 3 clocks
Add operation, obtains the sum of continuous 5 data；
Step B3 when first row data and is acquired when carrying out 5 row data and progress column direction summation operation
When, it is cached into line data, the summed result of one-dimensional line direction is taken into capable caching, until subsequent 4 data arrive, 5
Row data summed result carries out column direction summation, and structure is identical as row summation structure；
Operation divided by 25 is converted to 9 shifting functions and 7 sub-additions and operated by step B4, be finally completed mask be 5 ×
5 Image Mean Filtering.
The detailed process of above-mentioned steps C is：
Step C1, image resolve into low frequency component I after the transformation of primary rowLLWith high fdrequency component IHH；
Step C2, by low frequency component ILLIt converts again and once obtains 2 low frequency component ILL1, ILH1, by high fdrequency component IHHBecome again
It changes and once obtains 2 high fdrequency component IHL1, IHH1；
Step C3, then to low frequency component ILL1Step C1 is repeated, wavelet decomposition rank transformation needed for completing.
In above-mentioned steps D, using Canny operator to ILH1The detailed process of processing is：
Step D11, smoothing processing use mask for 5 × 5 and standard deviation be 1.4 Gaussian kernel carry out gaussian filtering, obtain
Smooth component information；
Step D12 opens a window to smooth rear image using Sobel operator, in image level direction and is hung down by 3 × 3 masks
Histogram calculates modulus value and the direction of gradient to being filtered；
Step D13, aforementioned Sobel operator calculate gradient modulus value and direction 3 × 3 mask on the basis of, find out
Pixel local maximum, so that gray value corresponding to non-maximum point is set to 0；
Step D14 eliminates alias by hysteresis threshold segmentation using dual-threshold voltage.
In above-mentioned steps D13, the method for finding out pixel local maximum is：By 8 pixels centered on intermediate pixel,
Be separated into 8 quadrants, and cross that central pixel point does oblique line and the intersection point of 8 gradient directions carries out distinguishing interpolation, thus by with
Whether comparing interpolation and judge the maximum value of central pixel point.
In above-mentioned steps D, the detailed process for carrying out image reconstruction is：
Step D21, by Canny operator treated low frequency component ILH10It is brought into reconstructed module；
Step D22, in reconstructed module, configure two divided-frequency clock CLK1, be responsible for coordinated control data flow prediction and
Interleaved computation and output are carried out in update module；
Step D23, when current pixel is carrying out prediction calculating, next pixel data is directly inputted to update module meter
It calculates, input prediction module calculates next one pixel data again；
Step D24, pixel data input update module after prediction calculating calculate output, are directly entered and update calculating
Data could export after participating in prediction.
After adopting the above scheme, compared with prior art, the present invention having the following technical effects：
(1) in terms of the complexity of method, the information content that method needs is few, and method is simple, need to only carry out color image
Gradation conversion is detected using low frequency component of the Canny operator to wavelet decomposition after image preprocessing, finally carries out figure
As reconstruct；
(2) in terms of the timeliness of method, because an of the invention information content needed of setting about is few, the complexity of implementation
It is low, to reduce the processing time of method；
(3) image detecting method based on FPGA is with a wide range of applications, and different IP can be customized by specific requirements
Core, and design result is reusable；
(4) based on the concurrency of FPGA, algorithm can be made to carry out realization of High Speed, complicated treatment process may be implemented；
(5) FPGA has powerful expansion, and FGPA is designed based on hardware language, has outstanding portable
Property.
Detailed description of the invention
Fig. 1 is flow chart of the invention；
Fig. 2 is that FPGA realizes two dimension summation exploded view in the present invention；
Fig. 3 is that FPGA realizes continuous data stream summation schematic diagram in the present invention；
Fig. 4 is that FPGA realizes two-dimensional wavelet transformation schematic diagram in the present invention；
Fig. 5 is that FPGA realizes Canny operator operation schematic diagram in the present invention；
Fig. 6 is that FPGA realizes Sobel operator operation schematic diagram in the present invention；
Fig. 7 is that FPGA realizes Canny operator gradient direction schematic diagram in the present invention；
Fig. 8 is that FPGA realizes wavelet transformation logic chart in the present invention；
Fig. 9 is that FPGA realizes wavelet reconstruction structure chart in the present invention；
Figure 10 is elimination alias image schematic diagram in the present invention.
Specific embodiment
Below with reference to attached drawing, technical solution of the present invention and beneficial effect are described in detail.
The present invention provides a kind of image alias removing method based on FPGA, includes the following steps：
Step A, the RGB image that will enter into FPGA carry out gradation conversion, obtain the grey scale signal that value is 0-255, so as to
It is subsequent to be handled；
In the step A, rgb space includes the chrominance signal in three channels, and the main signal of human eye cognition image is
Luminance signal, therefore three channel signals of rgb space are converted into single channel grey scale signal by classical formula, it is easy to simultaneously
FPGA carries out add operation, multiplying and shift operation.
Conversion gained gray level image is carried out the image preprocessing of mean filter, by the gray value for reducing image by step B
Sharp transformation, achieve the purpose that reduce noise；
In step A and step B, the input of RGB image signal, row clock synchronization signal of going forward side by side are carried out to FPGA from outside；
To RGB color image by conversion program, gray level image after conversion is passed through into clock sync signal and Image Mean Filtering
Program is attached；
Gray level image is carried out wavelet decomposition by step C, is decomposed into the low frequency comprising the most of essential informations of original image
Component (ILL) and high fdrequency component (I comprising original image detailsHH)；
Step D utilizes Canny operator gray level image low frequency component (I resulting to wavelet decompositionLH1) processing, and carry out figure
It is final to obtain the image information for eliminating alias as reconstruct.
As the present invention is based on the further prioritization scheme of image alias removing method of FPGA, operated in detail
Journey is as follows：The present invention is based on the flow diagram of the image alias removing method of FPGA as shown in Figure 1, main utilize
The resources such as FPGA piece inner multiplication device, internal storage and logic unit are under the control of the synchronization signals such as row, the field of vision signal
Realize the color space conversion of vision signal, image preprocessing, Canny edge detection, morphological erosion operation and last
Profile simply extracts several big modules, the edge vision signal of final output single pixel precision.
In view of the main clock synchronization information of FPGA, when pixel, row, column signal isochronon synchronization signal arrive, by
Clock control program sufficiently calls the Resources on Chip such as multiplier built in FPGA, memory and important logic unit, to input
Viewdata signal completes RGB color to the conversion in greyscale color space, Image Mean Filtering pre-process, image wavelet divides
Solution, Canny operator operation and wavelet reconstruction etc., it is final to realize the output for eliminating image alias.
Wherein, viewdata signal is transformed into greyscale color space, i.e. color transform module by RGB color,
Formula is：
Gray=0.30 × R+0.59 × G+0.11 × B (1)
In the intrinsic call multiplier and adder of FPGA, herein respectively by three road signals of the RGB color of input
Corresponding multiplying is carried out respectively, the result of caching is subjected to summation operation, and shift operation finally is done to summation acquired results, this
When obtain the gray value of image data pixel 0-255, formula is：
Gray=(300 × R+590 × G+110 × B+500) > > 10 (2)
Gray level image is attached by clock sync signal with Image Mean Filtering preprocessing module after converting.Figure
As preprocessing module, primarily to reducing the sharp transformation of the gray value of image, achieve the purpose that reduce noise.Mean value herein
The mask of filtering is 5 × 5, is designed using flowing structure, image is exactly a two-dimensional array, any two-dimensional calculating step
One-dimensional operation can be turned to, Change-over knot composition as shown in Fig. 2, its line direction sum structure as shown in figure 3, by 25 pixels
The problem of averaging is converted into the add operation that FPGA is good at processing, and concrete operations are as follows：
1) input data is cached, two-dimensional transform processor reads data from FIFO caching, and selected size is 5
× 5 mask, and slide mask and carry out image traversal to realize filtering；
2) 5 × 5 masks can regard a two-dimensional array as, the continuous row based on row data, therefore carry out 5 row data first
Input data is continuously played 4 bats by sum operation, in addition current data forms 5 beat of data, is transported by the addition two-by-two of 3 clocks
It calculates, the sum of continuous 5 data can be obtained；
3) it is carrying out by 5 row data and when carrying out column direction summation operation, it, need to be into when first row data and when acquiring
Line data caching, takes capable caching for the summed result of one-dimensional line direction, needs until subsequent 4 data arrive, 5 rows
Data summed result carries out column direction summation, and structure is identical as row summation structure；
4) in order to avoid FPGA carries out division arithmetic, the operation divided by 25 is converted into 9 shifting functions herein and 7 times add
Method operation, is no overhead operations since shifting function will not consume the clock cycle, therefore for FPGA, and being finally completed mask is 5 × 5
Image Mean Filtering.
Treated image is controlled by synchronised clock, is input to wavelet transformation module, carries out wavelet decomposition, it is right
Pixel data in one 5 × 5 mask does sum operation with coefficient, is related to additions and multiplications, small to two-dimensional discrete herein
Wave conversion uses fixed-point number operation.The shock response of lifting wavelet transform and formula are herein：
Wherein h (t) is discrete-time system function, and gray level image formerly resolves into high and low frequency after the transformation of primary row
Two subbands, then 4 frequency subbands are obtained through a rank transformation；Again to low frequency sub-band (ILL1) repeat before step can be completed
The method of next stage wavelet decomposition rank transformation is handled, and the principle steps of two-dimensional wavelet transformation are as shown in Figure 4.Concrete operations are such as
Under：
1) image resolves into low frequency component (I after the transformation of primary rowLL) and high fdrequency component (IHH)；
2) by low frequency component (ILL) convert once obtain 2 low frequency component (I againLL1, ILH1), by high fdrequency component (IHH)
It converts again and once obtains 2 high fdrequency component (IHL1, IHH1)；
3) again to low frequency component (ILL1) repeat before step, wavelet decomposition rank transformation needed for completing.
Wherein after three-level two-dimensional wavelet transformation, the possible maximum value of low frequency sub-band coefficient is gray level image：
Wherein, h (t) is discrete-time system function, and L is series.
After above-mentioned processing, call Canny operator module to low frequency component (I hereinLH1) be further processed.
As shown in figure 5, to be smoothed when Canny operator operation, gradient calculates, non-maximum value inhibits and hysteresis threshold segmentation four
A step is handled, and detailed step is as follows：
1) smoothing processing use mask for 5 × 5 and standard deviation be 1.4 Gaussian kernel carry out gaussian filtering, smoothly divided
Measure information.It is as follows that the normalization of its mask is rounded result：
2) it is opened a window using Sobel operator to smooth rear image, by 3 × 3 masks in image level direction and vertical direction
It is filtered, it is as shown in Figure 6 to calculate step.If the filtering template in the direction x and y is respectively GXAnd GY, respectively such as table 1, table 2
It is shown：
Table 1 filters template GX
| -1 | 0 | +1 |
| -2 | 0 | +2 |
| -1 | 0 | +1 |
Table 2 filters template GY
| +1 | +2 | +1 |
| 0 | 0 | 0 |
| -1 | -2 | -1 |
If gx(x, y) is the filter result in the direction x, gy(x, y) is the filter result in the direction y, then gradient modulus value g (x, y) has
Following formula：
Gradient direction angle calculation formula is：
3) when carrying out the inhibition of non-maximum value, the modulus value of gradient and 3 × 3 masks in direction are calculated in the above Sobel operator
On the basis of, pixel local maximum is found out, so that gray value corresponding to non-maximum point is set to 0.As shown in fig. 7,
a0~a8This 8 pixels are with current pixel point a4Centered on, 4 big quadrant is separated into 8 small quadrants, wherein vectorFor
Current pixel point a4Gradient direction.In order to determine a4It whether is maximum regional value, the intersection point m on gradient direction1And m2Carry out line
Property interpolation, utilizes a2And a5To m1Interpolation assessment, utilizes a3And a6To m2Interpolation assessment.If a4a5Distance be x, a5m1Distance
For y, interpolating function f, then interpolation result is：
If the calculated result is Result, then have：
When by above-mentioned Algorithm mapping to FPGA, in order to eliminate division arithmetic, do with down conversion：
x·f(m1)=ya2+(x-y)·a5 (11)
x·f(m2)=ya6+(x-y)·a3 (12)
Using same procedure, the interpolation result in the case of other three kinds can be obtained, it is as follows：
y·f(m3)=xa2+(y-x)·a1 (14)
y·f(m4)=xa6+(y-x)·a7 (15)
y·f(m5)=xa0+(y-x)·a1 (17)
y·f(m6)=xa8+(y-x)·a7 (18)
x·f(m7)=ya3+(x-y)·a0 (20)
x·f(m8)=ya5+(x-y)·a8 (21)
In order to eliminate x, the otherness of y does above-mentioned formula with down conversion：
Mmax·f(mX)=Mmin·C0+(Mmax-Mmin)·C1 (23)
Mmax·f(mY)=Mmin·C2+(Mmax-Mmin)·C3 (24)
In above formula, MmaxIndicate the larger value in current x and y direction gradient value, MminIndicate current x and y direction degree gradient
Smaller value in value, f (mX) and f (mY) all indicate interpolation, C0, C1, C2, C3Then respectively represent 4 interpolation elements.Not for 8
Same small quadrant, the call number of interpolation element can be as obtained by inquiry table 3：
Table 3
By whether obtained interpolation result judges the maximum value of central pixel point above, and effectively carry out non-maximum value suppression
System.
4) alias is eliminated by hysteresis threshold segmentation, uses dual-threshold voltage herein.By the way that two threshold values are arranged,
In the available image of high threshold based on setting marginal information, therefore alias can seldom occur in the image, but threshold is arranged
Value is higher, and the edge that may result in image can not be closed, and avoids this situation from occurring using other Low threshold is arranged herein, most
Canny operator processing result is obtained eventually.
Finally, by Canny operator treated low frequency component (ILH10) it is brought into reconstructed module.As shown in figure 8, reconstructing
In module, two divided-frequency clock CLK1 is configured, is responsible for coordinated control data flow and carries out interleaved computation in prediction and update module
And output.Wherein, the structure chart of wavelet reconstruction is as shown in figure 9, as seen from the figure, prediction type is：
It is the unlike signs exchange outside decomposition transform process type (26) and (27) bracket known to the reconstruct knowledge of small echo
Can, therefore the anti-prediction type of the process is：
Wherein, when current pixel is carrying out prediction calculating, next pixel data can be directly inputted to update module calculating,
Input prediction module calculates next one pixel data again；Pixel data input update module after prediction calculates calculates
Output, and could be exported after being directly entered the data needs participation prediction for updating calculating, it is final to reconstruct the alias that is eliminated
Image data, as shown in Figure 10.
The present invention is directed to the elimination problem that image alias is realized based on FPGA, farthest inhibits the " block of image
The detailed information such as shape effect " and the Edge texture for keeping image, based on the model that small echo and Canny algorithm combine, with small echo
It is theoretical to be used as time frequency analysis means, the processing such as non-maximum and hysteresis threshold segmentation is carried out using Canny algorithm, then will be after processing
Image Sub-Band carry out wavelet reconstruction recovery the detailed information such as image border texture can be protected while removing picture noise,
And parameter can be met specific requirements by concurrency and programmability based on FPGA, to be expanded accordingly to system,
Effectively inhibit alias, there is good denoising effect, final effect is ideal.
The above examples only illustrate the technical idea of the present invention, and this does not limit the scope of protection of the present invention, all
According to the technical idea provided by the invention, any changes made on the basis of the technical scheme each falls within the scope of the present invention
Within.
Claims (7)
1. a kind of image alias removing method based on FPGA, it is characterised in that include the following steps：
Step A, the RGB image that will enter into FPGA carry out gradation conversion, obtain the grey scale signal that value is 0-255；
Conversion gained gray level image is carried out the image preprocessing of mean filter, reduces the sharp change of the gray value of image by step B
It changes；
Gray level image is carried out wavelet decomposition by step C, is decomposed into the low frequency component I comprising original image essential informationLLAnd packet
The high fdrequency component I of the details containing original imageHH, and to ILLIt decomposes again and obtains its low frequency component ILL；
Step D, using Canny operator to ILH1Processing, and image reconstruction is carried out, it is final to obtain the image letter for eliminating alias
Breath.
2. a kind of image alias removing method based on FPGA as described in claim 1, it is characterised in that：The step
In A and step B, the input of RGB image signal, row clock synchronization signal of going forward side by side are carried out to FPGA from outside；To RGB color space figure
As by conversion program, gray level image after conversion is attached by clock sync signal and Image Mean Filtering program.
3. a kind of image alias removing method based on FPGA as described in claim 1, it is characterised in that：The step
The detailed process of B is：
Step B1, input data is cached, and two-dimensional transform processor reads data from FIFO caching, and selected size is
5 × 5 mask, and slide mask and carry out image traversal to realize filtering；
Step B2 regards 5 × 5 masks as a two-dimensional array, the continuous row based on row data, carries out 5 row data first
Input data is continuously played 4 bats by sum operation, in addition current data forms 5 beat of data, is transported by the addition two-by-two of 3 clocks
It calculates, obtains the sum of continuous 5 data；
Step B3, when carrying out 5 row data and progress column direction summation operation, when first row data is with acquiring, into
Line data caching, takes capable caching for the summed result of one-dimensional line direction, until subsequent 4 data arrive, 5 row data
Summed result carries out column direction summation, and structure is identical as row summation structure；
Operation divided by 25 is converted to 9 shifting functions and 7 sub-additions operates by step B4, and being finally completed mask is 5 × 5
Image Mean Filtering.
4. a kind of image alias removing method based on FPGA as described in claim 1, it is characterised in that：The step
The detailed process of C is：
Step C1, image resolve into low frequency component I after the transformation of primary rowLLWith high fdrequency component IHH；
Step C2, by low frequency component ILLIt converts again and once obtains 2 low frequency component ILL1, ILH1, by high fdrequency component IHHOne is converted again
It is secondary to obtain 2 high fdrequency component IHL1, IHH1；
Step C3, then to low frequency component ILL1Step C1 is repeated, wavelet decomposition rank transformation needed for completing.
5. a kind of image alias removing method based on FPGA as described in claim 1, it is characterised in that：The step
In D, using Canny operator to ILH1The detailed process of processing is：
Step D11, smoothing processing use mask for 5 × 5 and standard deviation be 1.4 Gaussian kernel carry out gaussian filtering, obtain smooth
Component information；
Step D12 opens a window to smooth rear image using Sobel operator, by 3 × 3 masks in image level direction and Vertical Square
To being filtered, modulus value and the direction of gradient are calculated；
Step D13, aforementioned Sobel operator calculate gradient modulus value and direction 3 × 3 mask on the basis of, find out pixel
Point local maximum, so that gray value corresponding to non-maximum point is set to 0；
Step D14 eliminates alias by hysteresis threshold segmentation using dual-threshold voltage.
6. a kind of image alias removing method based on FPGA as claimed in claim 5, it is characterised in that：The step
In D13, the method for finding out pixel local maximum is：By 8 pixels centered on intermediate pixel, 8 quadrants are separated into, and
Cross central pixel point and do the intersection point of oblique line and 8 gradient directions and carry out interpolation respectively, thus by compared with interpolation judge center
Whether the maximum value of pixel.
7. a kind of image alias removing method based on FPGA as described in claim 1, it is characterised in that：The step
In D, the detailed process for carrying out image reconstruction is：
Step D21, by Canny operator treated low frequency component ILH10It is brought into reconstructed module；
Step D22 configures two divided-frequency clock CLK1 in reconstructed module, is responsible for coordinated control data flow and is predicting and updating
Interleaved computation and output are carried out in module；
Step D23, when current pixel is carrying out prediction calculating, next pixel data is directly inputted to update module calculating, then
Input prediction module calculates next pixel data again；
Step D24, pixel data input update module after prediction calculates calculate output, are directly entered the data for updating and calculating
It could be exported after participating in prediction.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111369615A (en) * | 2020-02-21 | 2020-07-03 | 苏州优纳医疗器械有限公司 | Cell nucleus central point detection method based on multitask convolutional neural network |
| CN111489313A (en) * | 2020-04-13 | 2020-08-04 | 湖南国科微电子股份有限公司 | CFA image demosaicing method and device |
| CN111504971A (en) * | 2020-05-11 | 2020-08-07 | 吉林大学 | 2, 4-dichlorphenoxyacetic acid on-site quantitative detection platform based on integration of target response type 3D printing model and smart phone |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102044071A (en) * | 2010-12-28 | 2011-05-04 | 上海大学 | Single-pixel margin detection method based on FPGA |
| CN102208104A (en) * | 2011-05-24 | 2011-10-05 | 中国科学院上海技术物理研究所 | CDB97 wavelet transformation real-time image fusion method based on field programmable gate array (FPGA) hardware |
| CN103179398A (en) * | 2013-03-04 | 2013-06-26 | 中国科学院长春光学精密机械与物理研究所 | FPGA (field programmable gate array) implement method for lifting wavelet transform |
| CN104616254A (en) * | 2015-01-09 | 2015-05-13 | 南京信息工程大学 | Wavelet and Canny algorithm combined image denoising method |
| CN106447597A (en) * | 2016-11-02 | 2017-02-22 | 上海航天控制技术研究所 | High-resolution image accelerated processing method based on parallel pipeline mechanism |
-
2018
- 2018-06-04 CN CN201810562838.8A patent/CN108876736A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102044071A (en) * | 2010-12-28 | 2011-05-04 | 上海大学 | Single-pixel margin detection method based on FPGA |
| CN102208104A (en) * | 2011-05-24 | 2011-10-05 | 中国科学院上海技术物理研究所 | CDB97 wavelet transformation real-time image fusion method based on field programmable gate array (FPGA) hardware |
| CN103179398A (en) * | 2013-03-04 | 2013-06-26 | 中国科学院长春光学精密机械与物理研究所 | FPGA (field programmable gate array) implement method for lifting wavelet transform |
| CN104616254A (en) * | 2015-01-09 | 2015-05-13 | 南京信息工程大学 | Wavelet and Canny algorithm combined image denoising method |
| CN106447597A (en) * | 2016-11-02 | 2017-02-22 | 上海航天控制技术研究所 | High-resolution image accelerated processing method based on parallel pipeline mechanism |
Non-Patent Citations (2)
| Title |
|---|
| 牟新刚 等: "《基于FPGA的数字图像处理原理及应用》", 31 January 2017 * |
| 陈拓: "小波图像去噪算法在FPGA中的实现", 《中国优秀硕士学位论文全文数据库》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111369615A (en) * | 2020-02-21 | 2020-07-03 | 苏州优纳医疗器械有限公司 | Cell nucleus central point detection method based on multitask convolutional neural network |
| CN111489313A (en) * | 2020-04-13 | 2020-08-04 | 湖南国科微电子股份有限公司 | CFA image demosaicing method and device |
| CN111489313B (en) * | 2020-04-13 | 2023-10-31 | 湖南国科微电子股份有限公司 | CFA image demosaicing method and device |
| CN111504971A (en) * | 2020-05-11 | 2020-08-07 | 吉林大学 | 2, 4-dichlorphenoxyacetic acid on-site quantitative detection platform based on integration of target response type 3D printing model and smart phone |
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