CN108875318A - A kind of FPGA property right protection and remote update system and its method based on MCU - Google Patents
A kind of FPGA property right protection and remote update system and its method based on MCU Download PDFInfo
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- CN108875318A CN108875318A CN201810519561.0A CN201810519561A CN108875318A CN 108875318 A CN108875318 A CN 108875318A CN 201810519561 A CN201810519561 A CN 201810519561A CN 108875318 A CN108875318 A CN 108875318A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/10—Protecting distributed programs or content, e.g. vending or licensing of copyrighted material ; Digital rights management [DRM]
- G06F21/12—Protecting executable software
- G06F21/121—Restricting unauthorised execution of programs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
- G06F8/654—Updates using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
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Abstract
The FPGA property right protection and remote update system and its method that the present invention relates to a kind of based on MCU, belong to the field FPGA.The invention mainly comprises the most of compositions of FPGA, PC, MCU, EPCS tetra-；PC software calculates key and address by the MD5 algorithm parameter arranged according to the UID of MCU, and in itself FLASH of key programming to MCU, equally, MCU can also generate a group key and be stored in EPCS, leave FPGA use for, the key of every set system is all, the uniqueness of guarantee every suit system calculated according to the UID of MCU；After starting, MCU reads itself UID and calculates key storage address according to the MD5 algorithm parameter of agreement, complete itself verification, FPGA does master control by MCU and completes itself verification, and further verification is completed by UART, once examining failure, MCU wipes EPCS in end first, then itself FLASH is wiped, the end FPGA can also wipe EPCS.
Description
Technical field
The FPGA property right protection and remote update system and its method that the present invention relates to a kind of based on MCU belong to FPGA neck
Domain.
Background technique
FPGA (Field-Programmable Gate Array), i.e. field programmable gate array, it be PAL,
The product further developed on the basis of the programming devices such as GAL, CPLD.It is as in the field specific integrated circuit (ASIC)
A kind of semi-custom circuit and occur, not only solved the deficiency of custom circuit, but also overcome original programming device part door electricity
Number is limited to be lacked, and has trigger and I/O pin abundant inside FPGA；FPGA is that the design cycle is most short in ASIC circuit, opens
Send out one of network minimal, device of least risk；FPGA uses high-speed cmos technique, low in energy consumption, can be with CMOS, Transistor-Transistor Logic level
It is compatible.It can be said that fpga chip is that small lot system improves one of level of integrated system, the optimal selection of reliability.
Currently, there are three types of basic FPGA programming techniques in the market：SRAM, antifuse, FLASH.Wherein SRAM is so far
Until the most wide framework of application range, it is fast and have reprogrammability to be primarily due to its speed, and
The FPGA of antifuse only has disposable programmable ability.Although FLASH type FPGA does not need configuration chip, anti-interference
The advantages that ability is strong, good confidentiality, but price is more expensive.
It needs to read in configuration data in external chip in SRAM when powering on based on FPGA, it just can be into after the completion of configuration
Enter working condition, with current science and technology, as long as the duplication of product is completed in the data flowing of detection FPGA load pin, or
The data of exterior arrangement chip can be read directly in person.Since pirate phenomenon makes designer by huge loss every year, in addition to
Outside economic loss, apply and be once cracked in the FPGA design of the special occasions such as military project, space flight, caused by consequence can not estimate,
So more and more important to the protection of the intellectual property of FPGA.
The property right protection scheme of FPGA is roughly divided into direct enciphered method and authentication method at present, wherein direct enciphered method is exactly handle
Configuration file all encrypts, and when power on configuration decrypts.It is only applicable to specific model, and its price is more expensive；Authentication method
Suitable for, than more sensitive user, being widely used to price.By taking a kind of authentication method for the encryption chip released based on company as an example,
Its protocol procedures is to generate random number after property right protection program starts, and the random number is sent to encryption chip by an agreement
Module encryption chip module is obtained according to data such as the good keys of random number, offered by Encryption Algorithm such as an algorithms
Unique authentification of message code value, and equally returned to via an agreement.The value that property right protection program obtains encryption chip module
It is matched with local by the value that identical data identical algorithms obtain, if the two is consistent, decision procedure operates in authorization environment
Under, it authenticates successfully, into normal operating conditions, conversely, authentification failure, into abnormal operating state.
STM32F series belongs to 32 ARM microcontrollers of low and middle-end, which is STMicw Electronics (ST) company
It produces, kernel is Cortex-M3.And each STM32 chip has a globally unique ID when leaving the factory, inside
FLASH can be used to store key, ST has carried encryption setting, and furthermore STM32 is at low cost, is suitable for FPGA encryption and remote
Cheng Gengxin.
Summary of the invention
The purpose of the present invention is realizing a kind of FPGA property right protection and method for remote updating based on MCU, prevent FPGA from setting
Meter achievement is replicated.Long-range more new function provided by the invention simultaneously is to needing in the personnel of outfield change parameter with greatly just
Benefit.
The object of the present invention is achieved like this：
A kind of FPGA property right protection and remote update system based on MCU, including：Fpga chip, nonvolatile memory
The end part EPCS, MCU, PC host computer, which is characterized in that by MCU can be carried out by secret key pair FPGA internal data encryption and
Long-range programming is carried out to EPCS internal data；Encrypting module is connected by pc port with MCU；After system electrification, PC control terminal is logical
Control MCU is crossed to calculate secret key, and encrypts program by secret key into the FLASH and EPCS of MCU its programming；
Activation system after secret key is burned, MCU module completes itself verification, and controls FPGA module and complete its own verification, is guaranteeing
In the case where the uniqueness of secret key, start to work normally；After work, MCU is sent to data by UART data
EPCS completes programming.The secret key of system is all to carry out MD5 algorithm by the UID of MCU to get, and the secret key of system has uniqueness.
Itself verification of FPGA is controlled by MCU, is connected by UART.The data remotely updated are unpacked by MCU, and programming is into EPCS.
A kind of FPGA property right protection and method for remote updating based on MCU, which is characterized in that include the following steps：
Step 1 is by MCU, after FPGA and PC machine configure, PC machine based on the UID of MCU, by MD5 rotation plus
Close method calculates one group of secret key 1；
Step 2 will be in the burned EPCS of FPGA firmware；
Step 3 is downloaded to configured secret key 1 in the FLASH of MCU by host computer；
Step 4 reads UID, and 1 address of computation key after MCU initialization, reads key 1 and compared with about definite value；
If verification failure, MCU remove all firmwares of itself and FPGA；MCU reads itself FLASH and completes CRC check, checks
Whether internal processes are tampered；If verification failure, MCU remove all firmwares of itself and FPGA；
Step 5 MCU changes MD5 algorithm number of turns and obtains key 2 and its address, and MCU is by control pin by FPGA
In reset state, key 2 is stored in EPCS later, key 2 is left FPGA verification for and used；
Step 6 MCU reads EPCS, completes the CRC check of FPGA, starts FPGA by control pin, FPGA is counted first
Key 2 and its address are calculated, key 2 is read and is verified, clashes key after the completion of verification, if MCU discovery FPGA starting failure,
MCU removes all firmwares of itself and FPGA；If the verification failure of key 2, FPGA wipe EPCS；
After step 7 FPGA and MCU normally start, the two is received and dispatched by UART and is ordered, and last verification is completed, if school
Failure is tested, then MCU removes all firmwares of itself and FPGA；
Step 8 enters normal operating conditions by rear FPGA and MCU.
Compared with prior art, beneficial effects of the present invention：
The present invention provides a kind of FPGA property right protection methods, and the long-range programming method of subsidiary FPGA a kind of.This hair
The bright protection completed by upper computer software and MCU to FPGA property right, prevents result of design to be replicated；Compared to traditional FPGA
Property right protection, the present invention take full advantage of the advantage of STM32 confidentiality, in the case where protecting FPGA property right, reduce whole
The cost of set system.Long-range more new function provided by the invention simultaneously is to needing in the personnel of outfield change parameter with greatly just
Benefit.The end PC software of the invention, MCU, FPGA Trinity, it is indispensable.
Detailed description of the invention
Fig. 1 is hardware design of the invention；
Fig. 2 is workflow of the invention.
Specific embodiment
With reference to the accompanying drawing and example is moved, more detailed elaboration is made to the present invention.
A kind of FPGA property right protection and method for remote updating based on MCU, this system mainly include FPGA, PC, MCU,
The most of composition of EPCS tetra-；Host computer is connect by UART and JTAG with MCU, and MCU is connect with FPGA by UART, the control of FPGA
Pin processed is connected on MCU, is resetted and is started by MCU control FPGA, furthermore MCU is connected on EPCS together with the SPI interface of FPGA.
This connection type can clash by MCU or update the configuration file inside EPCS, and the system later period is facilitated to upgrade.
In itself FLASH, the configuration file of FPGA is stored in EPCS the program storage of MCU, the key of every set system
It is all, the uniqueness of guarantee every suit system calculated according to the UID of MCU.The end PC software is responsible for that MCU key 1, MCU is arranged
Complete itself verification (key 1 and CRC), and be supplied to EPCS key 2, FPGA completes itself verification according to key 2, MCU with
Last verification is completed in FPGA communication, once certain intermediate a part error, whole system can all work in abnormal condition.
The present invention is directed to propose a kind of SRAM type FPGA property right protection and method for remote updating based on MCU, right
FPGA property right, which provides, to be effectively protected, and the long-range programming method of subsidiary FPGA a kind of.Below with reference to case study on implementation, to this
The method of invention is described in further detail.
A kind of FPGA property right protection and method for remote updating, device based on MCU include：Fpga chip non-volatile is deposited
Memory device EPCS, MCU (STM32), the end PC host computer, characterized in that can by MCU can by secret key pair FPGA internal data into
Row encrypts and carries out long-range programming to EPCS internal data；
Encrypting module is connected by pc port with MCU；
After system electrification, PC control terminal calculates secret key by control MCU, and by its programming into the FLASH of MCU and
In EPCS, encrypt program by secret key；
Activation system after secret key is burned, MCU module completes itself verification, and controls FPGA module and complete its own school
It tests, in the case where guaranteeing the uniqueness of secret key, starts to work normally；
After work, there is MCU to be sent to EPCS data by UART data, complete programming.
The secret key of system is all to have the UID of MCU to carry out MD5 algorithm to get, and the secret key of system has uniqueness.FPGA's
Itself verification is controlled by MCU, is connected by UART.If verification failure, the data of EPCS, MCU, FPGA can be wiped successively, protect
Hinder the safety of encryption.Notice that the TX of UART (RS-232Serial port), RX pin will connect with ARM when distributing pin
The USART pin matching connect.The data remotely updated are unpacked by MCU, and programming is into EPCS.
Host computer is connect by UART and JTAG with MCU, and MCU is connect with FPGA by UART, and the control pin of FPGA connects
Onto MCU, is resetted and started by MCU control FPGA, furthermore MCU is connected on EPCS together with the SPI interface of FPGA.
In itself FLASH, the configuration file of FPGA is stored in EPCS the program storage of MCU, and each group key is all
Based on the UID of MCU, it is calculated by MD5 algorithm.First by FPGA firmware programming into EPCS；
Further, MCU deposit key 1 in the 16 system configuration files of MCU and is downloaded to by the software of host computer
In, key and its address all have passed through MD5 algorithm for encryption.
Further, UID, and 1 address of computation key are read after MCU initialization, reads key 1 and compared with about definite value.
If verification failure, MCU can remove all firmwares of itself and FPGA.
Further, MCU reads itself FLASH and completes CRC check, checks whether internal processes are tampered.If school
Failure is tested, MCU can remove all firmwares of itself and FPGA.
Further, MCU change MD5 algorithm number of turns obtain key 2 and its address, and MCU is allowed by controlling pin
FPGA is in reset state (all pins are in high-impedance state), key 2 is stored in EPCS later, key 2, which leaves FPGA verification for, to be made
With.
Further, MCU reads EPCS, completes the CRC check of FPGA, starts FPGA by control pin, FPGA is first
Computation key 2 and its address are read key 2 and are verified, clash key after the completion of verification, if MCU discovery FPGA starting failure,
MCU can remove all firmwares of itself and FPGA.If the verification failure of key 2, FPGA can wipe EPCS.
After FPGA and MCU normally starts, the two is received and dispatched by UART and is ordered, and is completed last verification, is passed through rear FPGA
Enter normal operating conditions with MCU.
This set system proposed by the present invention is attached to the method for remote updating of FPGA a kind of, and specific embodiment is as follows：
The same with property right protection, long-range update also needs upper computer software, MCU, EPCS.Firstly the need of the rbf of FPGA
Every 256 bytes of rbf file are made a call to a packet, insufficient benefit 0xFF, 256 bytes by file (binary profile file), host computer
Just correspond to the size of mono- page of EPCS.Each bag data includes packet header, Bale No., mirror image data, packet tail.MCU receives a packet number
According to rear, the corresponding position EPCS is write the data to, in remote update system, MCU decides, after MCU programming one bag data of success, to
Host computer sends Bale No. and requests next bag data, it is known that programming is completed, and host computer is equipped with progress bar and shows current programming progress.
The purpose of the present invention is to propose to a kind of SRAM type FPGA property right protection and remote update system based on MCU, this is
System mainly includes the end FPGA, PC software, the most of composition of MCU, EPCS tetra-；The end PC software is responsible for that MCU key 1 is arranged, and MCU is completed
Itself verification (key 1 and CRC), and it is supplied to EPCS key 2, FPGA completes itself verification according to key 2, and MCU and FPGA are logical
Letter completes last verification, once certain intermediate a part error, whole system can all work in abnormal condition.The end PC software,
MCU, FPGA Trinity, it is indispensable, effectively protect the only property right of FPGA, it is long-range update also great convenience certain
The exploitation of FPGA under a little particular surroundings.
Flow chart includes the following steps
1, firstly, by MCU, after FPGA and PC machine configure, PC machine based on the UID of MCU, by MD5 rotation plus
Close method calculates one group of secret key 1.
It 2, then, will be in the burned EPCS of FPGA firmware.
3, configured secret key 1 is downloaded in the FLASH of MCU by host computer.
4, UID, and 1 address of computation key are read after MCU initialization, reads key 1 and compared with about definite value.If school
Failure is tested, MCU can remove all firmwares of itself and FPGA.
MCU also can read itself FLASH and complete CRC check, check whether internal processes are tampered.If verification is lost
It loses, MCU can remove all firmwares of itself and FPGA.
5, MCU change MD5 algorithm number of turns obtain key 2 and its address, and MCU is in multiple by FPGA by control pin
Key 2, is stored in EPCS later by position state (all pins are in high-impedance state), and key 2 is left FPGA verification for and used.
6, MCU reads EPCS, completes the CRC check of FPGA, starts FPGA, FPGA computation key first by control pin
2 and its address, it reads key 2 and simultaneously verifies, clash key after the completion of verification, if MCU discovery FPGA starting failure, MCU can be clear
Except all firmwares of itself and FPGA.If the verification failure of key 2, FPGA can wipe EPCS.
7, after FPGA and MCU normally starts, the two is received and dispatched by UART and is ordered, and completes last verification, if verification
Failure, MCU can remove all firmwares of itself and FPGA.
8, normal operating conditions is entered by rear FPGA and MCU.
Claims (5)
1. a kind of FPGA property right protection and remote update system based on MCU, including：Fpga chip, nonvolatile semiconductor memory member
The end EPCS, MCU, PC host computer, which is characterized in that by MCU can be carried out by secret key pair FPGA internal data encryption and it is right
EPCS internal data carries out long-range programming；Encrypting module is connected by pc port with MCU；After system electrification, PC control terminal passes through
Control MCU calculates secret key, and encrypts program by secret key into the FLASH and EPCS of MCU its programming；It is close
Activation system after spoon is burned, MCU module completes itself verification, and controls FPGA module and complete its own verification, close in guarantee
In the case where the uniqueness of spoon, start to work normally；After work, MCU is sent to data by UART data
EPCS completes programming.
2. a kind of FPGA property right protection and remote update system based on MCU according to claim 1, which is characterized in that
The secret key of system is all to carry out MD5 algorithm by the UID of MCU to get, and the secret key of system has uniqueness.
3. a kind of FPGA property right protection and remote update system based on MCU according to claim 1, which is characterized in that
Itself verification of FPGA is controlled by MCU, is connected by UART.
4. a kind of FPGA property right protection and remote update system based on MCU according to claim 1, which is characterized in that
The data remotely updated are unpacked by MCU, and programming is into EPCS.
5. a kind of FPGA property right protection and method for remote updating based on MCU, which is characterized in that include the following steps：
Step 1 is by MCU, and after FPGA and PC machine configure, PC machine rotates enciphered method based on the UID of MCU, through MD5
Calculate one group of secret key 1；
Step 2 will be in the burned EPCS of FPGA firmware；
Step 3 is downloaded to configured secret key 1 in the FLASH of MCU by host computer；
Step 4 reads UID, and 1 address of computation key after MCU initialization, reads key 1 and compared with about definite value；If verification
Failure, then MCU removes all firmwares of itself and FPGA；MCU reads itself FLASH and completes CRC check, checks internal journey
Whether sequence is tampered；If verification failure, MCU remove all firmwares of itself and FPGA；
Step 5 MCU changes MD5 algorithm number of turns and obtains key 2 and its address, and MCU is in multiple by FPGA by control pin
Key 2, is stored in EPCS later by position state, and key 2 is left FPGA verification for and used；
Step 6 MCU reads EPCS, completes the CRC check of FPGA, starts FPGA, FPGA computation key first by control pin
2 and its address, it reads key 2 and simultaneously verifies, clash key after the completion of verification, if MCU discovery FPGA starting failure, MCU are removed
All firmwares of itself and FPGA；If the verification failure of key 2, FPGA wipe EPCS；
After step 7 FPGA and MCU normally start, the two is received and dispatched by UART and is ordered, and completes last verification, if verification is lost
It loses, then MCU removes all firmwares of itself and FPGA；
Step 8 enters normal operating conditions by rear FPGA and MCU.
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| CN109408099A (en) * | 2018-09-13 | 2019-03-01 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | Remote FPGA firmware code updating system, method and medium |
| CN111259370A (en) * | 2020-01-13 | 2020-06-09 | 苏州浪潮智能科技有限公司 | FPGA program security verification method, system, terminal and storage medium |
| CN111339544A (en) * | 2019-04-24 | 2020-06-26 | 上海安路信息科技有限公司 | Offline downloading device and offline downloading method |
| CN112114830A (en) * | 2020-09-16 | 2020-12-22 | 天津光电通信技术有限公司 | Method for protecting FPGA (field programmable Gate array) programming file |
| CN112532391A (en) * | 2020-11-05 | 2021-03-19 | 成都芯通软件有限公司 | FPGA-ID-based digital product software and hardware collaborative encryption method |
| CN112732304A (en) * | 2021-02-03 | 2021-04-30 | 浙江日风电气股份有限公司 | CPLD firmware updating method |
| CN112860275A (en) * | 2021-01-26 | 2021-05-28 | 北京自动化控制设备研究所 | Software and hardware cooperative encryption circuit and method for embedded computer |
| CN113239370A (en) * | 2021-04-29 | 2021-08-10 | 江苏无线电厂有限公司 | Embedded software encryption design method based on SOC hardware identification code |
| CN114237676A (en) * | 2021-12-28 | 2022-03-25 | 湖南云箭智能科技有限公司 | FPGA (field programmable Gate array) logic updating method, device, equipment and readable storage medium |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109408099A (en) * | 2018-09-13 | 2019-03-01 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | Remote FPGA firmware code updating system, method and medium |
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| CN112532391A (en) * | 2020-11-05 | 2021-03-19 | 成都芯通软件有限公司 | FPGA-ID-based digital product software and hardware collaborative encryption method |
| CN112860275A (en) * | 2021-01-26 | 2021-05-28 | 北京自动化控制设备研究所 | Software and hardware cooperative encryption circuit and method for embedded computer |
| CN112732304A (en) * | 2021-02-03 | 2021-04-30 | 浙江日风电气股份有限公司 | CPLD firmware updating method |
| CN113239370A (en) * | 2021-04-29 | 2021-08-10 | 江苏无线电厂有限公司 | Embedded software encryption design method based on SOC hardware identification code |
| CN114237676A (en) * | 2021-12-28 | 2022-03-25 | 湖南云箭智能科技有限公司 | FPGA (field programmable Gate array) logic updating method, device, equipment and readable storage medium |
| CN114237676B (en) * | 2021-12-28 | 2023-12-08 | 湖南云箭智能科技有限公司 | FPGA logic updating method, device, equipment and readable storage medium |
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Application publication date: 20181123 |