CN108874232B - Array substrate and display panel - Google Patents

Array substrate and display panel Download PDF

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Publication number
CN108874232B
CN108874232B CN201810837353.5A CN201810837353A CN108874232B CN 108874232 B CN108874232 B CN 108874232B CN 201810837353 A CN201810837353 A CN 201810837353A CN 108874232 B CN108874232 B CN 108874232B
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data line
pixel
sub
segment
routing
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CN108874232A (en
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李宁
贾鹏
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Human Computer Interaction (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The embodiment of the invention provides an array substrate and a display panel, relates to the technical field of touch control, and can enable parasitic capacitances at two sides of a pixel electrode in a sub-pixel through which a touch electrode wire passes to be mutually offset when a data line adopts a column inversion driving mode. Each touch electrode routing in the array substrate comprises a plurality of first routing segments and a plurality of second routing segments, the first routing segments and the second routing segments are arranged at intervals, and any adjacent first routing segments and any adjacent second routing segments are connected through a third routing segment; each touch electrode wire penetrates through a plurality of continuous sub-pixels positioned in the same column in the process of extending from the display area to the non-display area on one side of the display area; for any sub-pixel through which the touch electrode is routed, a first routing segment is located between a first data line connected with the sub-pixel and a pixel electrode in the sub-pixel, and a second routing segment is located between a second data line adjacent to the first data line and the pixel electrode in the sub-pixel.

Description

Array substrate and display panel
Technical Field
The invention relates to the technical field of touch control, in particular to an array substrate and a display panel.
Background
With the rapid development of display technology, the birth of Touch Panel (TP for short) makes people's life more convenient. Nowadays, the embedded capacitive touch technology has been widely applied to the display field.
Disclosure of Invention
Embodiments of the present invention provide an array substrate and a display panel, in which when a data line adopts a column inversion driving manner, parasitic capacitances at two sides of a pixel electrode in a sub-pixel through which a touch electrode trace passes are mutually offset, so as to improve an abnormal picture phenomenon.
In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
on one hand, the array substrate comprises a plurality of touch electrode routing wires arranged on a substrate; each touch electrode wire comprises a plurality of first wire sections and a plurality of second wire sections, the first wire sections and the second wire sections are arranged at intervals, and any adjacent first wire sections and second wire sections are connected through a third wire section; each touch electrode wire penetrates through a plurality of continuous sub-pixels positioned in the same column in the process of extending from the display area to the non-display area on one side of the display area; for any sub-pixel through which the touch electrode is routed, the first routing segment is located between a first data line connected with the sub-pixel and a pixel electrode in the sub-pixel, and the second routing segment is located between a second data line adjacent to the first data line and the pixel electrode in the sub-pixel.
In some embodiments, for any sub-pixel through which the touch electrode is routed, the pixel electrode in the sub-pixel includes at least one first portion and at least one second portion distributed along the first data line direction, and the first portion and the second portion are alternately arranged; in the sub-pixel, the first routing segment is located between the first data line and the first portion, and the second routing segment is located between the second data line and the second portion; the first portion and the second portion are staggered by a certain distance in a gate line direction.
In some embodiments, for any sub-pixel through which the touch electrode is routed, the pixel electrode in that sub-pixel includes one of the first portions and one of the second portions.
In some embodiments, the first routing segment is flush with an edge of the second portion near the first data line, and the second routing segment is flush with an edge of the first portion near the second data line.
In some embodiments, a length of an edge of the first portion near the second data line is equal to a length of an edge of the second portion near the first data line; a spacing between the first portion and the second data line is equal to a spacing between the second portion and the first data line.
In some embodiments, the first routing segment is flush with an edge of the second portion near the first data line, and the second routing segment is flush with an edge of the first portion near the second data line. On the basis, the distance between the first line segment and the first data line is equal to the distance between the second line segment and the second data line; the distance between the first line segment and the first part is equal to the distance between the second line segment and the second part.
On this basis, in some embodiments, the length of the edge of the first portion near the first running line segment is equal to the length of the edge of the second portion near the second running line segment.
In some embodiments, the first and second routing segments and all data lines including the first and second data lines are arranged in parallel; the third wire segment is arranged in parallel with the grid line.
In some embodiments, the touch electrode trace and all data lines including the first data line and the second data line are disposed in the same layer.
In another aspect, a display panel is provided, which includes the array substrate.
Embodiments of the present invention provide an array substrate and a display panel, in each sub-pixel through which each touch electrode trace passes, a first trace segment of the touch electrode trace is located between a first data line connected to the sub-pixel and a pixel electrode in the sub-pixel, and a second trace segment is located between a second data line adjacent to the first data line and a pixel electrode in the sub-pixel (i.e., the first trace segment and the second trace segment are respectively located at left and right sides of the pixel electrode in the sub-pixel), so that a partial segment of the second data line can be directly adjacent to the pixel electrode, and thus parasitic capacitances at both sides of the pixel electrode along a gate line direction can be cancelled when all data lines including the first data line and the second data line are driven in a column inversion manner by reasonably setting a length of a segment of the second data line directly adjacent to the pixel electrode and a distance between the segment and the pixel electrode, thereby improving the abnormal picture phenomenon.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of a connection between a touch electrode and a touch electrode trace provided in the related art;
fig. 2 is a schematic view illustrating a touch electrode trace extending in a display area according to the related art;
fig. 3 is a schematic view of an array substrate according to some embodiments of the present invention;
fig. 4 is a schematic view of another array substrate according to some embodiments of the present invention.
Reference numerals:
1-a display area; 2-a non-display area; 10-touch electrodes; 11-touch electrode routing; 12-sub-pixel; 15-first sub-pixel; 16-a first pixel electrode; 20-a data line; 21-a first data line; 22-a second data line; 30-a gate line; 40-pixel electrodes; 111-first route segment; 112-a second route segment; 113-third route segment; 401-a first part; 402-second part.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
For the embedded self-contained Touch technology, as shown in fig. 1, a plurality of Touch electrodes 10 are usually arranged in an array, and each Touch electrode 10 is connected to a Touch Driver IC (TIC) located in a non-display area 2 on one side of a display area 1 through a Touch electrode trace 11. In the display area 1, the touch electrode trace 11 electrically connected to each touch electrode 10 extends from a starting point in the display area 1 along a certain direction (e.g., vertical direction) until extending to an edge of the display area 1 near the non-display area 2 where TIC is disposed and extending to the non-display area 2. It should be noted that, for any one touch electrode trace 11, the starting point is: the touch electrode trace 11 is electrically connected to the corresponding touch electrode 10.
As shown in fig. 2, in the process of extending from the starting point to the edge of the display area 1, any one of the touch electrode traces 11 passes through at least some of the continuous sub-pixels (the sub-pixel is shown as a first sub-pixel 15 in fig. 2) of a column of sub-pixels. Based on the arrangement of the touch electrode trace 11, the distance between the data line 20 adjacent to and not electrically connected to the first pixel electrode 16 in the first sub-pixel 15 and the first pixel electrode 16 in the first sub-pixel 15 is widened, so that when the data line 20 is driven in a column inversion manner, i.e., voltages of the adjacent data lines 20 in one frame are "+" and "-", respectively, parasitic capacitances at two sides of the first pixel electrode 16 in the first sub-pixel 15 along the gate line 30 cannot cancel each other. Therefore, during the line-by-line scanning of the gate line 30, the voltage of the first pixel electrode 16 in the first sub-pixel 15 is higher or lower than the voltage of the data line 20, which causes abnormal image display.
Based on this, some embodiments of the present invention provide an array substrate, including a plurality of touch electrode traces 11 disposed on a substrate; as shown in fig. 3, each touch electrode trace 11 includes a plurality of first trace segments 111 and a plurality of second trace segments 112, the first trace segments 111 and the second trace segments 112 are arranged at intervals, and any adjacent first trace segments 111 and second trace segments 112 are connected by a third trace segment 113. That is, each touch electrode trace 11 is shaped like a snake.
In some embodiments, the plurality of touch electrode traces 11 are disposed in parallel.
It can be understood that the first trace segment 111 and the second trace segment 112 are disposed at intervals, that is, for any one touch electrode trace 11, starting from a starting point of electrical connection with a corresponding touch electrode, during an extending process of the trace to the non-display area 2, the first trace segment 111 and the second trace segment 112 are sequentially and alternately disposed.
Each touch electrode wire 11 passes through a plurality of continuous sub-pixels 12 in the same column in the process of extending from the display area 1 to the non-display area 2 on one side of the display area 1; for any sub-pixel 12 through which the touch electrode trace 11 passes, the first trace segment 111 is located between the first data line 21 connected to the sub-pixel 12 and the pixel electrode 40 in the sub-pixel 12, and the second trace segment 112 is located between the second data line 22 adjacent to the first data line 21 and the pixel electrode 40 in the sub-pixel 12.
It should be noted that, for describing "the first data line 21 connected to the sub-pixel 12", those skilled in the art understand that the first data line 21 is actually connected to a TFT (Thin Film Transistor) in the sub-pixel 12.
In addition, as can be seen from the above description of the first routing segment 111 and the second routing segment 112, for any sub-pixel 12 through which the touch electrode trace 11 passes, the first routing segment 111 and the second routing segment 112 are respectively located at the left and right sides of the pixel electrode 40 in the sub-pixel 12.
In each sub-pixel 12 through which each touch electrode trace 11 passes, by positioning the first wire segment 111 of the touch electrode trace 11 between the first data line 21 connected to the sub-pixel 12 and the pixel electrode 40 in the sub-pixel 12, and positioning the second wire segment 112 between the second data line 22 adjacent to the first data line 21 and the pixel electrode 40 in the sub-pixel 12 (i.e., by positioning the first wire segment 111 and the second wire segment 112 on the left and right sides of the pixel electrode 40 in the sub-pixel 12, respectively), a part of the second data line 22 can be directly adjacent to the pixel electrode 40, so that when all the data lines including the first data line 21 and the second data line 22 are driven in a column inversion manner by reasonably setting the length of the wire segment in the second data line 22 directly adjacent to the pixel electrode 40 and the distance between the wire segment and the pixel electrode 40, the parasitic capacitances at the two sides of the pixel electrode 40 along the gate line 30 are offset, thereby improving the abnormal picture phenomenon.
The term "directly adjacent" means that there is no other conductive line or conductive electrode between the two directly adjacent.
In some embodiments, as shown in fig. 4, for any one of the sub-pixels 12 through which the touch electrode trace 11 passes, the pixel electrode 40 in the sub-pixel 12 includes at least one first portion 401 and at least one second portion 402 distributed along the direction of the first data line 21, and the first portion 401 and the second portion 402 are alternately arranged. In the sub-pixel 12, the first line segment 111 is located between the first data line 21 and the first portion 401, and the second line segment 112 is located between the second data line 22 and the second portion 402; the first portion 401 and the second portion 402 are staggered by a certain distance in the direction of the gate line 30.
By making the pixel electrode 40 include at least one first portion 401 and at least one second portion 402 and making the first portion 401 and the second portion 402 alternately arranged, the second data line 22 can be extended along a straight line under the condition that the parasitic capacitances at both sides of the pixel electrode 40 can be ensured to be cancelled out. Thereby being simpler in process.
On this basis, in some embodiments, the first portion 401 and the second portion 402 are staggered by a certain distance in the direction of the gate line 30, which may be: the side of the first portion 401 close to the first data line 21 is set back to the side close to the second data line 22 relative to the side of the second portion 402 close to the first data line 21. Thus, the size of the sub-pixel 12 where the pixel electrode 40 is located can be made as small as possible based on the design requirement when the process pitch is satisfied.
On the basis, in some embodiments, for any sub-pixel through which the touch electrode trace 11 passes, as shown in fig. 4, the pixel electrode 40 in the sub-pixel includes a first portion 401 and a second portion 402. This can prevent the fabrication process of the pixel electrode 40 from being excessively complicated.
In some embodiments, the first trace segment 111 is flush with the edge of the second portion 402 near the first data line 21, and the second trace segment 112 is flush with the edge of the first portion 401 near the second data line 22. In this way, the size of the sub-pixel 12 where the pixel electrode 40 is located can be made smaller on the basis of meeting the design requirements.
In some embodiments, as shown in fig. 4, the length of the side of the first portion 401 near the second data line 22 is equal to the length of the side of the second portion 402 near the first data line 21. The spacing between the first portion 401 and the second data line 22 is equal to the spacing between the second portion 402 and the first data line 21.
Accordingly, the parasitic capacitances on both sides of the pixel electrode 40 can be equalized, and thus the parasitic capacitances on both sides of the pixel electrode 40 can be cancelled out in the column inversion driving method.
On the basis that the first routing segment 111 is flush with the edge of the second part 402 close to the first data line 21, and the second routing segment 112 is flush with the edge of the first part 401 close to the second data line 22, in some embodiments, as shown in fig. 4, the distance between the first routing segment 111 and the first data line 21 is equal to the distance between the second routing segment 112 and the second data line 22; the distance between the first segment 111 and the first portion 401 is equal to the distance between the second segment 112 and the second portion 402. Even if the first data line 21 and the second data line 22 generate coupling capacitance to the pixel electrode 40 through the first routing segment 111 and the second routing segment 112, respectively, the coupling capacitance on both sides of the pixel electrode 40 can be cancelled out due to such an arrangement.
In some embodiments, the length of the edge of the first portion 401 adjacent to the first route segment 111 is equal to the length of the edge of the second portion 402 adjacent to the second route segment 112.
In some embodiments, the first and second routing segments 111 and 112, and all data lines including the first and second data lines 21 and 22 are parallel; the third wire segment 113 is parallel to the gate line 30. The process for preparing the touch electrode trace 11 is simpler.
In some embodiments, the touch electrode trace 11 and all the data lines including the first data line 21 and the second data line 22 are disposed in the same layer. This can avoid an increase in the number of patterning processes.
In some embodiments, the array substrate further includes a plurality of touch electrodes arranged in an array, and the touch electrodes are in one-to-one correspondence with and electrically connected to the touch electrode traces 11. In some embodiments, the touch electrode is common to the common electrode. In other embodiments, the touch electrode is shared with the cathode.
The embodiment of the invention also provides a display panel which comprises the array substrate.
The display panel may be a liquid crystal display panel, or may be an OLED (Organic Light Emitting Diode) display panel.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (10)

1. The array substrate is characterized by comprising a plurality of touch electrode routing lines arranged on a substrate;
each touch electrode wire comprises a plurality of first wire sections and a plurality of second wire sections, the first wire sections and the second wire sections are arranged at intervals, and any adjacent first wire sections and second wire sections are connected through a third wire section;
each touch electrode wire penetrates through a plurality of continuous sub-pixels positioned in the same column in the process of extending from the display area to the non-display area on one side of the display area; for any sub-pixel through which the touch electrode is routed, the first routing segment is located between a first data line connected with the sub-pixel and a pixel electrode in the sub-pixel, and the second routing segment is located between a second data line adjacent to the first data line and the pixel electrode in the sub-pixel.
2. The array substrate according to claim 1, wherein for any sub-pixel through which the touch electrode traces, the pixel electrode in the sub-pixel comprises at least one first portion and at least one second portion distributed along the direction of the first data line, and the first portion and the second portion are alternately arranged; in the sub-pixel, the first routing segment is located between the first data line and the first portion, and the second routing segment is located between the second data line and the second portion;
the first portion and the second portion are staggered by a certain distance in a gate line direction.
3. The array substrate of claim 2, wherein for any sub-pixel through which the touch electrode traces, the pixel electrode in the sub-pixel comprises one of the first portions and one of the second portions distributed along the first data line direction.
4. The array substrate of claim 2, wherein the first line segment is flush with an edge of the second portion adjacent to the first data line, and the second line segment is flush with an edge of the first portion adjacent to the second data line.
5. The array substrate of any one of claims 2-4, wherein a length of an edge of the first portion adjacent to the second data line is equal to a length of an edge of the second portion adjacent to the first data line;
a spacing between the first portion and the second data line is equal to a spacing between the second portion and the first data line.
6. The array substrate of claim 4, wherein a distance between the first line segment and the first data line is equal to a distance between the second line segment and the second data line;
the distance between the first line segment and the first part is equal to the distance between the second line segment and the second part.
7. The array substrate of claim 6, wherein the length of the edge of the first portion adjacent to the first line segment is equal to the length of the edge of the second portion adjacent to the second line segment.
8. The array substrate of claim 2, wherein the first and second routing segments and all data lines including the first and second data lines are disposed in parallel;
the third wire segment is arranged in parallel with the grid line.
9. The array substrate of claim 1, wherein the touch electrode traces and all data lines including the first data line and the second data line are disposed in a same layer.
10. A display panel comprising the array substrate according to any one of claims 1 to 9.
CN201810837353.5A 2018-07-26 2018-07-26 Array substrate and display panel Active CN108874232B (en)

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US9823771B2 (en) * 2014-11-12 2017-11-21 Crucialtec Co., Ltd. Display apparatus capable of image scanning and driving method thereof
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