CN108873528B - Array substrate, manufacturing method thereof and display panel - Google Patents
Array substrate, manufacturing method thereof and display panel Download PDFInfo
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- CN108873528B CN108873528B CN201810841318.0A CN201810841318A CN108873528B CN 108873528 B CN108873528 B CN 108873528B CN 201810841318 A CN201810841318 A CN 201810841318A CN 108873528 B CN108873528 B CN 108873528B
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- 239000000758 substrate Substances 0.000 title claims abstract description 132
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 claims description 25
- 238000002161 passivation Methods 0.000 claims description 21
- 239000012945 sealing adhesive Substances 0.000 claims description 17
- 238000007789 sealing Methods 0.000 claims description 10
- 239000003292 glue Substances 0.000 claims description 7
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 239000003990 capacitor Substances 0.000 description 30
- 230000003068 static effect Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 238000005096 rolling process Methods 0.000 description 6
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136204—Arrangements to prevent high voltage or static electricity failures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2202/00—Materials and properties
- G02F2202/22—Antistatic materials or arrangements
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Abstract
The application discloses an array substrate, a manufacturing method of the array substrate and a display panel, and belongs to the technical field of display. The array substrate includes: the substrate comprises a substrate base plate, wherein a conductive structure is arranged on the substrate base plate and comprises a grid line and a data line which are overlapped; an insulating structure is arranged on the conductive structure; a common electrode layer is formed on the insulating structure; the non-display area of the substrate base plate is provided with a first concave structure opposite to the grid line and a second concave structure opposite to the data line in the insulating structure, openings of the first concave structure and the second concave structure are far away from the substrate base plate, and the distance between the bottom surface of the first concave structure and the grid line is equal to the distance between the bottom surface of the second concave structure and the data line. The electrostatic charge that gathers more among the second electric capacity has been solved to this application to lead to the second electric capacity to take place the problem of electrostatic breakdown easily, this application is used for array substrate.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to an array substrate, a manufacturing method thereof, and a display panel.
Background
The liquid crystal display panel mainly comprises an array substrate, a color film substrate and a liquid crystal layer, wherein the array substrate and the color film substrate are arranged oppositely, and the liquid crystal layer is arranged between the color film substrate and the array substrate.
The array substrate generally includes: the display device comprises a substrate, a grid line, a grid insulating layer, a data line, a data insulating layer, a flat layer, a passivation layer and a common electrode layer, wherein the grid line, the grid insulating layer, the data line, the data insulating layer, the flat layer, the passivation layer and the common electrode layer are sequentially arranged on the substrate, a first capacitor is formed between the grid line and the common electrode layer, and a second capacitor is formed between the data line and the. Because the distance between the grid line and the common electrode layer is larger than that between the data line and the common electrode, the first capacitance is smaller than the second capacitance. In addition, an alignment layer of the liquid crystal layer is disposed on the common electrode layer, and a rubbing roller is required to roll on the array substrate during the manufacturing process of the alignment layer. During the rolling process of the rubbing roller, more static charges are generated on the surface of the array substrate, and the static charges are accumulated at the first capacitor and the second capacitor.
Because the second capacitor is larger than the first capacitor, more static charges are collected in the second capacitor, so that the second capacitor is easy to generate electrostatic breakdown, and the normal use of the array substrate is influenced.
Disclosure of Invention
The application provides an array substrate, a manufacturing method thereof and a display panel, which can solve the problem that in the prior art, more static charges are accumulated in a second capacitor, so that electrostatic breakdown of the second capacitor is easily caused, and the technical scheme is as follows:
in one aspect, an array substrate is provided, including: a substrate base plate, a first substrate base plate,
the substrate base plate is provided with a conductive structure, and the conductive structure comprises a grid line and a data line which are overlapped;
an insulating structure is arranged on the conductive structure;
a common electrode layer is formed on the insulating structure;
the non-display area of the substrate base plate is provided with a first concave structure facing the grid line and a second concave structure facing the data line, openings of the first concave structure and the second concave structure are far away from the substrate base plate, and the distance between the bottom surface of the first concave structure and the grid line is equal to the distance between the bottom surface of the second concave structure and the data line.
Optionally, a frame sealing adhesive is arranged on the common electrode layer;
the insulating structure is internally provided with a target recessed structure facing the frame sealing adhesive, an opening of the target recessed structure is far away from the substrate, and the first recessed structure and the second recessed structure are both positioned in the target recessed structure.
Optionally, a frame sealing adhesive is arranged on the common electrode layer;
a target recessed structure facing the frame sealing adhesive is arranged in the insulating structure, and an opening of the target recessed structure is far away from the substrate;
the insulating structure is provided with a plurality of second recessed structures, the first recessed structures and a part of the second recessed structures are positioned in the target recessed structures, and the other part of the second recessed structures are positioned outside the target recessed structures.
Optionally, the insulating structure comprises: the data insulating layer, the flat layer and the passivation layer are sequentially arranged on the conductive structure along a direction far away from the conductive structure, and the concave structure in the insulating structure is positioned in at least one film layer of the data insulating layer, the flat layer and the passivation layer.
Optionally, the gate line is disposed between the substrate and the data line, and an intermediate insulating layer is disposed between the gate line and the data line.
In another aspect, there is provided a method for manufacturing an array substrate, the method being used for manufacturing any one of the array substrates, the method including:
forming a conductive structure on a substrate, wherein the conductive structure comprises a grid line and a data line which are overlapped;
forming an insulating structure on the conductive structure;
forming a common electrode layer on the insulating structure;
the non-display area of the substrate base plate is provided with a first concave structure facing the grid line and a second concave structure facing the data line, openings of the first concave structure and the second concave structure are far away from the substrate base plate, and the distance between the bottom surface of the first concave structure and the grid line is equal to the distance between the bottom surface of the second concave structure and the data line.
Optionally, after forming the common electrode layer on the insulating structure, the method further includes:
forming frame sealing glue on the common electrode layer;
the insulating structure is internally provided with a target recessed structure facing the frame sealing adhesive, an opening of the target recessed structure is far away from the substrate, and the first recessed structure and the second recessed structure are both positioned in the target recessed structure.
Optionally, after forming the common electrode layer on the insulating structure, the method further includes:
forming frame sealing glue on the common electrode layer;
the insulating structure is internally provided with a target recessed structure facing the frame sealing adhesive, and an opening of the target recessed structure is far away from the substrate; the insulating structure is provided with a plurality of second recessed structures, the first recessed structures and a part of the second recessed structures are positioned in the target recessed structures, and the other part of the second recessed structures are positioned outside the target recessed structures.
Optionally, forming an insulating structure on the gate line and the data line includes:
sequentially forming a target insulating layer, a flat layer and a passivation layer on the conductive structure;
and forming a recessed structure in the insulating structure in at least one film layer of the target insulating layer, the planarization layer and the passivation layer.
In another aspect, a display panel is provided, and the display device includes the array substrate.
The beneficial effect that technical scheme that this application provided brought includes at least:
in the array substrate provided by the embodiment of the invention, the insulating structure is provided with the first concave structure facing the gate line and the second concave structure facing the data line, and the distance between the bottom surface of the first concave structure and the gate line is equal to the distance between the bottom surface of the second concave structure and the data line. Because the distance between the bottom surface of the first concave structure and the grid line is equal to the distance between the bottom surface of the second concave structure and the data line, and the common electrode layer is arranged along the grooves at the parts of the first concave structure and the second concave structure, the size of the capacitor formed by the common electrode layer and the grid line is equal to the size of the capacitor formed by the common electrode layer and the data line. Therefore, static charges generated by the friction roller in the rolling process can be uniformly distributed on the surface of the array substrate and cannot be concentrated on a certain capacitor of the array substrate, and electrostatic breakdown of the capacitor on the array substrate is avoided.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is an array substrate according to an embodiment of the present invention;
fig. 2 is a schematic diagram illustrating a cross-section BB' of a non-display region of the array substrate in fig. 1 according to an embodiment of the present invention;
fig. 3 is a schematic view of a cross-section BB' of a non-display region of the array substrate of fig. 1 according to another embodiment of the present invention;
fig. 4 is a schematic diagram illustrating a cross-section BB' of a non-display region of the array substrate of fig. 1 according to another embodiment of the present invention;
fig. 5 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present invention;
fig. 6 is a schematic partial structure diagram of a first array substrate according to an embodiment of the present invention;
fig. 7 is a schematic partial structure diagram of a second array substrate according to an embodiment of the present invention;
fig. 8 is a flowchart of another method for manufacturing an array substrate according to an embodiment of the present invention;
fig. 9 is a schematic partial structure diagram of a third array substrate according to an embodiment of the invention.
Detailed Description
To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
Fig. 1 is a schematic view of an array substrate according to an embodiment of the present invention, and as shown in fig. 1, the array substrate 0 may be divided into a display area and a non-display area. Fig. 2 is a schematic diagram of a cross-section BB' of a non-display area of the array substrate in fig. 1 according to an embodiment of the invention.
As shown in fig. 2, the array substrate 0 may include a substrate 01. The substrate 01 is provided with a conductive structure 02, and the conductive structure 02 includes a gate line 021 and a data line 022 which are stacked. An insulating structure 04 is arranged on the conductive structure 02, and a common electrode layer 05 is formed on the insulating structure 04.
On the non-display region (such as the region shown in fig. 1) of the substrate base plate 01, the insulating structure 04 is provided with a first recessed structure a1 facing the gate line 021 and a second recessed structure a2 facing the data line 022, the openings of the first recessed structure a1 and the second recessed structure a2 are far away from the substrate base plate 01, and the distance L1 between the bottom surface of the first recessed structure a1 and the gate line 021 is equal to the distance L2 between the bottom surface of the second recessed structure a2 and the data line 022.
In summary, in the array substrate provided in the embodiments of the present invention, the insulating structure is provided with a first recessed structure facing the gate line and a second recessed structure facing the data line, and a distance between a bottom surface of the first recessed structure and the gate line is equal to a distance between a bottom surface of the second recessed structure and the data line. Because the distance between the bottom surface of the first concave structure and the grid line is equal to the distance between the bottom surface of the second concave structure and the data line, and the common electrode layer is arranged along the grooves at the parts of the first concave structure and the second concave structure, the size of the capacitor formed by the common electrode layer and the grid line is equal to the size of the capacitor formed by the common electrode layer and the data line. Therefore, static charges generated by the friction roller in the rolling process can be uniformly distributed on the surface of the array substrate and cannot be concentrated on a certain capacitor of the array substrate, and electrostatic breakdown of the capacitor on the array substrate is avoided.
The conductive structure 02 includes a gate line 021 and a data line 022 which are stacked, and optionally, an intermediate insulating layer 03 may be further disposed between the gate line 021 and the data line 022. In the embodiment of the present invention, the gate line 021 is disposed between the substrate 01 and the data line 022, optionally, the positions of the gate line 021 and the data line 022 may be interchanged, and the data line 022 is disposed between the gate line 021 and the substrate 01, which is not limited in the embodiment of the present invention.
Fig. 3 is a schematic view of another cross-section BB' of the non-display area of the array substrate in fig. 1 according to an embodiment of the invention. As shown in fig. 3, a gate line 021 on an array substrate may be disposed between a substrate 01 and a data line 022, and an intermediate insulating layer 03 is disposed between the gate line 021 and the data line 022. The insulating structure 04 may include: the target insulating layer 041, the planarization layer 042 and the passivation layer 043 disposed on the conductive structure 02 are sequentially disposed in a direction away from the conductive structure 02.
Alternatively, the thickness of the middle insulating layer 03 in the array substrate may be 2000 angstroms, the thickness of the target insulating layer 041 may be 2000 angstroms, the thickness of the planarization layer 042 may be 20000 angstroms, and the thickness of the passivation layer 043 may be 2500 angstroms.
In addition, a frame sealing adhesive (not shown in fig. 3) may be further disposed on the common electrode layer 05 in the array substrate. The insulating structure 04 may have a target recessed structure C facing the sealant, an opening of the target recessed structure C is far away from the substrate 01, wherein the first recessed structure a1 and the second recessed structure a2 are both located in the target recessed structure C, for example, located on a bottom surface of the target recessed structure C.
It should be noted that the frame sealing adhesive is used to adhere the array substrate and the color film substrate together, and is used to seal the liquid crystal between the color film substrates of the array substrate. In order to improve the adhesion effect and the sealing effect of the frame sealing adhesive, a target recessed structure is usually disposed in the insulating structure in the array substrate, so that the contact area between the frame sealing adhesive and the array substrate is large, and the adhesion effect and the sealing effect of the frame sealing adhesive are further improved. In the embodiment of the invention, the target recessed structure is also provided with the first recessed structure and the second recessed structure, so that the contact area of the frame sealing adhesive and the array substrate is further increased, and the adhesion effect and the sealing effect of the frame sealing adhesive are further improved.
It should be further noted that the recessed structure in the insulating structure 04 (e.g., at least one of the first recessed structure a1, the second recessed structure a2, and the target recessed structure C) may be located in at least one film layer in the insulating structure 04, as exemplified by the recessed structure located in the passivation layer 043 and the planarization layer 042 in the embodiment of the present invention. Alternatively, the recessed structure may also be located in other layers in the insulating structure 04, for example, the recessed structure is located in the passivation layer 043; alternatively, the recess structure is located in the passivation layer 043, the planarization layer 042, and the target insulating layer 041, which is not limited in this embodiment of the invention.
Taking the example of fig. 3 that the second recess structures are located in the target recess structure C, alternatively, as shown in fig. 4, the first recess structure a1 and a portion of the second recess structure a2 in the insulating structure 04 may be located in the target recess structure, and another portion of the second recess structure a2 may also be located outside the target recess structure C.
In summary, in the non-display region of the array substrate provided in the embodiments of the present invention, the insulating structure is provided with a first recess structure facing the gate line and a second recess structure facing the data line, and a distance between a bottom surface of the first recess structure and the gate line is equal to a distance between a bottom surface of the second recess structure and the data line. Because the distance between the bottom surface of the first concave structure and the grid line is equal to the distance between the bottom surface of the second concave structure and the data line, and the common electrode layer is arranged along the grooves at the parts of the first concave structure and the second concave structure, the size of the capacitor formed by the common electrode layer and the grid line is equal to the size of the capacitor formed by the common electrode layer and the data line. Therefore, static charges generated by the friction roller in the rolling process can be uniformly distributed on the surface of the array substrate and cannot be concentrated on a certain capacitor of the array substrate, and electrostatic breakdown of the capacitor on the array substrate is avoided.
Fig. 5 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present invention, where the array substrate may be the array substrate shown in fig. 2, and as shown in fig. 5, the method for manufacturing the array substrate may include:
Alternatively, the gate line may be disposed between the substrate and the data line, or the data line may be disposed between the gate line and the substrate. As shown in fig. 6, in step 501, a gate line 021, an intermediate insulating layer 03, and a data line 022 may be sequentially formed on a substrate 01.
As shown in fig. 7, an insulating structure 04 is formed on a conductive structure (e.g., on a data line 022 in the conductive structure). In forming the insulating structure 04, a target insulating layer, a planarization layer, and a passivation layer may be sequentially formed on the conductive structure in step 502, and a recess structure D may be formed in at least one of the film layers (e.g., the planarization layer and the passivation layer).
Thereafter, a first recess structure and a second recess structure are formed in the recess structure D to obtain the insulating structure 04. The first recessed structure and the second recessed structure are both located in a non-display region of the substrate, the first recessed structure is over against the gate line 021, and the second recessed structure is over against the data line 022. And the openings of the first and second recessed structures are both far away from the substrate 01, and the distance between the bottom surface of the first recessed structure and the gate line 021 is equal to the distance between the bottom surface of the second recessed structure and the data line 022.
After the insulating structure is formed, as shown in fig. 2, a common electrode layer 05 is formed on the insulating structure 04.
In summary, in the non-display region of the array substrate manufactured by the method provided by the embodiment of the invention, the insulating structure is provided with a first recessed structure facing the gate line and a second recessed structure facing the data line, and a distance between a bottom surface of the first recessed structure and the gate line is equal to a distance between a bottom surface of the second recessed structure and the data line. Because the distance between the bottom surface of the first concave structure and the grid line is equal to the distance between the bottom surface of the second concave structure and the data line, and the common electrode layer is arranged along the grooves at the parts of the first concave structure and the second concave structure, the size of the capacitor formed by the common electrode layer and the grid line is equal to the size of the capacitor formed by the common electrode layer and the data line. Therefore, static charges generated by the friction roller in the rolling process can be uniformly distributed on the surface of the array substrate and cannot be concentrated on a certain capacitor of the array substrate, and electrostatic breakdown of the capacitor on the array substrate is avoided.
Fig. 8 is a flowchart of another method for manufacturing an array substrate according to an embodiment of the present invention, where the method for manufacturing an array substrate can be used to manufacture the array substrate shown in fig. 3. As shown in fig. 8, the method for manufacturing the array substrate may include:
step 801 is to form a conductive structure on a substrate, where the conductive structure includes a gate line and a data line that are stacked.
It should be noted that, in step 801, reference may be made to step 501, which is not described herein again in this embodiment of the present invention.
As shown in fig. 9, a target insulating layer 041, a planarization layer 042 and a passivation layer 043 may be sequentially formed on the conductive structure 04 in step 802, and a recess structure D may be formed in at least one of these film layers (e.g., the planarization layer 042 and the passivation layer 043).
It should be noted that, when the embodiment of the present invention is used to manufacture the array substrate shown in fig. 4, the recessed structure in the insulating structure formed in step 802 may include: the concave structure of the object, the first concave structure and a part of the second concave structure which are positioned in the concave structure of the object, and the other part of the second concave structure which is positioned outside the concave structure of the object.
After the insulating structure is formed, as shown in fig. 3, a common electrode layer 05 is formed on the insulating structure 04.
In summary, in the non-display region of the array substrate manufactured by the method provided by the embodiment of the invention, the insulating structure is provided with a first recessed structure facing the gate line and a second recessed structure facing the data line, and a distance between a bottom surface of the first recessed structure and the gate line is equal to a distance between a bottom surface of the second recessed structure and the data line. Because the distance between the bottom surface of the first concave structure and the grid line is equal to the distance between the bottom surface of the second concave structure and the data line, and the common electrode layer is arranged along the grooves at the parts of the first concave structure and the second concave structure, the size of the capacitor formed by the common electrode layer and the grid line is equal to the size of the capacitor formed by the common electrode layer and the data line. Therefore, static charges generated by the friction roller in the rolling process can be uniformly distributed on the surface of the array substrate and cannot be concentrated on a certain capacitor of the array substrate, and electrostatic breakdown of the capacitor on the array substrate is avoided.
An embodiment of the present invention provides a display panel, which may include an array substrate as shown in any one of fig. 2, 3, and 4.
The embodiment of the invention also provides a display device which can comprise any one of the display panels. By way of example, the display device may be: any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
It should be noted that, the method embodiments provided in the embodiments of the present invention can be mutually referred to corresponding display panel and display device embodiments, and the embodiments of the present invention do not limit this. The sequence of the steps of the method embodiments provided by the embodiments of the present invention can be appropriately adjusted, and the steps can be correspondingly increased or decreased according to the situation, and any method that can be easily conceived by those skilled in the art within the technical scope disclosed by the present invention shall be covered by the protection scope of the present invention, and therefore, the detailed description thereof shall not be repeated.
The above description is only exemplary of the present application and should not be taken as limiting, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (10)
1. An array substrate, comprising: a substrate base plate, a first substrate base plate,
the substrate base plate is provided with a conductive structure, and the conductive structure comprises a grid line and a data line which are overlapped;
an insulating structure is arranged on the conductive structure;
a common electrode layer is formed on the insulating structure;
the non-display area of the substrate base plate is provided with a first concave structure facing the grid line and a second concave structure facing the data line, openings of the first concave structure and the second concave structure are far away from the substrate base plate, and the distance between the bottom surface of the first concave structure and the grid line is equal to the distance between the bottom surface of the second concave structure and the data line.
2. The array substrate of claim 1,
frame sealing glue is arranged on the common electrode layer;
the insulating structure is internally provided with a target recessed structure facing the frame sealing adhesive, an opening of the target recessed structure is far away from the substrate, and the first recessed structure and the second recessed structure are both positioned in the target recessed structure.
3. The array substrate of claim 1,
frame sealing glue is arranged on the common electrode layer;
a target recessed structure facing the frame sealing adhesive is arranged in the insulating structure, and an opening of the target recessed structure is far away from the substrate;
the insulating structure is provided with a plurality of second recessed structures, the first recessed structures and a part of the second recessed structures are positioned in the target recessed structures, and the other part of the second recessed structures are positioned outside the target recessed structures.
4. The array substrate of any of claims 1 to 3, wherein the insulating structure comprises: the data insulating layer, the flat layer and the passivation layer are sequentially arranged on the conductive structure along a direction far away from the conductive structure, and the concave structure in the insulating structure is positioned in at least one film layer of the data insulating layer, the flat layer and the passivation layer.
5. The array substrate of claim 4,
the gate line is disposed between the substrate and the data line, and an intermediate insulating layer is disposed between the gate line and the data line.
6. A method for manufacturing an array substrate, the method being used for manufacturing the array substrate of any one of claims 1 to 5, the method comprising:
forming a conductive structure on a substrate, wherein the conductive structure comprises a grid line and a data line which are overlapped;
forming an insulating structure on the conductive structure;
forming a common electrode layer on the insulating structure;
the non-display area of the substrate base plate is provided with a first concave structure facing the grid line and a second concave structure facing the data line, openings of the first concave structure and the second concave structure are far away from the substrate base plate, and the distance between the bottom surface of the first concave structure and the grid line is equal to the distance between the bottom surface of the second concave structure and the data line.
7. The method of claim 6, wherein after forming a common electrode layer on the insulating structure, the method further comprises:
forming frame sealing glue on the common electrode layer;
the insulating structure is internally provided with a target recessed structure facing the frame sealing adhesive, an opening of the target recessed structure is far away from the substrate, and the first recessed structure and the second recessed structure are both positioned in the target recessed structure.
8. The method of claim 6, wherein after forming a common electrode layer on the insulating structure, the method further comprises:
forming frame sealing glue on the common electrode layer;
the insulating structure is internally provided with a target recessed structure facing the frame sealing adhesive, and an opening of the target recessed structure is far away from the substrate; the insulating structure is provided with a plurality of second recessed structures, the first recessed structures and a part of the second recessed structures are positioned in the target recessed structures, and the other part of the second recessed structures are positioned outside the target recessed structures.
9. The method of any one of claims 6 to 8, wherein forming an insulating structure on the gate line and the data line comprises:
sequentially forming a target insulating layer, a flat layer and a passivation layer on the conductive structure;
and forming a recessed structure in the insulating structure in at least one film layer of the target insulating layer, the planarization layer and the passivation layer.
10. A display panel, comprising: the array substrate of any one of claims 1 to 5.
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| CN109765733A (en) * | 2018-12-29 | 2019-05-17 | 成都中电熊猫显示科技有限公司 | A kind of array substrate, display panel and display device |
| CN110164870A (en) * | 2019-05-14 | 2019-08-23 | 深圳市华星光电半导体显示技术有限公司 | Backsheet constructions containing capacitor |
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