CN108872835B - Detection circuit - Google Patents
Detection circuit Download PDFInfo
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- CN108872835B CN108872835B CN201810708324.9A CN201810708324A CN108872835B CN 108872835 B CN108872835 B CN 108872835B CN 201810708324 A CN201810708324 A CN 201810708324A CN 108872835 B CN108872835 B CN 108872835B
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- 238000001514 detection method Methods 0.000 title claims abstract description 97
- 238000005070 sampling Methods 0.000 claims abstract description 32
- 238000002955 isolation Methods 0.000 claims description 56
- 230000003044 adaptive effect Effects 0.000 claims description 7
- 230000003071 parasitic effect Effects 0.000 description 40
- 239000003990 capacitor Substances 0.000 description 18
- 101100102849 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) VTH1 gene Proteins 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000005669 field effect Effects 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000005284 excitation Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention discloses a detection circuit which is applied to a flyback active clamp converter, and is used for detecting and judging the ZVS condition of a main power tube by directly sampling the voltage at one end of a resistor Rcs connected with the source end of the main power tube of the flyback active clamp converter.
Description
Technical Field
The invention relates to a detection circuit, in particular to a detection circuit of a flyback active clamp converter.
Background
With the rapid development of the power electronics field, the application of the switching converter is becoming wider and wider, and in particular, more requirements are being put on the switching converter with high power density, high reliability and small volume. The general traditional low-power AC/DC conversion is realized by adopting flyback topology, and has the advantages of simple structure, low cost and the like; however, due to the influence of leakage inductance of the transformer, voltage clamping modes of the main switching tube of the flyback converter comprise RC buffer absorption, RCD clamping, LCD clamping and active clamping. The active clamp can absorb leakage inductance energy and feed the energy back to the output end in a forward mode, and can fully utilize the excitation inductance and the leakage inductance energy to realize the ZVS of the switching tube, namely, before the switching tube is conducted, the parasitic body diode of the switching tube is conducted first, the drain end of the switching tube is clamped at a lower voltage, at the moment, the switching tube is conducted again, the switching tube is turned on, the loss of the switching tube is reduced, and the efficiency of the switching converter is improved.
The parameters of excitation inductance, leakage inductance, clamping capacitance and the like are changed along with the change of the ambient temperature, so that ZVS cannot be realized by the switching tube, and the efficiency of the switching converter is reduced. Therefore, a detection circuit needs to be added to detect whether the switching tube realizes ZVS in real time, and relevant parameters are adjusted according to the detection result to ensure that the switching tube realizes ZVS.
As shown in fig. 1, a detection circuit of a first flyback active clamp converter in the prior art is a scheme that an NMOS tube clamp circuit and a high-voltage device are externally arranged outside a converter control chip, a transistor Q2 in the circuit is a clamp tube, and specific circuit components and connection modes are described as follows.
The input power supply VIN is connected to one end of the capacitor C1, and the other end of the capacitor C1 is connected to the input power supply ground GND; leakage inductance L K One end is connected to the input power VIN and the clamping capacitor C clamp Is one end of leakage inductance L K Is connected to the exciting inductance L M And the 1 terminal of the transformer T1; the turn ratio of the transformer T1 is NP/NS; clamping capacitor C clamp Is connected to the drain terminal of the transistor Q2, the parasitic diode D of the transistor Q2 P2 Cathode of transistor Q2 parasitic capacitance C P2 Is a member of the group; source terminal of transistor Q2, parasitic diode D of transistor Q2 P2 Anode of transistor Q2 parasitic capacitance C P2 Is connected to the exciting inductance L M And the other end of the transformer T1, one end of the isolation/bootstrap driver U3, one end of the high-voltage device U6, the drain end of the transistor Q1, the parasitic diode D of the transistor Q1 P1 Cathode of transistor Q1 parasitic capacitance C P1 Is a member of the group; the gate terminal of the transistor Q2 is connected to the other end of the isolation/bootstrap drive U3. The third end of the isolation/bootstrap driver U3 is connected to a GTH pin of the internal control circuit U1; the transistors Q1 and Q2 are NMOS transistors and the threshold voltage of NMOS is VTHN; the other end of the high-voltage device U6 is connected to an SW pin of the internal control circuit U1; the gate end of the transistor Q1 is connected to a GTL pin of the internal control circuit U1; source terminal of transistor Q1, parasitic diode D of transistor Q1 P1 Anode of transistor Q1 parasitic capacitance C P1 Is connected to the other end of the resistor R CS A CS pin of the internal control circuit U1; resistor R CS The other end of (2) is connected to the input power ground GND; the adaptive U2 and the low voltage detection U4 are integrated in the internal control circuit U1. One end of the low-voltage detection U4 is connected to an SW pin of the internal control circuit U1, and the other end of the low-voltage detection U is connected to one end of the self-adaptive U2; the other end of the self-adaptive U2 is connected to a GTH pin of the internal control circuit U1; the 4 end of the transformer T1 is connected to the anode of the diode D1; the cathode of the diode D1 is connected to the capacitor C out One end of the output voltage VOUT and one end of the voltage sampling isolation feedback U5; the 3 terminal of the transformer T1 is connected to the capacitor C out Is connected with the other end of the power supply ground VSS; the other end of the voltage sampling isolation feedback U5 is connected to the FB pin of the internal control circuit U1;
the internal control circuit U1 is a control chip of the power supply system, receives a feedback signal output by the voltage sampling isolation feedback U5 through the FB pin, and samples the resistor R through the CS pin cs The voltage at one end is the voltage of the input power ground GND and the first input power VDD through the GTL pin output range, the gate terminal of the transistor Q1 is controlled to turn on or off the transistor Q1, the voltage output by the high-voltage device U6 is received through the SW pin, the voltage of the input power ground GND and the first input power VDD through the GTH pin output range is output to the isolation/bootstrap driving U3.
The voltage sampling isolation feedback U5 samples the output voltage of the power supply system and generates a feedback signal, and the internal control circuit U1 receives the feedback signal through the FB pin.
The high voltage device U6 samples the drain voltage of the transistor Q1, and the high voltage device U6 sets the threshold voltage VTH to be higher than the input power ground GND. When the drain voltage of the transistor Q1 is higher than the threshold voltage VTH set by the high-voltage device U6, the high-voltage device U6 outputs the set threshold voltage VTH; after the drain voltage of the transistor Q1 is lower than the threshold voltage VTH set by the high-voltage device U6, the high-voltage device U6 outputs the drain voltage of the transistor Q1 to the SW pin of the internal control circuit U1.
The circuit of fig. 1 is due to the parasitic diode D of transistor Q1 having an absolute value of transistor Q1 and a source voltage range of transistor Q2 from below input power GND P1 Voltage drop across and sampling resistor R CS The sum of the voltage drops across it reaches vin+ (NP/NS) VOUT. In order to turn on the transistor Q2, the voltage at the gate terminal of the transistor Q2 needs to be higher than or equal to the sum of the voltage at the source of the transistor Q2 and the threshold voltage VTHN of the transistor Q2; in order to turn off the transistor Q2, the gate voltage of the transistor Q2 needs to be lower than the sum of the source voltage of the transistor Q2 and the threshold voltage VTHN of the transistor Q2; the internal control circuit U1 outputs voltages in the range of the input power ground GND and the first input power VDD through the GTH pin, where the first input power VDD is far smaller than vin+ (NP/NS) VOUT, and cannot normally control the turn-on of the transistor Q2, and the isolation/bootstrap driver U3 needs to be introduced.
The isolation/bootstrap driver U3 receives the signal output from the internal control circuit U1 through the GTH pin, and receives the voltage at the source terminal of the transistor Q2 as the reference voltage of the isolation/bootstrap driver U3, where the voltage range of the output signal is vin+ (NP/NS) VOUT to vin+ (NP/NS) vout+vthn, so that the gate terminal of the transistor Q2 can be controlled normally to turn on or off the transistor Q2.
The adaptation U2 is integrated in the internal control circuit U1. The self-adaptive U2 receives the voltage output by the low-voltage detection U4 to adjust the signal output by the self-adaptive U2, and the self-adaptive U2 outputs the signal to the isolation/bootstrap driving U3 through the GTH pin of the internal control circuit U1 to indirectly control the on or off of the transistor Q2.
The low voltage detection U4 is integrated in the internal control circuit U1 and sets a threshold voltage VTH1 and VTH1 is higher than the input power supply ground GND, less than or equal to the threshold voltage VTH set by the high voltage device U6. The low voltage detection U4 receives the voltage output by the high voltage device U6 through the SW pin of the internal control circuit U1, the low voltage detection U4 compares the received voltage output by the high voltage device U6 with a set threshold voltage VTH1 before the transistor Q1 is conducted, if the voltage output by the high voltage device U6 is higher than the set threshold voltage VTH1 of the low voltage detection U4, the low voltage detection U4 outputs the voltage to the self-adaptive U2, the self-adaptive U2 receives the voltage output by the low voltage detection U4 before the transistor Q1 is conducted to adjust the signal output by the self-adaptive U2, and the self-adaptive U2 controls the gate end of the transistor Q2 to conduct the transistor Q2 through the isolation/bootstrap driving U3 and increases the conducting time of the transistor Q2; once the voltage output by the high-voltage device U6 is lower than the threshold voltage VTH1 set by the low-voltage detection U4, the isolation/bootstrap driver U3 directly controls the gate terminal of the transistor Q2 to turn on the transistor Q2 without increasing the turn-on time of the transistor Q2, and at this time, the transistor Q1 is determined to realize ZVS, and the parasitic diode D of the transistor Q1 P1 Turned on to make the drain voltage of the transistor Q1 lower than the input power GND, and the drain voltage of the transistor Q1 is the parasitic diode D of the transistor Q1 P1 Voltage drop across and sampling resistor R CS The sum of the voltage drops at the two ends is sampled by a resistor R CS The voltage at one end connected to the CS pin of the internal control circuit U1 is also lower than the input power GND.
FIG. 2 shows a second prior art detection circuit for a flyback active clamp converter, which is a scheme in which the PMOS tube clamp circuit and the high-voltage device are externally arranged outside the converter control chip, i.e., the crystal in FIG. 1The transistor Q2 is a PMOS transistor with a threshold value of VTHP. The source end of the PMOS tube Q2 of the circuit and the parasitic diode D of the PMOS tube Q2 P2 Parasitic capacitance C of cathode and PMOS tube Q2 of (C) P2 Is connected to the input power ground GND; PMOS tube Q2 drain terminal, PMOS tube Q2 parasitic diode D P2 Parasitic capacitance C of anode and PMOS transistor Q2 P2 Is connected to the clamp capacitor C clamp Clamping capacitor C clamp Is connected to the 2-terminal of the transformer T1 and the exciting inductance L M One end of the high voltage detection U4, the drain end of the transistor Q1, the parasitic diode D of the transistor Q1 P1 One end of transistor Q1 parasitic capacitance C P1 Is a member of the group; the gate terminal of the transistor Q2 is connected to the GTH pin of the internal control circuit U1.
The circuit of fig. 2 is to turn on the transistor Q2, wherein the voltage at the gate terminal of the transistor Q2 is lower than the voltage at the source terminal of the transistor Q2, i.e. the sum of the input power ground GND and the threshold voltage VTHP of the transistor Q2; in order to turn off the transistor Q2, the gate voltage of the transistor Q2 needs to be higher than the source voltage of the transistor Q2, i.e. the sum of the input power ground GND and the threshold voltage VTHP of the transistor Q2; the internal control circuit U1 outputs the voltage ranging from the ground GND to the VDD of the input power supply through the GTH pin, and can normally control the on and off of the transistor Q2, so that the isolation/bootstrap driving U3 is not required in FIG. 2; the other circuits are connected in the same way as the circuit shown in fig. 1, and the working principle of the circuit shown in fig. 2 is the same as that of the circuit shown in fig. 1.
Assuming that the turn ratio of the transformer T1 is NP/NS, the drain voltage of the transistor Q1 is VIN+ (NP/NS) VOUT. In an AC-DC converter, the input voltage may be up to 360V, i.e., the input power VIN is 360V; the turn ratio NP/NS of the transformer T1 is 14, the output voltage VOUT is 5V, and the drain terminal voltage of the transistor Q1 is 430V. If the highest voltage withstand value of the internal control circuit U1 is lower than 100V, the drain voltage of the transistor Q1 needs to be sampled by the high-voltage device U6, and the high-voltage device U6 is typically a depletion type N-channel field effect transistor or an enhancement type N-channel field effect transistor with a voltage withstand value up to 700V, which occupies the area on the PCB board and increases the cost of the power supply system.
A method for reducing the occupied area on a PCB board is to integrate a high-voltage device U6 into an internal control circuit U1, as shown in FIG. 3, FIG. 3 is a detection circuit of a third flyback active clamp converter in the prior art, the circuit is an NMOS tube clamp circuit, the high-voltage device is built in the scheme of the converter control chip, a transistor Q2 in the circuit is a clamp tube, the specific circuit composition and connection mode are adopted, and the functions of each functional module are described as follows.
The high-voltage device U6A is integrated in the internal control circuit U1A, one end of the high-voltage device U6A is connected with the SW pin of the internal control circuit U1A, the other end of the high-voltage device U6A is connected with one end of the low-voltage detection U4, and the other circuit connection modes are the same as those of the circuit shown in FIG. 1; the difference in the operation principle is that the high voltage device U6A and the low voltage detection U4 together determine whether the transistor Q1 achieves ZVS. According to the scheme, the high-voltage device U6A needs to bear higher voltage, so that the high-voltage device U6A needs to occupy a larger area in the internal control circuit U1A, and the cost of the internal control circuit U1A is increased.
Fig. 4 shows a detection circuit of a fourth flyback active clamp converter in the prior art, which is a PMOS tube clamp circuit, and the scheme of the high-voltage device being built in the converter control chip, that is, the transistor Q2 in fig. 3 adopts a PMOS tube. The PMOS transistor source end and the PMOS parasitic diode D of the circuit P2 Cathode, PMOS parasitic capacitance C P2 Is connected to the input power ground GND; PMOS tube drain terminal, PMOS parasitic diode D P2 Anode, PMOS parasitic capacitance C P2 Is connected to the clamp capacitor C clamp Clamping capacitor C clamp Is connected to the 2-terminal of the transformer T1 and the exciting inductance L M Is connected to the drain terminal of the transistor Q1, the parasitic diode D of the transistor Q1 P1 Cathode of transistor Q1 parasitic capacitance C P1 SW pin of the internal control circuit U1A; the gate terminal of the transistor Q2 is connected to the GTH pin of the internal control circuit U1A, and the isolation/bootstrap driver U3 is also not required in fig. 4 of the present circuit; the other circuits are connected in the same way as the circuit shown in fig. 3, and the working principle of the circuit shown in fig. 4 is the same as that of the circuit shown in fig. 3.
In summary, the existing detection circuit of the flyback active clamp converter has the following defects:
the scheme of the external and internal control chips of the high-voltage device cannot solve the contradiction between the large area occupied by the power supply system on the PCB and the high cost of the control chip.
Disclosure of Invention
In view of this, the technical problem to be solved by the present invention is to provide a detection circuit of a flyback active clamp converter, which reduces the occupied area of a PCB board, and can complete the detection of whether the ZVS is implemented on the main power switching tube without increasing the cost of a control chip, and also can reduce the cost of the circuit.
In order to solve the technical problems, the technical scheme of the detection circuit of the flyback active clamp converter provided by the invention is as follows:
the utility model provides a detection circuit, is applied to flyback active clamp converter, flyback active clamp converter is including main power switch tube and clamp tube, and the clamp tube is NMOS pipe, its characterized in that:
the detection circuit includes: the internal control circuit U1B, the self-adaptive U2A, the isolation/bootstrap driving U3, the low-voltage detection U4A, the voltage sampling isolation feedback U5 and the resistor Rcs; the internal control circuit U1B comprises four pins of FB, CS, GTL and GTH; the low-voltage detection U4A and the self-adaptive U2A are arranged in an internal control circuit U1B; one end of the resistor Rcs is connected with a CS pin of the internal control circuit U1B and a source end of the main power switching tube, and the other end of the resistor Rcs is connected with the input power ground GND;
the voltage sampling isolation feedback U5 samples output voltage and outputs an isolated feedback signal to the FB pin;
the isolation/bootstrap driving U3 receives a signal output by the GTH pin, receives the voltage of the drain end of the main power switch tube, and outputs a signal to control the on or off of the clamp tube;
the low-voltage detection U4A is provided with a threshold voltage VTH3, the threshold voltage VTH3 is lower than an input power supply GND, the low-voltage detection U4A samples the voltage at one end of a resistor Rcs through a CS pin, compares the sampled voltage with the threshold voltage VTH3, and inputs a comparison result into the self-adaptive U2A;
the self-adaptive U2A receives a comparison result of the low-voltage detection U4A before the main power tube is conducted, when the sampling voltage is higher than the threshold voltage VTH3, a GTH pin outputs a signal to the isolation/bootstrap driving U3, and the signal controls the clamp tube to be conducted through the isolation/bootstrap driving U3 and increases the conduction time of the clamp tube; once the sampling voltage is below the threshold voltage VTH3, the GTH pin outputs a signal to the isolation/bootstrap driver U3 that controls the clamp to conduct through the isolation/bootstrap driver U3 without increasing the clamp conduction time.
As an equivalent alternative to the above technical solution, it is characterized in that: the low voltage detection U4A is placed between the CS pin and one end of the resistor Rcs.
As an equivalent alternative to the above technical solution, it is characterized in that: the adaptive U2A is placed between the GTH pin and the third end of the isolation/bootstrap driver U3.
As an equivalent alternative to the above technical solution, it is characterized in that: the low voltage detection U4A is placed between the CS pin and one end of the resistor Rcs, and the adaptive U2A is placed between the GTH pin and the third end of the isolation/bootstrap driver U3.
As one of the above technical solutions, the following is specific:
the utility model provides a detection circuit, is applied to flyback active clamp converter, flyback active clamp converter is including main power switch tube and clamp tube, and clamp tube is PMOS pipe, its characterized in that:
the detection circuit includes: the internal control circuit U1B, the self-adaptive U2A, the low-voltage detection U4A, the voltage sampling isolation feedback U5 and the resistor Rcs; the internal control circuit U1B comprises four pins of FB, CS, GTL and GTH; the low-voltage detection U4A and the self-adaptive U2A are arranged in an internal control circuit U1B; one end of the resistor Rcs is connected with a CS pin of the internal control circuit U1B and a source end of the main power switching tube, and the other end of the resistor Rcs is connected with the input power ground GND;
the voltage sampling isolation feedback U5 samples output voltage and outputs an isolated feedback signal to the FB pin;
the low-voltage detection U4A is provided with a threshold voltage VTH3, the threshold voltage VTH3 is lower than an input power supply GND, the low-voltage detection U4A samples the voltage at one end of a resistor Rcs through a CS pin, compares the sampled voltage with the threshold voltage VTH3, and inputs a comparison result into the self-adaptive U2A;
the self-adaptive U2A receives a comparison result of the low-voltage detection U4A before the main power tube is conducted, and when the sampling voltage is higher than the threshold voltage VTH3, the GTH pin outputs a signal to control the clamp tube to conduct and increase the conduction time of the clamp tube; once the sampling voltage is lower than the threshold voltage VTH3, the GTH pin output signal controls the clamp to conduct but does not increase the conduction time of the clamp.
As an equivalent alternative to the above technical solution, it is characterized in that: the low voltage detection U4A is placed between the CS pin and one end of the resistor Rcs.
As an equivalent alternative to the above technical solution, it is characterized in that: and placing the self-adaptive U2A between the GTH pin and the gate end of the clamping tube.
As an equivalent alternative to the above technical solution, it is characterized in that: the low-voltage detection U4A is arranged between the CS pin and one end of the resistor Rcs, and the self-adaptive U2A is arranged between the GTH pin and the gate end of the clamping tube.
Term interpretation:
clamping tube: the switching transistors in the flyback active clamp converter clamp circuits, such as the corresponding components in fig. 1, 2, 3 and 4, are all transistors Q2.
FB pin: and receiving a feedback signal output by the voltage sampling isolation feedback U5.
CS pin: sampling resistor R cs Voltage at one end.
GTL pin: and outputting a signal to control the on or off of the main power tube.
GTH pin: aiming at the scheme that the clamping tube is an NMOS tube, outputting a signal, and controlling the clamping tube to be turned on or off through an isolation bootstrap/driving U3; aiming at the scheme that the clamping tube is a PMOS tube, a signal is output to directly control the on or off of the clamping tube.
To illustrate the beneficial effects of the present invention, it is also assumed that the transformer turn ratio is NP/NS and the primary power transistor drain voltage is vin+ (NP/NS) ×vout. In an AC-DC converter, the input voltage may be up to 360V, i.e., the input power VIN is 360V; the turn ratio NP/NS of the transformer is 14, the output voltage is 5V, and the drain voltage of the main power tube is 430V. If the highest withstand voltage of the internal control circuit U1B is lower than 100V, the prior art samples the drain voltage of the main power transistor through the high-voltage device U6, where the high-voltage device U6 is generally a depletion type N-channel field effect transistor or an enhancement type N-channel field effect transistor with a withstand voltage of 700V, which occupies the area on the PCB board and increases the cost of the power supply system. The voltage at one end of the resistor Rcs is directly sampled to realize detection and judgment of the ZVS condition of the main power tube, the highest voltage is the difference between the first input power supply VDD and the threshold voltage VTHN of the main power tube, namely VDD-VTHN, the difference is far smaller than vin+ (NP/NS) VOUT, and the voltage is within the voltage-withstanding range of the internal control circuit U1, so that the participation of high-voltage devices is not needed.
In summary, compared with the prior art, the invention has the following beneficial effects:
first, reduce PCB board area, need not high-voltage device U6, reduce electrical power generating system cost.
Second, the pins of the internal control circuit U1B are reduced, and the SW detection pins are not needed.
Third, because the low-voltage detection U4A is adopted, the occupied area in the internal control circuit U1B is far lower than the occupied area of the high-voltage device U6A in the internal control circuit U1A, the cost of the internal control circuit U1B is reduced, and the cost of the whole power supply system is further reduced.
Drawings
FIG. 1 is a schematic diagram of a first prior art flyback active clamp converter detection circuit;
FIG. 2 is a schematic diagram of a second prior art flyback active clamp converter detection circuit;
FIG. 3 is a schematic diagram of a third prior art flyback active clamp converter detection circuit;
FIG. 4 is a schematic diagram of a fourth prior art flyback active clamp converter detection circuit;
FIG. 5 is a schematic diagram of a detection circuit for a flyback active clamp converter according to a first embodiment of the present invention;
fig. 6 is a detection circuit of a flyback active clamp converter according to a second embodiment of the present invention.
Detailed Description
The invention concept of the application is that the voltage at one end of the resistor Rcs connected with the source end of the main power tube of the flyback active clamp converter is directly sampled, so that the detection and judgment of the ZVS condition of the main power tube are realized, and the voltage at one end of the resistor Rcs is greatly reduced compared with the voltage at the drain end of the main power, so that a high-voltage device which affects the occupation area and the cost of a power supply system is not needed, and a pin for detecting the voltage at the drain end of the main power tube is not needed, and the internal control chip and the power supply system are simplified.
The present invention will be described in further detail below with reference to the drawings and specific embodiments in order to enable those skilled in the art to better understand the present application.
Example 1
As shown in fig. 5, in the detection circuit of the flyback active clamp converter according to the second embodiment of the present invention, an input power source VIN is connected to one end of a capacitor C1, and the other end of the capacitor C1 is connected to an input power source ground GND; leakage inductance L K One end is connected to the input power VIN and the clamping capacitor C clamp Is one end of leakage inductance L K Is connected to the exciting inductance L M And the 1 terminal of the transformer T1; clamping capacitor C clamp Is connected to the drain terminal of the transistor Q2, the parasitic diode D of the transistor Q2 P2 Cathode of transistor Q2 parasitic capacitance C P2 Is a member of the group; source terminal of transistor Q2, parasitic diode D of transistor Q2 P2 Anode of transistor Q2 parasitic capacitance C P2 Is connected to the exciting inductance L M And the other end of the transformer T1, one end of the isolation/bootstrap driver U3, the drain end of the transistor Q1, the parasitic diode D of the transistor Q1 P1 Cathode of transistor Q1 parasitic capacitance C P1 Is a member of the group; the gate terminal of the transistor Q2 is connected to the other end of the isolation/bootstrap drive U3. The third end of the isolation/bootstrap driver U3 is connected to a GTH pin of the internal control circuit U1B; the transistor Q2 is an NMOS transistor; the gate end of the transistor Q1 is connected to a GTL pin of the internal control circuit U1B; source terminal of transistor Q1, parasitic diode D of transistor Q1 P1 Anode of transistor Q1 parasitic capacitance C P1 Is connected to the other end of the resistor R CS A CS pin of the internal control circuit U1B; resistor R CS The other end of (2) is connected to the input power ground GND; the self-adaptive U2A and the low-voltage detection U4A are integrated in the internal control circuit U1B; one end of the self-adaptive U2A is connected to one end of the low-voltage detection U4A, and the other end of the self-adaptive U2A is connected withA GTH pin connected to the internal control circuit U1B; the other end of the low-voltage detection U4A is connected to a CS pin of the internal control circuit U1B; the 4 end of the transformer T1 is connected to the anode of the diode D1; the cathode of the diode D1 is connected to the capacitor C out One end of the output voltage VOUT and one end of the voltage sampling isolation feedback U5; the 3 terminal of the transformer T1 is connected to the capacitor C out Is connected with the other end of the power supply ground VSS; the other end of the voltage sampling isolation feedback U5 is connected to the FB pin of the internal control circuit U1B;
the internal control circuit U1B is a power system control chip, the internal control circuit U1B receives a feedback signal output by the voltage sampling isolation feedback U5 through the FB pin, and samples the resistor R through the CS pin cs The voltage at one end controls the gate end of the transistor Q1 through the GTL pin to enable the transistor Q1 to be turned on or turned off, and outputs a control signal to the isolation/bootstrap driving U3 through the GTH pin.
The voltage sampling isolation feedback U5 samples the output voltage of the power supply system and generates a feedback signal, and the internal control circuit U1B receives the feedback signal through the FB pin.
The isolation/bootstrap driver U3 receives the signal output from the internal control circuit U1B via the GTH pin, receives the voltage at the drain terminal of the transistor Q1, and outputs a signal to control the gate terminal of the transistor Q2 to turn on or off the transistor Q2.
The low-voltage detection U4A samples the resistor R through a CS pin of the internal control circuit U1B cs Voltage at one end and the resistor R obtained by sampling cs The voltage at one end is compared with a threshold voltage VTH3 set by the low voltage detection U4A, and the low voltage detection U4A inputs the comparison result into the adaptive U2A. The threshold voltage VTH3 set by the low voltage detection U4A is lower than the input power GND.
The self-adaptive U2A receives the comparison result of the low-voltage detection U4A before the transistor Q1 is conducted, and when the low-voltage detection U4A is used for sampling the resistor R obtained by the CS pin of the internal control circuit U1B cs When the voltage at one end is higher than the threshold voltage VTH3 set by the low-voltage detection U4A, the self-adaptive U2A outputs a signal to the isolation/bootstrap driving U3 through the GTH pin of the internal control circuit U1B, and the isolation/bootstrap driving U3 controls the gate end of the transistor Q2 to enable the transistor Q2 to be conducted and increase the conduction time of the transistor Q2;resistor R sampled by CS pin of internal control circuit U1B once low voltage detection U4A cs When the voltage at one end is lower than the threshold voltage VTH3 set by the low voltage detection U4A, the self-adaptive U2A outputs a signal to the isolation/bootstrap driving U3 through the GTH pin of the internal control circuit U1B, the isolation/bootstrap driving U3 controls the gate end of the transistor Q2 to enable the transistor Q2 to be conducted, the conduction time of the transistor Q2 is not increased any more, at the moment, the transistor Q1 is judged to realize ZVS, and the parasitic diode D of the transistor Q1 is judged to be P1 Turned on to make the drain voltage of the transistor Q1 lower than the input power GND, and the drain voltage of the transistor Q1 is the parasitic diode D of the transistor Q1 P1 Voltage drop across and sampling resistor R CS The sum of the voltage drops at the two ends is sampled by a resistor R CS The voltage at one end connected to the CS pin of the internal control circuit U1B is also lower than the input power GND and lower than the threshold voltage VTH3 set by the low voltage detection U4A.
Second embodiment
Referring to fig. 6, a detection circuit of a flyback active clamp converter according to a second embodiment of the present invention, that is, a PMOS transistor is adopted as the transistor Q2 in the first embodiment. PMOS transistor source and PMOS parasitic diode D in the circuit of FIG. 2 P2 Cathode, PMOS parasitic capacitance C P2 Is connected to the input power ground GND; PMOS tube drain terminal, PMOS parasitic diode D P2 Anode, PMOS parasitic capacitance C P2 Is connected to the clamp capacitor C clamp Clamping capacitor C clamp Is connected to the 2-terminal of the transformer T1 and the exciting inductance L M Is connected to the drain terminal of the transistor Q1, the parasitic diode D of the transistor Q1 P1 Cathode of transistor Q1 parasitic capacitance C P1 Is a member of the group; the gate end of the transistor Q2 is connected to the GTH pin of the internal control circuit U1B, and the transistor Q2 in the embodiment adopts a PMOS tube, so that the isolation/bootstrap driving U3 is not needed; the other circuits are connected in the same way as the circuit shown in fig. 5, and the working principle of the circuit shown in fig. 6 is the same as that of the circuit shown in fig. 5. And will not be described in detail herein.
The above is only a preferred embodiment of the present invention, and alterations and modifications may be made to the above-described specific embodiment by those skilled in the art to which the present invention pertains. Therefore, the present invention is not limited to the specific embodiments disclosed and described above, and some modifications and variations of the present invention should fall within the scope of the claims of the present invention, such as placing the low voltage detection U4A and/or the adaptive U2A outside the internal control circuit U1B. In addition, although specific terms are used in the present specification, these terms are for convenience of description only and do not limit the present invention in any way.
Claims (8)
1. The utility model provides a detection circuit, is applied to flyback active clamp converter, flyback active clamp converter is including main power switch tube and clamp tube, and the clamp tube is NMOS pipe, its characterized in that:
the detection circuit includes: the internal control circuit U1B, the self-adaptive U2A, the isolation/bootstrap driving U3, the low-voltage detection U4A, the voltage sampling isolation feedback U5 and the resistor Rcs; the internal control circuit U1B comprises four pins of FB, CS, GTL and GTH; the low-voltage detection U4A and the self-adaptive U2A are arranged in an internal control circuit U1B; one end of the resistor Rcs is connected with a CS pin of the internal control circuit U1B and a source end of the main power switching tube, and the other end of the resistor Rcs is connected with the input power ground GND;
the voltage sampling isolation feedback U5 samples output voltage and outputs an isolated feedback signal to the FB pin;
the isolation/bootstrap driving U3 receives a signal output by the GTH pin, receives the voltage of the drain end of the main power switch tube, and outputs a signal to control the on or off of the clamp tube;
the low-voltage detection U4A is provided with a threshold voltage VTH3, the threshold voltage VTH3 is lower than an input power supply GND, the low-voltage detection U4A samples the voltage at one end of a resistor Rcs through a CS pin, compares the sampled voltage with the threshold voltage VTH3, and inputs a comparison result into the self-adaptive U2A;
the self-adaptive U2A receives a comparison result of the low-voltage detection U4A before the main power tube is conducted, when the sampling voltage is higher than the threshold voltage VTH3, a GTH pin outputs a signal to the isolation/bootstrap driving U3, and the signal controls the clamp tube to be conducted through the isolation/bootstrap driving U3 and increases the conduction time of the clamp tube; once the sampling voltage is below the threshold voltage VTH3, the GTH pin outputs a signal to the isolation/bootstrap driver U3 that controls the clamp to conduct through the isolation/bootstrap driver U3 without increasing the clamp conduction time.
2. The detection circuit of claim 1, wherein: the low voltage detection U4A is placed between the CS pin and one end of the resistor Rcs.
3. The detection circuit of claim 1, wherein: the adaptive U2A is placed between the GTH pin and the third end of the isolation/bootstrap driver U3.
4. The detection circuit of claim 1, wherein: the low voltage detection U4A is placed between the CS pin and one end of the resistor Rcs, and the adaptive U2A is placed between the GTH pin and the third end of the isolation/bootstrap driver U3.
5. The utility model provides a detection circuit, is applied to flyback active clamp converter, flyback active clamp converter is including main power switch tube and clamp tube, and clamp tube is PMOS pipe, its characterized in that:
the detection circuit includes: the internal control circuit U1B, the self-adaptive U2A, the low-voltage detection U4A, the voltage sampling isolation feedback U5 and the resistor Rcs; the internal control circuit U1B comprises four pins of FB, CS, GTL and GTH; the low-voltage detection U4A and the self-adaptive U2A are arranged in an internal control circuit U1B; one end of the resistor Rcs is connected with a CS pin of the internal control circuit U1B and a source end of the main power switching tube, and the other end of the resistor Rcs is connected with the input power ground GND;
the voltage sampling isolation feedback U5 samples output voltage and outputs an isolated feedback signal to the FB pin;
the low-voltage detection U4A is provided with a threshold voltage VTH3, the threshold voltage VTH3 is lower than an input power supply GND, the low-voltage detection U4A samples the voltage at one end of a resistor Rcs through a CS pin, compares the sampled voltage with the threshold voltage VTH3, and inputs a comparison result into the self-adaptive U2A;
the self-adaptive U2A receives a comparison result of the low-voltage detection U4A before the main power tube is conducted, and when the sampling voltage is higher than the threshold voltage VTH3, the GTH pin outputs a signal to control the clamp tube to conduct and increase the conduction time of the clamp tube; once the sampling voltage is lower than the threshold voltage VTH3, the GTH pin output signal controls the clamp to conduct but does not increase the conduction time of the clamp.
6. The detection circuit of claim 5, wherein: the low voltage detection U4A is placed between the CS pin and one end of the resistor Rcs.
7. The detection circuit of claim 5, wherein: and placing the self-adaptive U2A between the GTH pin and the gate end of the clamping tube.
8. The detection circuit of claim 5, wherein: the low-voltage detection U4A is arranged between the CS pin and one end of the resistor Rcs, and the self-adaptive U2A is arranged between the GTH pin and the gate end of the clamping tube.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106059313A (en) * | 2016-07-19 | 2016-10-26 | 深圳南云微电子有限公司 | Active clamp flyback circuit and control method thereof |
| CN108155799A (en) * | 2016-12-06 | 2018-06-12 | 台达电子企业管理（上海）有限公司 | For the control method and control device of flyback converter circuit |
| CN108809107A (en) * | 2018-07-13 | 2018-11-13 | 深圳南云微电子有限公司 | A kind of method and circuit of the self adaptive control of active clamp flyback converter |
| CN208421161U (en) * | 2018-07-02 | 2019-01-22 | 广州金升阳科技有限公司 | A kind of detection circuit |
| CN111200364A (en) * | 2020-02-25 | 2020-05-26 | 浙江大学 | AC-DC conversion device based on active clamping flyback converter |
| CN112491258A (en) * | 2020-11-20 | 2021-03-12 | 广州金升阳科技有限公司 | Clamping circuit of active clamping flyback converter and control method thereof |
-
2018
- 2018-07-02 CN CN201810708324.9A patent/CN108872835B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106059313A (en) * | 2016-07-19 | 2016-10-26 | 深圳南云微电子有限公司 | Active clamp flyback circuit and control method thereof |
| CN108155799A (en) * | 2016-12-06 | 2018-06-12 | 台达电子企业管理（上海）有限公司 | For the control method and control device of flyback converter circuit |
| CN208421161U (en) * | 2018-07-02 | 2019-01-22 | 广州金升阳科技有限公司 | A kind of detection circuit |
| CN108809107A (en) * | 2018-07-13 | 2018-11-13 | 深圳南云微电子有限公司 | A kind of method and circuit of the self adaptive control of active clamp flyback converter |
| CN111200364A (en) * | 2020-02-25 | 2020-05-26 | 浙江大学 | AC-DC conversion device based on active clamping flyback converter |
| CN112491258A (en) * | 2020-11-20 | 2021-03-12 | 广州金升阳科技有限公司 | Clamping circuit of active clamping flyback converter and control method thereof |
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