CN108872768B - Accurate test method for negative sequence element in double-voltage lockout - Google Patents

Accurate test method for negative sequence element in double-voltage lockout Download PDF

Info

Publication number
CN108872768B
CN108872768B CN201810594705.9A CN201810594705A CN108872768B CN 108872768 B CN108872768 B CN 108872768B CN 201810594705 A CN201810594705 A CN 201810594705A CN 108872768 B CN108872768 B CN 108872768B
Authority
CN
China
Prior art keywords
voltage
phase
bus
sequence voltage
fault
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201810594705.9A
Other languages
Chinese (zh)
Other versions
CN108872768A (en
Inventor
陈泽华
刘亚男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yichang Power Supply Co of State Grid Hubei Electric Power Co Ltd
Original Assignee
Yichang Power Supply Co of State Grid Hubei Electric Power Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yichang Power Supply Co of State Grid Hubei Electric Power Co Ltd filed Critical Yichang Power Supply Co of State Grid Hubei Electric Power Co Ltd
Priority to CN201810594705.9A priority Critical patent/CN108872768B/en
Publication of CN108872768A publication Critical patent/CN108872768A/en
Application granted granted Critical
Publication of CN108872768B publication Critical patent/CN108872768B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections

Abstract

Accurate test method for negative sequence element in composite voltage latch, composite voltage latch comprises low powerVoltage lock, complex sequence voltage lock and zero sequence voltage lock, when the voltage of the bus is lower than the low voltage fixed value of the low voltage lock, the zero sequence voltage is higher than the zero sequence voltage fixed value of the zero sequence voltage lock or the negative sequence voltage is higher than the negative sequence voltage fixed value of the complex sequence voltage lock, the complex voltage element acts, the bus voltage of the non-fault phase is not changed when the two phases are in short circuit fault, the amplitude of the bus voltage of the two phases of the fault phase is reduced, the angle is also changed, the included angle between the two phases of the voltage is reduced, and the symmetrical relation is maintained, for example, when the phase A is the non-fault phase, the phase B and the phase C are in short circuit, the non-fault bus voltage is Ue (U1 + U2) 57.7V, the bus voltage is normal when UM is used, the bus voltage is in fault, UK is the bus voltage, a is the deflection angle of the voltage, α is the unit vector operator ∠ 120 degrees:
Figure DDA0001691793760000011
the action of the composite voltage element caused by the fact that the zero sequence voltage reaches a fixed value is avoided.

Description

Accurate test method for negative sequence element in double-voltage lockout
Technical Field
The invention relates to an accurate test method for a negative sequence element in a double-voltage latch, in particular to an accurate test method for checking an action value of the negative sequence element in the double-voltage latch in bus protection, failure protection and transformer protection with voltage grades of 220kV and below.
Background
In a power system, bus protection, failure protection and transformer protection of 220kV and below voltage classes are carried out, elements on a bus are completely cut off in order to prevent mistaken exit protection, and composite voltage locking realized by bus voltage is introduced. The composite voltage lock is usually composed of a low voltage lock, a complex sequence voltage lock and a zero sequence voltage lock, when the phase voltage of the bus is lower than a low voltage fixed value, the zero sequence voltage is higher than a zero sequence voltage fixed value or the negative sequence voltage is higher than a negative sequence voltage fixed value, the composite voltage element acts to protect the bus and the bus is exported, and the three are in an OR gate relationship. In the debugging of relay protection, fixed values of medium-low voltage, zero sequence voltage and negative sequence voltage of composite voltage locking of bus protection are respectively checked. When negative sequence voltage fixed value inspection is carried out, debugging personnel often adopt bus voltage for simulating bus single-phase grounding to carry out test, zero sequence voltage can be generated during single-phase grounding, and when the zero sequence voltage reaches the zero sequence voltage fixed value, a composite voltage element can also act, so that inconvenience is caused to relay protection debugging.
Disclosure of Invention
In order to solve the technical problems, the invention provides a method for accurately testing a negative sequence element in a complex voltage lockout, which can verify the fixed value of the negative sequence voltage by utilizing a method for simulating a two-phase short circuit fault of a bus and avoid the action of a complex voltage element caused by the fact that the zero sequence voltage reaches the fixed value.
In order to realize the technical test, the invention aims to realize that the invention is a method for accurately testing a negative sequence element in a complex voltage latch, the complex voltage latch comprises a low voltage latch, a negative sequence voltage latch and a zero sequence voltage latch, when the voltage of a bus is lower than the low voltage fixed value of the low voltage latch, the zero sequence voltage is higher than the zero sequence voltage fixed value of the zero sequence voltage latch or the negative sequence voltage is higher than the negative sequence voltage fixed value of the complex sequence voltage latch, the complex voltage element acts, the bus voltage of a non-fault phase is unchanged when two phases are in short circuit, the voltage amplitude of the two phases of the bus of the fault phase is reduced, the angle is also changed, the included angle between the two phases of the voltages is reduced, and the symmetrical relation is kept
Figure GDA0002579285450000011
The three-phase voltages are then as follows:
non-fault bus voltage: u shapeMA=U1+U2=57.7V
Voltage of fault bus: u shapeKB=α2U1+αU2
UKC=αU12U2
Positive sequence voltage phasor:
Figure GDA0002579285450000021
and U1=57.7-U2
Therefore: u shapeKcosa=57.7-1.5U2-------------------①
Negative-sequence voltage phasor:
Figure GDA0002579285450000022
3U2=57.7-2UKcos(60°+a)
UKcos(60°+a)=28.85-1.5U2-----------②
combining the first step and the second step to obtain:
UK(0.5cosa-0.866sina)=28.85-1.5U2
Figure GDA0002579285450000023
28.85-0.75U2-(49.97-1.299U2)tana=28.85-1.5U2
0.75U2=(49.97-1.299U2)tana
Figure GDA0002579285450000024
Figure GDA0002579285450000025
fault phase voltage and deflection angle of
Figure GDA0002579285450000026
Through the steps, the size and the direction of the fault phase bus voltage UK are determined by the size of the negative sequence voltage U2, and when the negative sequence voltage constant value is verified, the action condition of the composite voltage element caused by the fact that the zero sequence voltage reaches the constant value is avoided.
The invention has the advantages that when the locking fixed value of the bus protection negative sequence voltage is checked, the two-phase short circuit fault of the bus is simulated without generating zero sequence voltage, and the action of a zero sequence voltage element is avoided. The protection constant value does not need to be modified in debugging, so that the debugging efficiency is improved, and the accuracy of negative sequence voltage locking constant value inspection is also improved.
Drawings
The invention is further illustrated by the following figures and examples.
FIG. 1 is a view of UMIs the bus voltage U in normalKThe positive sequence voltage phasor diagram is that the busbar voltage at fault, the deflection angle of a is voltage, and α is a unit vector operator which is 1 ∠ 120 degrees.
FIG. 2 shows a UMIs the bus voltage U in normalKThe negative sequence voltage phasor diagram is that the busbar voltage at fault, the deflection angle of a is voltage, and α is unit vector operator 1 ∠ 120 degrees.
FIG. 3 shows that when the specific double-bus differential protection verifies the constant value of the negative sequence element in the double-voltage latch, 1.05U is output2The time tester sets up diagram (one).
FIG. 4 shows that when the constant value of the negative sequence element in the double-bus differential protection verification complex voltage latch is specific, 0.95U is output2The time tester sets up the picture (two).
Detailed Description
Embodiments of the present invention will be further described with reference to the accompanying drawings.
A method for accurately testing a negative sequence element in a complex voltage latch comprises a low voltage latch, a complex sequence voltage latch and a zero sequence voltage latch, wherein when the voltage of a bus is lower than the low voltage fixed value of the low voltage latch, the zero sequence voltage is higher than the zero sequence voltage fixed value of the zero sequence voltage latch or the negative sequence voltage is higher than the negative sequence voltage fixed value of the complex sequence voltage latch, the complex voltage element acts, and when two phases have a short circuit fault, the voltage of the bus of a non-fault phase is unchanged; the amplitude of the two-phase bus voltage of the fault phase is reduced, the angle is changed, the included angle between the two-phase bus voltage is reduced, and the symmetrical relation is kept. The method is characterized in that: if the phase A is a non-fault phase and the phase B and the phase C are in phase-to-phase short circuit, each phase voltage respectively consists of a positive sequence voltage component U by using a symmetrical phasor method1Negative sequence voltage component U2And (5) obtaining the result of the operation. By UMNormal bus voltage, UKFor the busbar voltage at fault, a is the deflection angle of the voltage and α is the unit vector operator, i.e.
Figure GDA0002579285450000031
The three-phase voltages are then as follows:
non-fault bus voltage: u shapeMA=U1+U2=57.7V
Voltage of fault bus: u shapeKB=α2U1+αU2
UKC=αU12U2
Positive sequence voltage phasor:
Figure GDA0002579285450000032
and U1=57.7-U2
Therefore: u shapeKcosa=57.7-1.5U2-------------------①
Negative-sequence voltage phasor:
Figure GDA0002579285450000041
3U2=57.7-2UKcos(60°+a)
UKcos(60°+a)=28.85-1.5U2-----------②
combining the first step and the second step to obtain:
UK(0.5cosa-0.866sina)=28.85-1.5U2
Figure GDA0002579285450000042
28.85-0.75U2-(49.97-1.299U2)tana=28.85-1.5U2
0.75U2=(49.97-1.299U2)tana
Figure GDA0002579285450000043
Figure GDA0002579285450000044
fault phase voltage and deflection angle of
Figure GDA0002579285450000045
Through the steps, the fault phase bus voltage UKIs controlled by a negative sequence voltage U2The magnitude of the zero sequence voltage is determined, and when the negative sequence voltage constant value is verified, the action condition of the composite voltage element caused by the fact that the zero sequence voltage reaches the constant value is avoided.
According to a fault phase voltage and deflection angle formula:
Figure GDA0002579285450000046
suppose that: the fixed value of a negative sequence voltage element in the complex voltage lock is fixed and set to be 4V, and the fixed value verification is carried out by simulating the short circuit of a phase B and a phase C:
1. negative sequence voltage U2 ═ 1.05X 4 ═ 4.2V
a=arctan[(0.75*4.2)/(49.94-1.299*4.2)]=4.05°
UK=(57.7-1.5*4.2)/cos4.05°=51.529V
The bus voltage UA is 57.7-0 ° (V), UB is 51.529-124.05 ° (V), UC is 51.529-124.05 ° (V) and the current introduced into the branch is larger than the differential current constant value as follows (as shown in figure 3):
tester displaying negative sequence voltage UWhen the voltage is larger than a fixed value, 4.2V, the zero-sequence voltage U0 is 0V, and differential protection is performed.
2. Negative sequence voltage U2 ═ 0.95 × 4 ═ 3.8V
a=arctan[(0.75*3.8)/(49.94-1.299*3.8)]=3.62°
UK=(57.7-1.5*3.8)/cos3.62°=52.103V
The bus voltage UA (57.7 ∠ 0 degree) (V), UB (52.103 ∠ -123.62 degree (V) and UC (52.103 ∠ 123.62 degree) (V) are led into a relay protection tester, and the current led into a branch is larger than the fixed value of differential current (as shown in figure 4)When the voltage is less than a fixed value, 3.8V, the zero-sequence voltage U0 is 0V, and the differential protection does not act.
The method for verifying the locking fixed value of the negative sequence voltage of the bus protection by using the method for simulating the two-phase short circuit of the bus is used, the relation between the magnitude and the direction of the three-phase bus voltage can be determined only by giving the magnitude of the negative sequence voltage of the bus, and the core content of the patent of the invention is that the embodiment is only the preferable technical scheme of the patent of the invention, and is not regarded as the limitation of the invention. I.e., equivalent alterations and modifications within the scope hereof, are also intended to be within the scope of the invention.

Claims (1)

1. A method for accurately testing a negative sequence element in a complex voltage latch comprises a low voltage latch, a negative sequence voltage latch and a zero sequence voltage latch, wherein when the voltage of a bus is lower than the low voltage fixed value of the low voltage latch, the zero sequence voltage is higher than the zero sequence voltage fixed value of the zero sequence voltage latch or the negative sequence voltage is higher than the negative sequence voltage fixed value of the negative sequence voltage latch, the complex voltage element acts, and when two phases of short circuit faults occur, the voltage of the bus of a non-fault phase is unchanged; the amplitude of the voltage of the two-phase bus of the fault phase is reduced, the angle is changed, the included angle between the two-phase bus is reduced, and the symmetrical relation is kept, and the method is characterized in that: if the phase A is a non-fault phase and the phase B and the phase C are in phase-to-phase short circuit, each phase voltage respectively consists of a positive sequence voltage component U by using a symmetrical phasor method1Negative sequence voltage component U2Obtained by operation, with UMNormal bus voltage, UKFor the busbar voltage at fault, a is the deflection angle of the voltage and α is the unit vector operator, i.e.
Figure FDA0002613488950000011
The three-phase voltages are then as follows:
non-fault bus voltage: u shapeMA=U1+U2=57.7V
Voltage of fault bus: u shapeKB=α2U1+αU2
UKC=αU12U2
Positive sequence voltage phasor:
Figure FDA0002613488950000012
and U1=57.7-U2
Therefore: u shapeKcosa=57.7-1.5U2-------------------①
Negative-sequence voltage phasor:
Figure FDA0002613488950000013
3U2=57.7-2UKcos(60°+a)
UKcos(60°+a)=28.85-1.5U2-----------②
combining the first step and the second step to obtain:
UK(0.5cosa-0.866sina)=28.85-1.5U2
Figure FDA0002613488950000014
28.85-0.75U2-(49.97-1.299U2)tana=28.85-1.5U2
0.75U2=(49.97-1.299U2)tana
Figure FDA0002613488950000021
Figure FDA0002613488950000022
the fault phase voltage and deflection angle are as follows:
Figure FDA0002613488950000023
through the steps, the fault phase bus voltage UKIs controlled by a negative sequence voltage U2The magnitude of the zero sequence voltage is determined, and when the negative sequence voltage constant value is verified, the action condition of the composite voltage element caused by the fact that the zero sequence voltage reaches the constant value is avoided.
CN201810594705.9A 2018-06-11 2018-06-11 Accurate test method for negative sequence element in double-voltage lockout Expired - Fee Related CN108872768B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810594705.9A CN108872768B (en) 2018-06-11 2018-06-11 Accurate test method for negative sequence element in double-voltage lockout

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810594705.9A CN108872768B (en) 2018-06-11 2018-06-11 Accurate test method for negative sequence element in double-voltage lockout

Publications (2)

Publication Number Publication Date
CN108872768A CN108872768A (en) 2018-11-23
CN108872768B true CN108872768B (en) 2020-09-22

Family

ID=64337699

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810594705.9A Expired - Fee Related CN108872768B (en) 2018-06-11 2018-06-11 Accurate test method for negative sequence element in double-voltage lockout

Country Status (1)

Country Link
CN (1) CN108872768B (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104092201A (en) * 2014-07-25 2014-10-08 国家电网公司 Remote ultra-high voltage alternating-current transmission line fault determination method
CN107086549A (en) * 2017-05-22 2017-08-22 华北电力大学 The segment protection method of distance I of UPFC line attachment single-phase grounding faults

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2126195C1 (en) * 1997-07-29 1999-02-10 Научно-технический центр Всероссийского электротехнического института им.В.И.Ленина Internal short circuit protective device for controlled reactor
DE102014219235B4 (en) * 2014-09-24 2018-06-07 Conti Temic Microelectronic Gmbh Circuit apparatus and method for determining a condition of a lock conductor loop
CN104362599B (en) * 2014-11-13 2017-02-15 国家电网公司 Method for protecting low-voltage bus of intelligent substation
CN105301369B (en) * 2015-10-20 2017-12-26 国家电网公司 A kind of bus protection compound voltage lockout function test method
CN106169740B (en) * 2016-08-29 2018-08-31 国网江苏省电力公司镇江供电公司 110kV single-trunk segmental wiring incoming relay-protections are latched prepared auto restart relay protecting method
CN107918096A (en) * 2017-11-13 2018-04-17 鞍钢股份有限公司 Outlet wire protecting device test method is routinely matched somebody with somebody by a kind of substation

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104092201A (en) * 2014-07-25 2014-10-08 国家电网公司 Remote ultra-high voltage alternating-current transmission line fault determination method
CN107086549A (en) * 2017-05-22 2017-08-22 华北电力大学 The segment protection method of distance I of UPFC line attachment single-phase grounding faults

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
距离保护在测试过程中测试仪输出电流、电压分析;赵朗;《华电技术》;20130131;第35卷(第1期);31-33 *

Also Published As

Publication number Publication date
CN108872768A (en) 2018-11-23

Similar Documents

Publication Publication Date Title
Chowdhury et al. Transmission line protection for systems with inverter-based resources–Part I: Problems
Hooshyar et al. A new directional element for microgrid protection
Hooshyar et al. Fault type classification in microgrids including photovoltaic DGs
Zheng et al. Cosine similarity based line protection for large-scale wind farms
Gao et al. Design and evaluation of a directional algorithm for transmission-line protection based on positive-sequence fault components
Banaiemoqadam et al. A comprehensive dual current control scheme for inverter-based resources to enable correct operation of protective relays
CN105119270B (en) Analysis method for influence of scale wind power access on longitudinal direction protection
CN104535956A (en) Method for detecting wiring/polarity correctness of secondary opening delta loop of potential transformer
CN109286202B (en) Large-scale inversion type power supply grid-connected tie line current differential protection method, device and system
Liang et al. Effect of inverter-interfaced renewable energy power plants on negative-sequence directional relays and a solution
CN105301369B (en) A kind of bus protection compound voltage lockout function test method
CN108872768B (en) Accurate test method for negative sequence element in double-voltage lockout
Patel et al. On-line load test for induction machine stator inter-turn fault detection under stator electrical asymmetries
Mobashsher et al. A new fault type classification method in the presence of inverter-based resources
Behnke et al. Contribution of photovoltaic power generation systems to AC short circuits—A survey of current modeling practices and challenges
Dawood et al. Fuzzy logic based scheme for directional earth fault detection and classification
Benmouyal et al. Field experience with a digital relay for synchronous generators
Kim et al. Islanding detection method with negative-sequence current injection under unbalanced grid voltage
Kim A case study of calculating the short-circuit current of high-capacity power electronics-based distributed energy resources and loads
Wang et al. A novel directional element for transmission line connecting inverter-interfaced renewable energy power plant
Kariyawasam et al. A Negative Sequence Admittance Based Algorithm for Identifying Fault Direction in the Presence of Inverter Based Resources
Bagheri et al. Characterizing three-phase unbalanced dips through the ellipse parameters of the space phasor model
Aboelnaga et al. Dual stationary frame control of inverter-based resources for reliable phase selection
Si et al. Reactive power injection and SOGI based active anti-islanding protection method
Alvidrez et al. PV-Inverter Dynamic Model Validation and Comparison Under Fault Scenarios Using a Power Hardware-in-the-Loop Testbed.

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20200922

CF01 Termination of patent right due to non-payment of annual fee