CN108848006B

CN108848006B - Port state monitoring method and device

Info

Publication number: CN108848006B
Application number: CN201810975321.1A
Authority: CN
Inventors: 李绍军; 刘小兵
Original assignee: Hangzhou DPTech Technologies Co Ltd
Current assignee: Hangzhou DPTech Technologies Co Ltd
Priority date: 2018-08-24
Filing date: 2018-08-24
Publication date: 2020-11-06
Anticipated expiration: 2038-08-24
Also published as: CN108848006A

Abstract

The utility model provides a monitoring method of port state is applied to network equipment, the network equipment is provided with FPGA, the FPGA is connected with CPU and PHY chip of the network equipment, the method comprises: the FPGA receives the configuration of a port to be monitored of the CPU, and acquires the information of the port to be monitored from the configuration, wherein the port to be monitored is managed by the PHY chip; receiving a port monitoring trigger enabling instruction of the CPU, inquiring the PHY chip according to a preset polling strategy based on the information of the port to be monitored, and acquiring the port state of the port to be monitored; and saving the port state to a DMA memory address appointed by the CPU.

Description

Port state monitoring method and device

Technical Field

The present application relates to the field of communications technologies, and in particular, to a method and an apparatus for monitoring a port state.

Background

With the continuous development of IT (Information Technology) industry, the number of computers accessing the internet is increasing, so that switches with more port density are required to meet the port access number and bandwidth. When the switch forwards the traffic, the state of the data forwarding port must be periodically detected to update the related routing information and the related table entry, thereby ensuring normal traffic forwarding.

Information such as port state is usually stored in a register of a PHY chip on a switch, and needs to be acquired by a CPU through an MDIO bus. In practical application, a lot of services need to be uploaded to a CPU for processing, and due to the comprehensive influence of factors such as the complexity of network topology and port monitoring through a system software mechanism, the problem of high CPU load exists with a high probability when monitoring the port state through CPU execution. How to effectively reduce the load of a CPU and improve the stability of equipment is very necessary.

Disclosure of Invention

In view of the above, the present application provides a method and an apparatus for monitoring a port state, so as to solve the problem that a CPU load is high with a high probability in an original scenario that a CPU is required to perform monitoring of a port state.

Specifically, the method is realized through the following technical scheme:

in a first aspect of the present disclosure, a method for monitoring a port state is applied to a network device, where the network device is provided with an FPGA, and the FPGA is connected to a CPU and a PHY chip of the network device, and the method includes: the FPGA receives the configuration of a port to be monitored of the CPU, and acquires the information of the port to be monitored from the configuration, wherein the port to be monitored is managed by the PHY chip; receiving a port monitoring trigger enabling instruction of the CPU, inquiring the PHY chip according to a preset polling strategy based on the information of the port to be monitored, and acquiring the port state of the port to be monitored; and saving the port state to a DMA memory address appointed by the CPU.

With reference to the first aspect, in a first possible implementation manner, after the FPGA stores the port state to the DMA memory address specified by the CPU, the method further includes: and judging based on the current state of the port to be monitored compared with the saved previous state, if the current state of the port to be monitored is changed, sending an interrupt request to a CPU (Central processing Unit) for triggering the CPU to search and read the port state from the DMA memory address of the finger.

With reference to the first aspect, in a second possible implementation manner, the method further includes: and the FPGA receives a locking enabling instruction of the CPU aiming at the port to be monitored, and then stops inquiring the port to be monitored.

With reference to the first aspect, in a third possible implementation manner, the FPGA is connected to the PHY chip based on an MDIO bus, and the FPGA is connected to the CPU based on a PCI-E bus.

In a second aspect of the present disclosure, a device for monitoring a port state is provided, where the device is applied to a network device, the network device is provided with an FPGA, the FPGA is connected to a CPU and a PHY chip of the network device, and the device includes:

the configuration module is used for receiving the configuration of the port to be monitored of the CPU by the FPGA and acquiring the information of the port to be monitored from the configuration, wherein the port to be monitored is managed by the PHY chip; the FPGA is used for receiving a port monitoring trigger enabling instruction of the CPU;

the monitoring module is used for the FPGA to inquire the PHY chip according to a preset polling strategy based on the information of the port to be monitored so as to acquire the port state of the port to be monitored; and saving the port state to a DMA memory address appointed by the CPU.

With reference to the second aspect, in a first possible implementation manner, after the FPGA stores the port state to the DMA memory address specified by the CPU, the method further includes: and the monitoring module is used for judging whether the current state of the port to be monitored is compared with the saved previous state by the FPGA based on the current state of the port to be monitored, if so, sending an interrupt request to the CPU, and triggering the CPU to search and read the port state from the DMA memory address of the finger.

With reference to the second aspect, in a second possible implementation manner, the method further includes: and the configuration module receives a locking enabling instruction of the CPU aiming at the port to be monitored, and stops querying the port to be monitored.

With reference to the second aspect, in a third possible implementation manner, the FPGA is connected to the PHY chip based on an MDIO bus, and the FPGA is connected to the CPU based on a PCI-E bus.

In a third aspect of the present disclosure, a data processing apparatus is provided, including a communication interface, a processor, an FPGA, a PHY chip, a memory, and a bus, where the communication interface, the processor, the FPGA, the PHY chip, and the memory are connected to each other through the bus, the FPGA is connected to the PHY chip based on an MDIO bus, and the FPGA is connected to a CPU based on a PCI-E bus. The memory stores machine-readable instructions, and the processor executes the aforementioned method by calling the machine-readable instructions.

In a fourth aspect of the present disclosure, there is provided a machine-readable storage medium having stored thereon machine-executable instructions which, when invoked and executed by a processor, cause the processor to carry out the method of the first aspect of the present disclosure.

The present disclosure provides a method for monitoring a port state, which is applied to a network device, where the network device is provided with an FPGA, and the FPGA is connected to a CPU and a PHY chip of the network device, and the method includes: the FPGA receives the configuration of a port to be monitored of the CPU, and acquires the information of the port to be monitored from the configuration, wherein the port to be monitored is managed by the PHY chip; receiving a port monitoring trigger enabling instruction of the CPU, inquiring the PHY chip according to a preset polling strategy based on the information of the port to be monitored, and acquiring the port state of the port to be monitored; and saving the port state to a DMA memory address appointed by the CPU. By applying the embodiment of the disclosure, the problem that the CPU load is higher at a higher probability in the original scene that the CPU is required to execute monitoring of the port state can be solved, the CPU load is reduced, and the port state monitoring efficiency is improved.

Drawings

FIG. 1 is a schematic diagram of a system configuration provided by an embodiment of the present disclosure;

fig. 2 is a flowchart of a port status monitoring method provided by an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of an interaction process of port status monitoring provided by an embodiment of the present disclosure;

FIG. 4 is a block diagram of functional blocks of an apparatus provided by the present disclosure;

fig. 5 is a hardware block diagram of the apparatus shown in fig. 4 provided by the present disclosure.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.

In order to make those skilled in the art better understand the technical solutions in the embodiments of the present disclosure, a brief description will be given below of the system components to which the embodiments of the present disclosure are applicable.

Please refer to the system composition illustrated in fig. 1, which includes a CPU, an FPGA, and a plurality of PHY chips, wherein the CPU communicates with the FPGA via a PCIE bus, the PHY chips communicate with the FPGA via an MDIO bus, and each PHY chip has a plurality of ports.

An fpga (field Programmable Gate array), i.e. a field Programmable Gate array chip, shown in fig. 1 is a product developed further on the basis of Programmable devices such as PAL (Programmable array logic), GAL (Programmable logic array), CPLD (complex Programmable logic device), etc. The circuit is used as a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC), not only overcomes the defects of the custom circuit, but also overcomes the defect that the number of gate circuits of the original programmable device is limited. The FPGA can be understood as a large number of logic gate arrays, and a user can freely and flexibly implement different circuit functions, i.e. programmable characteristics of the FPGA, through a circuit design completed by a hardware description language (Verilog or VHDL). Compared with general processors such as a CPU (central processing unit) and a GPU (graphic processing unit) with a Von Neumann structure, the FPGA has the advantages of higher efficiency and higher speed; compared with a dedicated ASIC for full time, the FPGA has the advantages of small development difficulty and shorter development period, and is more suitable for the technical field of communication with complicated and various protocols. As shown in fig. 1, the FPGA and the CPU communicate via a PCIE bus, where the PCIE (peripheral component interconnect express) bus is a high-speed serial computer expansion bus. PCIE supports functions such as hot plug and quality of service (QOS), allocates an independent channel bandwidth to devices connected thereto, and can provide serial point-to-point, dual channel, high bandwidth, high speed, reliable data transmission between devices.

As shown in fig. 1, the FPGA communicates with PHY chips, each having multiple ports, via an MDIO bus. PHY (port Physical layer), which is the Physical layer, is located at the lowest layer of the osi (open System interconnection) open communication System interconnection reference model, and this layer defines the electrical signals, the line status, the clock requirement, the port status, the data encoding and the data transmission connector, and integrates the chip with the above Physical layer functions, which is called PHY chip. A PHY chip may have multiple ports, where each port is a port in a corresponding network device. Typically, a PHY chip includes two types of buses: one is a data bus, namely MII, and other equipment acquires data from the PHY chip through the MII bus; the other type is Management bus, namely MDIO (Management Data Input/Output), which is a Management interface of MII bus and can access the register on the PHY chip through a simple two-wire serial interface protocol, wherein the purpose of the register comprises the storage of the configuration and the port state of the PHY chip. The port state includes at least: and up and down, wherein the up state marks that the link connection between the port and the external network port is established by negotiation, and the down state is otherwise.

In the prior art, information such as port status is usually stored in a register of a PHY chip on a switch, and a CPU is required to obtain the information through an MDIO bus. In practical application, a lot of services need to be uploaded to a CPU for processing, and due to the comprehensive influence of factors such as the complexity of network topology and port monitoring through a system software mechanism, the number of ports of switches is increasing, so that a problem of high CPU load exists at a high probability when monitoring the port state through CPU execution.

The port state monitoring method is applied to network equipment, the network equipment is provided with an FPGA, and the FPGA is connected with a CPU and a PHY chip of the network equipment. In order to implement the method provided by the present disclosure, the technical solution in the embodiments of the present disclosure is further described in detail below with reference to the accompanying drawings. Referring to fig. 2, a flow chart of a method for allocating communication ports provided by the present disclosure may include the following steps:

step 201, the FPGA receives the configuration of the port to be monitored of the CPU, and acquires the information of the port to be monitored from the configuration, where the port to be monitored is managed by the PHY chip.

202, receiving a port monitoring trigger enabling instruction of the CPU by the FPGA, querying the PHY chip according to a preset polling strategy based on the port information to be monitored, and acquiring a port state of the port to be monitored.

And 203, the FPGA stores the port state to the DMA memory address appointed by the CPU.

Thus, the flow shown in fig. 2 is completed.

As can be seen from the process shown in fig. 2, the FPGA receives the configuration of the port to be monitored of the CPU, and acquires the information of the port to be monitored from the configuration, where the port to be monitored is managed by the PHY chip; receiving a port monitoring trigger enabling instruction of the CPU, inquiring the PHY chip according to a preset polling strategy based on the information of the port to be monitored, and acquiring the port state of the port to be monitored; and saving the port state to a DMA memory address appointed by the CPU. By applying the embodiment of the disclosure, the problem that the CPU load is higher at a higher probability in the original scene that the CPU is required to execute monitoring of the port state can be solved, the CPU load is reduced, and the port state monitoring efficiency is improved.

More specifically, when the CPU needs to monitor the states of the plurality of ports corresponding to the plurality of PHY chips, the states of the plurality of ports do not need to be obtained through frequent inquiry, but the states of the plurality of ports are monitored and obtained through configuration of the FPGA and control thereof according to a policy.

In order to make those skilled in the art better understand the technical solutions provided by the embodiments of the present disclosure, the following describes the technical solutions provided by the embodiments of the present disclosure with reference to specific application scenarios. Please refer to fig. 3, which is a schematic diagram illustrating an interaction process of port status monitoring according to an embodiment of the present disclosure.

As shown in fig. 1, there are three PHY chips PHY1, PHY2, and PHY3, which respectively manage 3, 2, and 3 ports, and the FPGA and the three PHY chips communicate via three MDIO buses, that is, MDIO1, MDIO2, and MDIO 3.

The FPGA on the network equipment has the following initial configuration and register format definition:

1) a reg _ data register, which is a 32-bit register, configured to store data information in the port configuration information to be monitored, which is received by the FPGA from the CPU, where the data information is defined as follows according to a negotiation format of the CPU and the FPGA, please refer to an example in table 1:

port_id	phy_addr	dev_addr	bus	st
					[0～7]bit	[8～15]bit	[16～23]bit	[24～30]bit	[31]bit

TABLE 1

Wherein the above register definitions are explained as follows:

the port _ id is an identifier of a certain port to be monitored, and occupies 8 bits, namely [ 0-7 ] bit of 32 bits;

the PHY _ addr is the address of the PHY chip where the port is located, and occupies 8 bits, namely [ 8-15 ] bit of the 32 bits;

dev _ addr is an address of an indirect address register, wherein the indirect address register is used by the PHY chip when the PHY chip communicates according to a C45 protocol, and does not need to occupy 8 bits when the PHY chip communicates according to a C22 protocol, namely [ 16-23 ] bit of the 32 bits; the C45 protocol refers to the communication protocol type of the MDIO bus, and comprises two types, namely C22 and C45, wherein the main difference between C45 and C22 is that under the C45 protocol, MDIO data access has one more register parameter than C22, namely the indirect address register;

the bus is a bus address where the PHY chip is located, and occupies 7 bits, namely [ 24-30 ] bit of 32 bits; referring to the example shown in fig. 1, there are three PHY chips PHY1, PHY2, and PHY3, and the bus is used to identify the address differences of the three PHY chips for the subsequent FPGA to select different PHY chips, such as: PHY1 is 0x10 for bus, PHY2 is 0x20 for bus, and PHY3 is 0x30 for bus;

st is the communication protocol type selection of the PHY chip, namely C22 or C45, and occupies 1bit, namely [31] bit of 32 bits; wherein if the mode is C22, the bit is 0, if the mode is C45, the bit is 1; when in the C22 mode, the dev _ addr indirect address register address content is invalid, and when in the C45 mode, the dev _ addr indirect address register address content is valid;

when the actual port monitoring configuration is carried out, each port to be monitored is correspondingly configured with a reg _ data register.

2) And the reg _ address register is a 16-bit register and is used for storing address information in the port configuration information to be monitored, which is received by the FPGA from the CPU, wherein the address information is a register address in which a port state is stored on the PHY chip. Through the address information, the FPGA issues one or more port status query instructions on one or more PHY chips (as shown in fig. 1) according to the data format of the reg _ data register, where each port to be monitored is configured with a reg _ address register.

3) An FPGA _ port _ status register, which is a 32-bit register, configured to store a port status of a corresponding port to be monitored, which is obtained from the PHY chip by the FPGA, where a format of the register is defined as follows, please refer to the example in table 2:

port_id	phy_addr	bus	port_status
				[0～7]bit	[8～15]bit	[16～22]bit	[23～31]bit

TABLE 2

Wherein the above register definitions are explained as follows:

the bus is a bus address where the PHY chip is located, and occupies 7 bits, namely [ 16-22 ] bit of 32 bits; referring to the example shown in fig. 1, there are three PHY chips PHY1, PHY2, and PHY3, and the bus is used to identify address differences of the three PHY chips for the subsequent FPGA to select different PHY chips;

port _ status is port state information of the port, and occupies 9 bits, namely [ 23-31 ] bit of 32 bits; wherein the port state information includes at least: up and down, wherein the up state marks that the link connection between the port and the external network port is established by negotiation, otherwise, the down state marks a 31 th bit, wherein if up, the bit is 1, and if down, the bit is 0; other information may also be included and not limited to, such as: the port rate negotiation is 100M, the duplex state is full duplex, and the like, and the 23 rd to 30 th bit identifier is used, and the method can be defined by port up/down, and details are not repeated. When the actual port monitoring is configured, each port to be monitored is correspondingly configured with a port _ status register.

Based on the above configuration, the CPU communicates with the FPGA through the PCIE bus, the FPGA communicates with the PHY chip through the MDIO bus, the FPGA monitors the state of the management port corresponding to the PHY chip, and can perform the port monitoring interaction process shown in fig. 3:

step S301, issuing register configuration and initializing the FPGA, wherein the steps comprise:

referring to the example shown in fig. 1, the CPU monitors the ports managed by the three PHY chips PHY1, PHY2, and PHY3, such as: PORT1 of PHY 1; PORT2 of PHY 2; PORT1 of PHY 3.

For each port to be monitored, the CPU issues two register configurations, namely a reg _ data register and a reg _ address register, wherein the detailed format definition and the purpose of the registers can be referred to the FPGA initial configuration specification.

Step S302, receiving register configuration, analyzing the configuration according to a negotiation format, and acquiring information of a port to be monitored, wherein the method comprises the following steps:

for each port to be monitored, the FPGA receives register configuration, wherein the register configuration comprises two register configurations, namely a reg _ data register and a reg _ address register.

And the FPGA defines and analyzes the configuration in detail according to the format of the register to acquire the port information to be monitored.

The port information to be monitored specifically includes: port _ id, phy _ addr, dev _ addr, bus, st, reg _ address, see table 3 for examples:

port_id

phy_addr

dev_addr

bus

st

reg_address

0x01

0xFF

0x10

0

0xFFEA

0x02

0x7A

0x20

1

0xFFEB

0x01

0x03

0xFF

0x30

0

0xFFEC

TABLE 3

Through the first record in table 3, according to the initial configuration bus 0x10 corresponding to the PHY1 chip, the PORT information of the PORT1 that the FPGA can obtain the PHY1 corresponds to:

port_id＝0x01、phy_addr＝0x01、dev_addr＝0xFF、bus＝0x10、st＝0、reg_address＝0xFFEA

by analyzing the PORT information of the PORT1 of the PHY1, if st is 0, the PHY chip is identified to follow the C22 protocol of MDIO, and its dev _ addr information is useless. Based on this information, the FPGA subsequently communicates with the PHY1 via the MDIO bus in the C22 protocol.

Similarly, according to the example shown in table 3, the PORT information of PORT2 that the FPGA can obtain the PHY2 corresponds to:

port_id＝0x02、phy_addr＝0x02、dev_addr＝0x7A、bus＝0x20、st＝1、reg_address＝0xFFEB

by analyzing the PORT information of the PORT2 of the PHY2, the dev _ addr ═ 0x7A information is valid. Based on this information, the FPGA subsequently communicates with the PHY2 via the MDIO bus in the C45 protocol.

Similarly, according to the example shown in table 3, the PORT information of PORT1 that the FPGA can obtain the PHY3 corresponds to:

port_id＝0x01、phy_addr＝0x03、dev_addr＝0xFF、bus＝0x30、st＝0、reg_address＝0xFFEC

by analyzing the PORT information of the PORT1 of the PHY3, if st is 0, the PHY chip is identified to follow the C22 protocol of MDIO, and its dev _ addr information is useless. Based on this information, the FPGA subsequently communicates with the PHY3 via the MDIO bus in the C22 protocol.

Step S303, issuing a port monitoring trigger enable instruction, including:

and the CPU issues a port monitoring trigger enabling instruction to the FPGA, and the FPGA triggers port monitoring query after receiving the port monitoring trigger enabling instruction.

Step S304, based on the port information to be monitored, querying the PHY chip according to a preset polling strategy, including:

based on the port information to be monitored acquired in step S302, after receiving the port monitoring trigger enable instruction of step S303, the FPGA queries according to the following method:

a) determining an access address port _ address of the port to be monitored through the bus, the PHY address PHY _ address, and the port identification port _ id, where the access address port _ address is port _ id, PHY _ address, and bus bit-by-bit combination, i.e. port _ id | PHY _ address | bus, such as: referring to table 3, PORT _ address value of PORT1 of PHY1 is 0x 010110;

b) based on the reg _ address, determining that the port to be monitored corresponds to the PHY chip and has the register address PHY _ port _ reg _ address of the port state, that is, the value of PHY _ port _ reg _ address is reg _ address, for example: referring to table 3, the PHY _ PORT _ reg _ address value of PORT1 of PHY1 is 0 xffie;

c) based on the value of the port information st to be monitored acquired in step S302, which may be C22 or C45, it is determined that when the register of the port status is queried, it corresponds to the MDIO protocol type.

Such as: referring to table 3, the FPGA communicates with the PHY1 via MDIO bus in C22 protocol; the FPGA and the PHY2 communicate according to a C45 protocol through an MDIO bus; the FPGA communicates with the PHY3 via an MDIO bus according to the C22 protocol.

d) Based on the port _ address, the phy _ port _ reg _ address and the MDIO protocol type, the FPGA performs MDIO read operation to query and acquire a state value phy _ port _ status of the register, where the state value at least includes: up and down, wherein the up state identifies that the link connection between the port and the external network port is established by negotiation, otherwise, the up state is the down state; other information may also be included and not limited to, such as: the port rate negotiation is 100M, the duplex state is full duplex, and the like, and the 23 rd to 30 th bit identifier is used, and the method can be defined by port up/down, and details are not repeated.

e) The FPGA performs a plurality of ports to be monitored according to the method in the step d) and a preset polling strategy, such as: according to a certain period, the threshold value is 500ms for inquiry.

In another scenario, for example, the CPU needs to directly access the port state of a port on a certain PHY chip, and since the FPGA is performing port state polling through the MDIO bus at this time, the MDIO bus corresponding to the PHY is occupied by the FPGA, and the CPU cannot be used at this time. One preferred implementation is: the CPU sends a locking enabling instruction aiming at the port to be monitored of the PHY chip to the FPGA, the FPGA stops inquiring the port to be monitored on the PHY chip after receiving the locking enabling instruction, an MDIO bus of the FPGA is idle, and the CPU can directly access the port state on the PHY chip at the moment.

Step S305, acquiring a port state of the port to be monitored, including:

and the FPGA acquires the state value PHY _ port _ status of the register corresponding to the port to be monitored from the PHY chip.

For example, if the value of PHY _ PORT _ status of PORT1 of PHY1 obtained by the FPGA is 1, it identifies that the current PORT state of the PORT is up, that is, the link connection between the PORT and the external network PORT has been successfully established through negotiation. Similarly, for example, the FPGA obtains the value of 0 for PHY _ PORT _ status of PORT2 of PHY 2; the FPGA obtains a value of 0 for the PHY _ PORT _ status of PORT1 of PHY 3.

The FPGA acquires the port states of the ports to be monitored corresponding to the three PHY chips, and stores the port states in the FPGA _ port _ status registers corresponding to the ports to be monitored, for detailed definitions of the port states, see the FPGA _ port _ status register format definition in the FPGA initial configuration. Taking port state up/down as an example, the port states of the ports to be monitored corresponding to the three PHY chips, which correspond to three fpga _ port _ status, are obtained, as shown in table 4:

TABLE 4

Step S306, saving the port state to the DMA memory address specified by the CPU, including:

the FPGA stores the obtained FPGA _ port _ status information corresponding to each port in step S305 to the DMA memory address specified by the CPU, that is, 32-bit information corresponding to each port state, where the DMA memory address is applied by the CPU for the FPGA in advance and is configured for the FPGA in advance. The FPGA writes or reads the phy _ port _ status information at the address in a DMA (Direct Memory Access) manner.

Step S307, checking whether the port state changes, if so, reporting an interrupt to the CPU, and the method comprises the following steps:

and the FPGA performs port state polling according to the methods from the step S304 to the step S306, acquires the current state of the port, acquires the last port state in the DMA memory address corresponding to the port, and compares whether the port state and the last port state are changed.

For example, if the PORT1 of the PHY1 was last up and the current state was down, it is determined that the PORT has changed state, the PORT state of the PORT in the DMA memory address is updated to be down, and an interrupt is reported to the CPU, where the interrupt includes the PORT _ id of the PORT.

In a preferred implementation, the FPGA periodically thresholds, such as: and 1 second, the states of a plurality of ports are collected, and an interrupt is triggered by reporting, so that the communication efficiency can be improved.

Step S308, after receiving the interrupt, the CPU obtains the port status by using the specified DMA memory address, which includes:

after receiving the interrupt, the CPU queries and acquires the state of the port from the DMA memory address in step S307 according to the port _ id included in the DMA memory address. For example, the CPU obtains the PORT state of the PORT1 of the PHY1 as down from the DMA memory address for the interrupt information of the PORT1 of the PHY1 through the FPGA.

Based on the steps, the monitoring of the port state of the PHY chip is realized by adding the FPGA, expanding the MDIO bus, communicating according to the preset register format and protocol, and through the interruption and DMA memory sharing access mode, so that the problems of large port number and high load caused by frequent rotation of the CPU in the original scene of needing the CPU to execute the port state monitoring can be realized, the CPU load is reduced, and the port state monitoring efficiency is improved.

The methods provided by the present disclosure are described above. The following describes the apparatus provided by the present disclosure.

Referring to fig. 4, for the monitoring apparatus for port status provided by the present disclosure, the apparatus is applied to a network device, the network device is provided with an FPGA, the FPGA is connected to a CPU and a PHY chip of the network device, and the apparatus includes:

In one embodiment, after the FPGA saves the port state to the DMA memory address specified by the CPU, the method further includes: and the monitoring module is used for judging whether the current state of the port to be monitored is compared with the saved previous state by the FPGA based on the current state of the port to be monitored, if so, sending an interrupt request to the CPU, and triggering the CPU to search and read the port state from the DMA memory address of the finger.

In one embodiment, the method further comprises the following steps: and the configuration module receives a locking enabling instruction of the CPU aiming at the port to be monitored, and stops querying the port to be monitored.

In one embodiment, the FPGA is connected to the PHY chip based on an MDIO bus, and the FPGA is connected to the CPU based on a PCI-E bus.

The description of the apparatus shown in fig. 4 is thus completed.

Correspondingly, the present disclosure also provides a hardware structure of a network device of the apparatus shown in fig. 4, referring to fig. 5, and fig. 5 is a schematic diagram of a hardware structure of a network device provided by the present disclosure. The apparatus comprises: a communication interface 501, a processor 502, an FPGA506, a PHY507, a machine-readable storage medium 503, and a bus 505; the FPGA506 communicates with the processor 502 through a PCIE bus, the FPGA506 communicates with the PHY507 through an MDIO bus, and the communication interface 501, the processor 502, and the machine-readable storage medium 503 complete communication with each other through a bus 505.

The communication interface 501 is used for sending and receiving messages. The processor 502 may be a Central Processing Unit (CPU), and the processor 502 and the FPGA506 may execute machine-readable instructions stored in the machine-readable storage medium 503 to implement the method shown in fig. 2 and described above.

The machine-readable storage medium 503 referred to herein may be any electronic, magnetic, optical, or other physical storage device that can contain or store information such as executable instructions, data, and the like. For example, the machine-readable storage medium may be: volatile memory, non-volatile memory, or similar storage media. In particular, the machine-readable storage medium 503 may be a RAM (random Access Memory), a flash Memory, a storage drive (e.g., a hard disk drive), a solid state disk, any type of storage disk (e.g., a compact disk, a DVD, etc.), or similar storage medium, or a combination thereof.

To this end, the description of the hardware configuration shown in fig. 5 is completed.

Furthermore, the present application also provides a machine-readable storage medium, such as the machine-readable storage medium 503 in fig. 5, including machine executable instructions, which can be executed by the processor 501 and the FPGA506 in the data processing apparatus to implement the data processing method described above.

The implementation process of the functions and actions of each unit in the above device is specifically described in the implementation process of the corresponding step in the above method, and is not described herein again.

The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.

Claims

1. The method for monitoring the port state is characterized in that the method is applied to network equipment, the network equipment is provided with an FPGA, the FPGA is connected with a PHY chip of the network equipment based on an MDIO bus, and is connected with a CPU of the network equipment based on a PCI-E bus; the method comprises the following steps:

the FPGA receives the configuration of a port to be monitored of the CPU, and acquires the information of the port to be monitored from the configuration, wherein the port to be monitored is managed by the PHY chip;

the FPGA receives a port monitoring trigger enabling instruction of the CPU, and queries the PHY chip according to a preset polling strategy based on the information of the port to be monitored to acquire the port state of the port to be monitored;

and the FPGA stores the port state to a DMA memory address appointed by the CPU.

2. The method of claim 1, further comprising, after the FPGA saving the port state to the DMA memory address specified by the CPU:

and judging based on the current state of the port to be monitored compared with the saved previous state, if the current state of the port to be monitored is changed, sending an interrupt request to a CPU (Central processing Unit) for triggering the CPU to search and read the port state from the specified DMA memory address.

3. The method of claim 1, further comprising:

and the FPGA receives a locking enabling instruction of the CPU aiming at the port to be monitored, and then stops inquiring the port to be monitored.

4. The device for monitoring the port state is characterized in that the device is applied to network equipment, the network equipment is provided with an FPGA, the FPGA is connected with a PHY chip of the network equipment based on an MDIO bus, and is connected with a CPU of the network equipment based on a PCI-E bus; the device comprises:

5. The apparatus of claim 4, further comprising, after the FPGA saves the port state to the DMA memory address specified by the CPU:

and the monitoring module is used for judging whether the current state of the port to be monitored is larger than the previous state stored by the FPGA, if so, sending an interrupt request to the CPU for triggering the CPU to search and read the port state from the specified DMA memory address.

6. The apparatus of claim 4, further comprising:

and the configuration module receives a locking enabling instruction of the CPU aiming at the port to be monitored, and stops querying the port to be monitored.

7. A data processing device is characterized by comprising a communication interface, a processor, an FPGA, a PHY chip, a memory and a bus, wherein the communication interface, the processor, the FPGA, the PHY chip and the memory are mutually connected through the bus, the FPGA is connected with the PHY chip based on an MDIO bus, and the FPGA is connected with a CPU based on a PCI-E bus;

the memory stores machine readable instructions, and the processor and the FPGA execute the method according to any one of claims 1 to 3 by calling the machine readable instructions.

8. A machine readable storage medium having stored thereon machine readable instructions which, when invoked and executed by a processor, cause the processor to carry out the method of any of claims 1 to 3.