CN108829618B - High-speed data real-time exchange processing device - Google Patents
High-speed data real-time exchange processing device Download PDFInfo
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- CN108829618B CN108829618B CN201811076252.7A CN201811076252A CN108829618B CN 108829618 B CN108829618 B CN 108829618B CN 201811076252 A CN201811076252 A CN 201811076252A CN 108829618 B CN108829618 B CN 108829618B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
Abstract
The invention discloses a high-speed data real-time exchange processing device which comprises a data acquisition and analysis module, an input buffer module, a signal conflict processing module, an intermediate buffer module and an output buffer module, wherein the data acquisition and analysis module is respectively connected with the input buffer module and the signal conflict processing module, the input buffer module is respectively connected with a first control switch, the intermediate buffer module, a second control switch and the output buffer module, the output buffer module is connected with a processor bus, and the signal conflict processing module is respectively connected with the first control switch and the second control switch. Compared with the prior art, the method has the advantages that in the real-time control occasion in the high-speed data acquisition application, the real-time algorithm can acquire the high-speed acquired data quickly, accurately and without omission, the data interaction method is simple, efficient and flexible, quick and real-time data transmission can be realized, and the system performance is not influenced.
Description
Technical Field
The invention relates to the technical field of signal acquisition and exchange, in particular to a high-speed data real-time exchange processing device.
Background
In high-speed data acquisition application, a general data transmission system has data blocking and low speed, and particularly in some real-time control occasions, a real-time algorithm needs to acquire data quickly, and the requirements cannot be met by adopting interrupt or inquiry modes and the like, and a reading interface is generally needed.
Disclosure of Invention
In order to solve the above-mentioned drawbacks, the present invention aims to provide a high-speed data real-time exchange processing device, which can realize flexible and rapid real-time data transmission without affecting the system performance, and solve the data exchange problem in the occasion requiring high real-time performance.
In order to achieve the above purpose, the invention adopts the following technical scheme: the high-speed Data real-time exchange processing device comprises a Data acquisition analysis module, an input buffer module, a signal conflict processing module, an intermediate buffer module and an output buffer module, wherein the Data acquisition analysis module is respectively connected with the input buffer module and the signal conflict processing module, the input buffer module is respectively connected with a first control switch, the intermediate buffer module, a second control switch and the output buffer module, the output buffer module is connected with a processor bus, the output buffer module transmits Data signals to the processor bus, the signal conflict processing module is respectively connected with the first control switch and the second control switch, and the signal conflict processing module and the processor bus are communicated with each other by reading signals RD and Busy;
when the device works, the data acquisition analysis module acquires and analyzes original high-speed bit stream data, the analyzed high-speed data is transmitted to the input buffer module, the output Ready mark is processed by the signal conflict processing module to generate a signal to conduct the first control switch, the high-speed data is transmitted to the middle buffer module, the upper computer reads the data of the middle buffer module through the processor bus, after the processing of the signal conflict processing module, the upper computer generates a signal to conduct the second control switch, the data in the middle buffer module is transmitted to the output buffer module after the connection, and the output buffer module is used for time-sharing reading of the installation word length under the bus reading control.
Furthermore, the signal conflict processing module can realize coordination processing of two operations of cache updating and cache reading according to the sequence of the signal receiving and signal reading of the intermediate cache module, so that simultaneous operation is avoided, and the real-time performance of the system is ensured.
The intermediate buffer module needs to apply signals when new data is acquired and new data is output each time, and if intermediate buffer can not be immediately carried out under the coordination of the signal conflict processing module, the buffer is subjected to complementary detection after the buffer reading operation is finished, so that the number leakage is avoided.
The signal conflict processing module in the invention has the functions of preventing the cache from being updated at high speed and the middle cache from being read at the same time, and ensuring the real-time performance of the system; the invention adopts three-level buffer and a signal conflict processing exchange logic to realize the real-time intermediate buffer of high-speed data, reads the buffer data in real time under the control of a bus, adopts large-scale programmable logic to realize, has high real-time performance and can be flexibly expanded; in the real-time control occasion in the high-speed data acquisition application, the real-time algorithm can acquire the high-speed acquired data quickly, accurately and without omission, and the data interaction method is simple, efficient and flexible, can realize flexible, quick and real-time data transmission, and does not influence the system performance.
Drawings
The structure and features of the present invention are further described below with reference to the drawings and examples.
Fig. 1 is a schematic diagram of the working principle of the present invention.
FIG. 2 is a flow chart of the present invention for high speed data during normal interaction.
FIG. 3 is a schematic diagram of the A-scenario in which high-speed data conflicts in interactions in the present invention.
FIG. 4 is a schematic diagram of the B-scenario in which high-speed data conflicts in interactions in the present invention.
FIG. 5 is a schematic diagram of the situation C when high-speed data conflicts in interactions in the present invention.
FIG. 6 is an embodiment of the invention employing an FPGA design to cache processing units for use in a control system.
Detailed Description
Referring to fig. 1, a high-speed Data real-time exchange processing device is disclosed, and the device comprises a Data acquisition analysis module U0, an input buffer module B0, a signal conflict processing module U1, an intermediate buffer module B1 and an output buffer module B2, wherein the Data acquisition analysis module U0 is respectively connected with the input buffer module B0 and the signal conflict processing module U1, the input buffer module B0 is respectively connected with a first control switch K1, the intermediate buffer module B1, a second control switch K2 and the output buffer module B2, the output buffer module B2 is connected with a processor bus, the output buffer module B2 transmits Data signals to the processor bus, the signal conflict processing module U1 is respectively connected with the first control switch K1 and the second control switch K2, and the read signals RD and Busy are mutually communicated between the signal conflict processing module U1 and the processor bus;
when the device works, the data acquisition analysis module U0 acquires and analyzes original high-speed bit stream data, the analyzed high-speed data is transmitted to the input buffer module B0, the output Ready mark is processed by the signal conflict processing module U1, a signal C1 is generated to conduct the first control switch K1, the high-speed data is transmitted to the middle buffer module B1, the upper computer reads the data of the middle buffer module B1 through the processor bus, after the signal conflict processing module U1 processes, a signal C2 is generated to conduct the second control switch K2, the data in the middle buffer module B1 after the connection is transmitted to the output buffer module B2, and the output buffer module B2 is read out in a time-sharing manner when the word length is installed under the control of bus reading.
Further, the signal conflict processing module U1 can realize coordination processing of two operations of cache updating and cache reading according to the sequence of the signals received by the intermediate cache module B1 and the read signals, so that simultaneous operation is avoided;
the intermediate buffer module B1 needs to apply a signal when acquiring new data and outputting new data each time, and if intermediate buffer cannot be immediately performed under the coordination of the signal conflict processing module U1, the buffer is detected after the buffer reading operation is completed, so as to avoid missing numbers.
Referring to fig. 2, in the case that no conflict occurs in the system, the update of the intermediate buffer and the buffer reading are performed at different time, and at this time, the data acquisition and analysis module U0 analyzes the effective data, updates the data input buffer at time T0, generates a Ready signal at time T1, updates the buffer B1 at time T2 under the control of the signal conflict processing module U1, and the RD signal arrives at time T3, and outputs the data to the buffer module B2 at time T4.
Figures 3-5 illustrate three embodiments of high-speed data when interactions collide, representing three scenarios when collisions occur:
a scenario: the start effective edge of the read signal is earlier than the start edge T5 of the cache update signal, the end edge of the read signal is earlier than the last system clock T7 in the defined time period of the cache update, when the read signal is invalid during the cache update operation, a C1 signal is immediately generated at the time T6 and the time T7, the first control switch K1 is controlled to be turned on, and the intermediate cache update is carried out in a complementary manner;
the B scene is that the initial effective edge of the read signal is earlier than the initial edge T5 of the cache update signal, but the final edge of the read signal is after the last system clock T7 in the defined time period of the cache update, at the moment, the cache update operation waits for the read signal to finish, and then a C1 signal is generated at the moment T6, and a first control switch K1 is conducted and controlled to perform the intermediate cache supplement update;
and C, the situation that the starting effective edge of a read signal is later than the starting edge T5 of a cache updating signal, the ending edge of the read signal is earlier than the moment T7, at the moment, a signal conflict processing module (U1) generates a Busy signal under the control of a CLK clock signal, then generates a C1 signal, controls a first control switch K1 to update the middle cache, an upper computer controller automatically delays and detects according to the Busy signal, generates a signal C2 at the moment T8 after waiting for the completion of the ongoing cache updating operation, controls a second control switch K2, and outputs the middle cache data to an output cache.
In fig. 6, an FPGA is used to design a cache processing unit according to the method principle, and the cache processing unit is successfully applied in a control system, wherein an input system clock CLK of the cache processing unit has a clock period of 10ns, input data including angle data and data flag signals are connected with an upper computer terminal through a bus, so that a path of angle data and the upper computer terminal are exchanged reliably at a high speed, the exchange rate of the path is 4KHZ, and through verification, a collision detection avoidance and delay compensation mechanism based on signal collision processing exchange logic is used, so that the problem of data exchange in the occasion of high real-time requirement is solved. The method can be realized by adopting large-scale programmable logic, has high real-time performance and can be flexibly expanded.
The embodiment of the invention adopts three-level buffer and one signal conflict processing exchange logic to realize the real-time intermediate buffer of high-speed data, reads the buffer data in real time under the control of a bus, adopts large-scale programmable logic to realize, has high instantaneity and can be flexibly expanded. In a real-time control occasion in high-speed data acquisition application, a real-time algorithm can acquire high-speed acquired data quickly, accurately and without omission, and the data interaction method is simple, efficient and flexible, can realize flexible, quick and real-time data transmission, and does not influence system performance; the signal conflict processing module in the embodiment of the invention has the function of preventing the cache from being updated at high speed and the intermediate cache from being read at the same time, and simultaneously ensuring the real-time performance of the system.
The above description is only of the preferred embodiments of the present invention, and the above embodiments are not intended to limit the present invention, and those skilled in the art may make modifications, adaptations or equivalent substitutions according to the above description, which fall within the scope of the present invention.
Claims (3)
1. A data interaction processing method of a high-speed data real-time exchange processing device is characterized by comprising the following steps of: the high-speed Data real-time exchange processing device comprises a Data acquisition analyzer, an input buffer, a signal conflict processor, an intermediate buffer and an output buffer, wherein the Data acquisition analyzer is respectively connected with the input buffer and the signal conflict processor, the input buffer is respectively connected with a first control switch, the intermediate buffer, a second control switch and an output buffer, the output buffer is connected with a bus processor, the output buffer transmits a Data signal Data to the bus processor, the signal conflict processor is respectively connected with the first control switch and the second control switch, and the signal conflict processor and the bus processor realize the intercommunication of a read signal RD and a Busy signal Busy;
when the high-speed data real-time exchange processing device works, the data acquisition analyzer acquires and analyzes original high-speed bit stream data, the analyzed high-speed data is transmitted to the input buffer, the output Ready signal Ready sign is processed by the signal conflict processor to generate a signal to conduct the first control switch, the high-speed data is transmitted to the middle buffer, the upper computer reads the data of the middle buffer through the bus processor, after the processing of the signal conflict processor, the signal to conduct the second control switch is generated, the data in the middle buffer after the conduction is transmitted to the output buffer, the output buffer is read out in a time-sharing mode under the control of bus reading, and particularly three situations exist when the high-speed data are in interaction conflict:
a scenario) the start valid edge of the read signal is earlier than the start edge T5 of the cache update signal, the end edge of the read signal is earlier than the last system clock T7 in the defined time period of the cache update, when the read signal is invalid during the cache update operation, a C1 signal is immediately generated at the time T6 and the time T7, and the first control switch K1 is turned on to perform the intermediate cache supplementary update;
b scenario) the reading signal start effective edge is earlier than the buffer update signal start edge T5, but the end edge is after the last system clock T7 in the buffer update definition time period, at this time, the buffer update operation waits for the reading signal to end and then generates a C1 signal at time T6, and the first control switch K1 is turned on to perform intermediate buffer supplementary update;
c scene) the reading signal start effective edge is later than the buffer updating signal start edge T5, the reading signal end edge is earlier than the time T7, at this moment, the signal conflict processor (U1) generates a Busy signal Busy under the control of a CLK clock signal, then generates a C1 signal, controls the first control switch K1 to update the intermediate buffer, the upper computer controller automatically delays and detects according to the Busy signal Busy, generates a signal C2 at the time T8 after waiting for the ongoing buffer updating operation to finish, and outputs the intermediate buffer data to the output buffer.
2. The data interaction processing method of the high-speed data real-time exchange processing device according to claim 1, wherein: the signal conflict processor can realize coordination processing of two operations of cache updating and cache reading according to the sequence of the signals received by the intermediate cache and the signals read by the intermediate cache, and avoid simultaneous operation.
3. The data interaction processing method of the high-speed data real-time exchange processing device according to claim 1, wherein: the intermediate buffer needs to apply for signals when new data is acquired and output each time, and if intermediate buffer cannot be immediately performed under the coordination of the signal conflict processor, supplementary detection is performed after the buffer reading operation is completed, so that the number leakage is avoided.
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