CN108828290A - Multiloop data sampling method and its manufactured monitoring terminal - Google Patents
Multiloop data sampling method and its manufactured monitoring terminal Download PDFInfo
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- CN108828290A CN108828290A CN201810380044.XA CN201810380044A CN108828290A CN 108828290 A CN108828290 A CN 108828290A CN 201810380044 A CN201810380044 A CN 201810380044A CN 108828290 A CN108828290 A CN 108828290A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
Abstract
The invention discloses a kind of multiloop data sampling methods, carry out multiloop data sampling using the controller with AFE(analog front end).The invention also discloses the monitoring terminals including the multiloop data sampling method.The present invention carries out multiloop data sampling by the controller containing AFE(analog front end), is sampled respectively to voltage and current, and the Σ Δ ADC of AFE(analog front end) is sampled using software triggering mode, and SAR-ADC uses polling mode；And not used channel can carry out time-sharing multiplex, can save the spending of AFE in chip in this way；Therefore the present invention is low in cost for developing multiloop sampling apparatus method simple practical.
Description
Technical field
Present invention relates particularly to a kind of multiloop data sampling method and its manufactured monitoring terminals.
Background technique
With the development of economic technology, requirement of the equipment for multiloop data sampling is also higher and higher.Especially matching
In automation system, due to needing to carry out multiloop sampling to data such as voltage, electric currents, to more times in detection route
The requirement that circuit-switched data samples real-time is higher and higher.
Currently, current widely applied multiloop ADC synchronized sampling circuit mostly uses sigma-delta ADC (Σ Δ
ADC principle).Sigma-delta modulator and digital filter inside ADC will have certain settling time, most of
Data filter inside ADC is sinc3 filter, may require that the time of 3 data output after having carried out channel switching
It can just set up.More cpu resources especially can be consumed in the more sampling channels of multiloop, seriously affect other application journey
The response and real-time of sequence；On the other hand, in existing design, as sampling circuit number increases, i.e., sigma-delta number increases
Add, if to meet the requirement of multiloop and real-time, the cost for sampling CPU will be improved greatly.
Summary of the invention
One of the objects of the present invention is to provide multiloop data samplings that is a kind of low in cost and taking into account multiloop sampling
Method.
The second object of the present invention is to provide a kind of monitoring terminal including the multiloop data sampling method.
This multiloop data sampling method provided by the invention carries out multiloop using the controller with AFE(analog front end)
Data sampling.
The ADC of AFE(analog front end) (AFE) is Σ Δ ADC.
The ADC of controller with AFE(analog front end) is SAR (successive approximation register type) ADC.
The controller with AFE(analog front end) is controller (such as control of model MKM34Z256 of KM34 series
Device).
The ADC of the AFE(analog front end) is used for sampled current signals, and the ADC of the controller with AFE(analog front end) is used
In sampled voltage signal.
The ADC of the AFE(analog front end) is used for sampled current signals, specially CH0~CH2 of the ADC channel of AFE(analog front end)
Channel is for A phase, B phase and the C phase current signal in sampling three-phase current signal；The channel CH3 of AFE(analog front end) executes state and turns
Exchange the letters number, the ADC of CH0~CH2 sampling channel of AFE(analog front end) triggers CH3 channel interrupt after the completion of successively sampling, to guarantee
State transition function is executed after the completion of current sample.
The ADC of the controller with AFE(analog front end) is used for sampled voltage signal, specially ADC sampling channel
The channel CH0~CH2 constitutes the 1st circuit of voltage sample, and the channel CH3~CH5 constitutes the 2nd circuit of voltage sample, CH6~CH8
Channel constitutes the 3rd circuit of voltage sample, and the channel CH9~CH11 constitutes the 4th circuit of voltage sample, the 1st~the 4th loop voltage
Sampling channel is used to sample in turn A phase, B phase and C phase voltage data, and the channel reusable for not carrying out voltage sample currently is it
The ADC channel of his sampling functions, such as temperature sampling function.
The present invention also provides a kind of monitoring terminals including the multiloop data sampling method.
The monitoring terminal of this multiloop data sampling method provided by the invention, by the controller for having AFE(analog front end)
Multiloop data sampling is carried out, the Σ Δ ADC of AFE(analog front end) carries out sampling driving by the way of software triggering, is modeled front end
The SAR-ADC of the controller of triggering carries out voltage sample using polling mode, and unsampled channel can carry out other function
The multiplexing of energy, therefore the method for the present invention is low in cost, and takes into account multiloop sampling.
Detailed description of the invention
Fig. 1 is the sampling schematic diagram of the method for the present invention.
Fig. 2 is the state switching flow figure of the method for the present invention.
Specific embodiment
It is as shown in Figure 1 the sampling schematic diagram of the method for the present invention：This multiloop data sampling method provided by the invention,
Multiloop data sampling is carried out using the controller with AFE(analog front end).The ADC of AFE(analog front end) (AFE) is Σ Δ ADC.With mould
The ADC of the controller of quasi- front end is SAR (successive approximation register type) ADC.For example, controller of the invention is KM34 series
Controller (such as controller of model MKM34Z256).
The ADC of the AFE(analog front end) is used for sampled current signals, specially CH0~CH2 of the ADC channel of AFE(analog front end)
Channel is for A phase, B phase and the C phase current signal in sampling three-phase current signal；The channel CH3 of AFE(analog front end) executes state and turns
Exchange the letters number, the ADC of CH0~CH2 sampling channel of AFE(analog front end) triggers CH3 channel interrupt after the completion of successively sampling, to guarantee
State transition function is executed after the completion of current sample.The ADC of the controller with AFE(analog front end) believes for sampled voltage
Number, specially ADC sampling channel the channel CH0~CH2 constitute voltage sample the 1st circuit, the channel CH3~CH5 constitute voltage
The 2nd circuit, the channel CH6~CH8 of sampling constitute the 3rd circuit of voltage sample, and the channel CH9~CH11 constitutes the of voltage sample
4 circuits, the 1st~the 4th loop voltage sampling channel is used to sample in turn A phase, B phase and C phase voltage data, and does not carry out electricity currently
The channel reusable of pressure sampling is the ADC channel, such as temperature sampling channel etc. of other sampling functions.Before simulation being saved in this way
The sampling channel at end, to substantially reduce use cost of the sampling channel feeder number of AFE(analog front end) in metering chip.
Systematic sampling initial work mainly includes the initialization such as AFE channel parameters, AFE sampling clock, SAR-ADC；Just
The Σ Δ ADC of AFE first carries out three-phase current sampling, the channel CH0~CH2 corresponding A BC three-phase current signal channel, when three after beginningization
After the completion of phase current signal sampling, will triggering the channel CH3 of the Σ Δ ADC of AFE(analog front end), (i.e. the Σ Δ ADC of AFE finally leads to
Road) it interrupts, and channel C H3 will execute state transition function；State transition function is responsible for SAR-ADC three-phase sampled result register
Configuration with voltage IO sampling channel switches.
It is illustrated in figure 2 the state switching flow figure of the method for the present invention：Firstly, a wheel sampling terminates for the first time as described above
Afterwards, it just executes state transition function and is entered state 1 by state 4 (state 4 be original state) and continued Σ Δ ADC electric current and adopt
The SAR-ADC voltage sample (i.e. the channel CH0~CH3 of SAR-ADC sampling channel) of sample and the 1st circuit；Secondly, AFE's is last
The triggering of current sample channel, which is interrupted, then executes state transition function, and process is also transformed into state 2 by state 1, at this time the 2nd circuit three
Phase voltage sampling channel (channel CH3~CH5 of SAR-ADC sampling channel) starts to be sampled；Again, the Σ Δ of AFE(analog front end)
ADC carries out current sample simultaneously until the last channel sample triggering of AFE electric current is interrupted, and executes state transition function, system from
State 2 is transformed into state 3, at this time the 3rd circuit three-phase voltage sampling channel (channel CH6~CH8)；And so on, such as Fig. 2 is completed
Shown in state conversion.
This multiloop data sampling method provided by the present application can be used for other any need progress multiloop data and adopt
The electronic equipment of sample, it is whole including all types of measuring instruments (such as electric energy meter, water meter, gas meter, flow meter, calorimeter etc.), electric energy management
End, distribution terminal, electric energy quality monitoring equipment, grid automation terminal, acquisition terminal, concentrator, data collector, gauge
Table, write by hand device, fault detector etc..
Claims (8)
1. a kind of multiloop data sampling method, it is characterised in that carry out multiloop data using the controller with AFE(analog front end)
Sampling.
2. multiloop data sampling method according to claim 1, it is characterised in that the ADC of AFE(analog front end) is Σ Δ ADC.
3. multiloop data sampling method according to claim 2, it is characterised in that the controller with AFE(analog front end)
ADC is SAR ADC.
4. multiloop data sampling method according to claim 3, it is characterised in that the control with AFE(analog front end)
Device processed is the controller of KM34 series.
5. multiloop data sampling method according to claim 4, it is characterised in that the ADC of the AFE(analog front end) is used for
The ADC of sampled current signals, the controller with AFE(analog front end) is used for sampled voltage signal.
6. multiloop data sampling method according to claim 5, it is characterised in that the ADC of the AFE(analog front end) is used for
Sampled current signals, the specially channel CH0~CH2 of the ADC channel of AFE(analog front end) are for the A in sampling three-phase current signal
Phase, B phase and C phase current signal；The channel CH3 of AFE(analog front end) executes state transition function, CH0~CH2 sampling of AFE(analog front end)
The ADC in channel triggers CH3 channel interrupt after the completion of successively sampling, to execute state conversion letter after the completion of guaranteeing current sample
Number.
7. multiloop data sampling method according to claim 6, it is characterised in that the control with AFE(analog front end)
The ADC of device processed is used for sampled voltage signal, and the specially channel CH0~CH2 of ADC sampling channel constitutes the 1st time of voltage sample
Road, the channel CH3~CH5 constitutes the 2nd circuit of voltage sample, the channel CH6~CH8 constitutes the 3rd circuit of voltage sample, and CH9~
The channel CH11 constitutes the 4th circuit of voltage sample, and the 1st~the 4th loop voltage sampling channel is used to sample in turn A phase, B phase and C
Phase voltage data, and the channel reusable for not carrying out voltage sample currently is the ADC channel of other sampling functions.
8. a kind of monitoring terminal, it is characterised in that including multiloop data sampling method described in one of claim 1~7.
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| CN201810380044.XA CN108828290A (en) | 2018-04-25 | 2018-04-25 | Multiloop data sampling method and its manufactured monitoring terminal |
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| CN201810380044.XA CN108828290A (en) | 2018-04-25 | 2018-04-25 | Multiloop data sampling method and its manufactured monitoring terminal |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101055284A (en) * | 2007-03-12 | 2007-10-17 | 上海安科瑞电气有限公司 | Single-phase multiple-loop monitoring device and its implement method |
| CN101109774A (en) * | 2007-03-12 | 2008-01-23 | 上海安科瑞电气有限公司 | Three-phase multiple loop monitoring device and implementing method thereof |
| CN103364657A (en) * | 2013-06-20 | 2013-10-23 | 广东电网公司东莞供电局 | Unfastening-free current loop bus bar differential protection test device in use for power system bus bar |
| CN104682958A (en) * | 2015-01-26 | 2015-06-03 | 电子科技大学 | Noise-shaping flash successive approximation register analog-to-digital converter (Noise-Shaping Flash-SAR ADC) |
| CN105938159A (en) * | 2016-06-28 | 2016-09-14 | 浙江涵普电力科技有限公司 | Method and system for realizing multi-loop voltage and multi-loop current synchronous sampling |
-
2018
- 2018-04-25 CN CN201810380044.XA patent/CN108828290A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101055284A (en) * | 2007-03-12 | 2007-10-17 | 上海安科瑞电气有限公司 | Single-phase multiple-loop monitoring device and its implement method |
| CN101109774A (en) * | 2007-03-12 | 2008-01-23 | 上海安科瑞电气有限公司 | Three-phase multiple loop monitoring device and implementing method thereof |
| CN103364657A (en) * | 2013-06-20 | 2013-10-23 | 广东电网公司东莞供电局 | Unfastening-free current loop bus bar differential protection test device in use for power system bus bar |
| CN104682958A (en) * | 2015-01-26 | 2015-06-03 | 电子科技大学 | Noise-shaping flash successive approximation register analog-to-digital converter (Noise-Shaping Flash-SAR ADC) |
| CN105938159A (en) * | 2016-06-28 | 2016-09-14 | 浙江涵普电力科技有限公司 | Method and system for realizing multi-loop voltage and multi-loop current synchronous sampling |
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Application publication date: 20181116 |