CN108809325A - LDPC decoder - Google Patents
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- CN108809325A CN108809325A CN201710312234.3A CN201710312234A CN108809325A CN 108809325 A CN108809325 A CN 108809325A CN 201710312234 A CN201710312234 A CN 201710312234A CN 108809325 A CN108809325 A CN 108809325A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1108—Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping
Abstract
The present invention provides a kind of ldpc decoders, which is characterized in that including：Main control module；Check matrix storage unit；Submatrix controls word modules；And multipair linea angulata information memory cell, wherein, main control module carries out checksum update using check matrix, variable information is updated to obtain intermediate variable result, multipair linea angulata information memory cell is for storing intermediate variable result, degree arranged side by side based on check matrix, mostly cornerwise line number and multipair linea angulata maximum number design the size of the multipair linea angulata information memory cell, submatrix submatrix current when controlling word modules to carrying out layer processing to check matrix using certain degree of parallelism judges as quasi-cyclic matrix or multipair diagonal matrices, when being determined as multipair diagonal matrices structure, main control module is stored using multipair linea angulata information memory cell, wherein, submatrix is the maximum number of multipair diagonal structure when multipair linea angulata maximum number indicates to carry out layer processing to check matrix with certain degree of parallelism.
Description
Technical field
The invention belongs to the communications fields, more specifically to a kind of ldpc decoder.
Background technology
Loe-density parity-check code (Low Density Parity Check Code, LDPC) code is Robert G.Gallager
It was proposed in 1962, until MacKay and Wilberg in 1999 has rediscovered the excellent in performance of LDPC code, just causes volume
The extensive concern of code domain expert and scholars.LDPC code is a kind of linear block codes, and check matrix is sparse matrix, is used
The decoding algorithm of iteration allows LDPC code close to the performance of shannon limit.Since the ldpc decoder of quasi- cyclic is easy to simultaneously
Row realize, high-throughput can be provided, therefore used by multiple standards, currently, the technology of LDPC code be applied to CMMB, DTMB,
In the communication system of the standards such as DVB-S2, DVB-T2, ATSC3.0 and 4G.
Existing ldpc decoder realizes the check matrix for being based primarily upon quasi- cyclic.With technological evolvement, also gradually
There is the check matrix of the even multipair diagonal structure of double diagonal line structure.When designing ldpc decoder or interpretation method,
It is original based on quasi- cyclic design when the check matrix of required processing need to be compatible with quasi- cycle and/or multipair diagonal structure
Ldpc decoder just often needs to redesign to meet Parallel Implementation when being used for the treatment of the check matrix of multipair diagonal structure
It needs, design is complicated, time-consuming and dumb.
In the prior art, also there are the considerations of design LDPC decodings need to be compatible with quasi- cyclic and multipair diagonal structure, group
When matrix is quasi- cyclic, update posterior information is without significant difference, still, when submatrix is multipair diagonal structure, due to
Sub-matrix column weight is more than or equal to 2, and update posterior information can cause the posterior information in same address ram according to row tuple amount phase
It updates with answering repeatedly, and rear primary update can override a preceding updated value, cause performance loss.
Invention content
To solve the above-mentioned problems, the present invention proposes a kind of ldpc decoder of efficient general, is particularly suitable for needing to be compatible with
Handle the check matrix of quasi- cyclic and/or the check matrix of multipair diagonal structure.
The present invention provides a kind of ldpc decoders, which is characterized in that including：Main control module；Check matrix storage unit；
Submatrix controls word modules；And multipair linea angulata information memory cell, wherein the main control module carries out school using check matrix
Update is tested, variable information is updated to obtain intermediate variable as a result, multipair linea angulata information memory cell is for storing the intermediate change
Amount is as a result, degree arranged side by side, mostly cornerwise line number and multipair linea angulata maximum number based on the check matrix are more to design this
The size of diagonal line information memory cell, submatrix control word modules to being carried out at layer to the check matrix with certain degree of parallelism
Current submatrix is that quasi-cyclic matrix or multipair diagonal matrices are judged when reason, when being determined as multipair diagonal matrices structure
When, main control module is stored using the multipair linea angulata information memory cell, wherein the multipair linea angulata maximum number indicates
Submatrix is the maximum number of multipair diagonal structure when carrying out layer processing to the check matrix with certain degree of parallelism.
Still optionally further, in ldpc decoder provided by the invention, further include：Check matrix storage unit；Posteriority
Information memory cell；Check information storage unit；Variable node update module；Check-node update module；Posterior information updates
Module；And address generation module, wherein check matrix storage unit：Under the different code checks supported for storage decoder
All check matrix information；Main control module：Generate the control logic of decoder：Including reading school from check matrix storage unit
Matrix information is tested, submatrix control word is arrived in update；It controls address generator and generates corresponding address, be output to check information storage
Unit and posterior information storage unit；It controls variable node update module, check-node update module and posterior information and updates mould
Block is updated processing；Judge whether currently processed submatrix is multipair diagonal structure according to submatrix control word, it is more in this way
Diagonal structure updates multipair linea angulata information memory cell.
Still optionally further, in ldpc decoder provided by the invention, when judging to be followed subject to currently processed submatrix
Ring structure, posterior information update module are done directly posterior information update.
Still optionally further, in ldpc decoder provided by the invention, when judging currently processed submatrix to be multipair
Check matrix is accordingly decomposed into more submatrixs by diagonal structure, using posterior information update module to the submatrix after decomposition point
It is not updated operation, by update result update to multipair linea angulata information memory cell.
Still optionally further, in ldpc decoder provided by the invention, judging module：For judging whether sentence result firmly
Meet check equations and sentences result output firmly.
Still optionally further, in ldpc decoder provided by the invention, wherein it is defeated that judging module progress sentences result firmly
Go out, including：For judging whether decoder reaches preset maximum iteration, control judging module output sentences result firmly.
Still optionally further, in ldpc decoder provided by the invention, wherein the multipair linea angulata information memory cell
Size determined by following manner：
Degree of parallelism × (posterior information bit wide+variable information bit wide × (K-1)) × Ndiag,
Wherein, degree of parallelism indicates the size of the submatrix for handling check matrix；Posterior information bit wide is expressed as posteriority
Width is preset needed for information memory cell；Variable information bit wide is expressed as setting in advance needed for variable information storage unit
Fixed width degree；NdiagSubmatrix is the maximum number of multipair diagonal structure when indicating to carry out layer processing with certain degree of parallelism；K expressions pair
Linea angulata number.
Still optionally further, in ldpc decoder provided by the invention, wherein ldpc decoder further includes utilizing verification
Matrix memory cell：All check matrix information under the different code checks supported for storage decoder can configure and support difference
Consensus standard.
Still optionally further, in ldpc decoder provided by the invention, wherein support ATSC3.0 standard agreements, verification
Matrix memory module need to store the information of two kinds of code lengths and corresponding code check, and code length is divided into 16200 and 64,800 two kind, corresponding code
Rate from 2/15 to 13/15 in any one.
Still optionally further, in ldpc decoder provided by the invention, wherein real in the ldpc decoder of ATSC3.0
In existing, it is 360 to use degree of parallelism, and posteriority nodal information and variable node information are disposed as 11 to store, and multipair linea angulata is believed
The size of breath storage RAM is 71280 bits.
The technique effect of the present invention
According to the decoder of LDPC code provided by the present invention, it is contemplated that the check matrix of quasi- cyclic need to be compatible with
And/or the check matrix of multipair diagonal structure not in the prior art completes an iteration and needs to update all check-nodes
And variable node, newer decoding algorithm cannot meet high-speed requirement and occupy unnecessary big storage line by line in this way
Space, and rear primary update can override a preceding updated value, causes performance loss, by quasi-cyclic matrix knot in the present invention
Structure or multipair diagonal matrices structure are judged, and increase to come to intermediate variable knot provided with multipair linea angulata information memory cell
Fruit is stored, and designs the size of multipair linea angulata information memory cell according to mostly cornerwise structure in advance, avoids wasting
Unnecessary memory space can reduce total memory space, and the decoding for realizing compatible quasi- cycle and double diagonal line structure is handled,
The whole memory space reduced needed for decoder, and performance loss will not be caused.
Description of the drawings
Fig. 1 be the embodiment of the present invention LDPC check matrixes in quasi-cyclic matrix structure submatrix schematic diagram；
Fig. 2 be the embodiment of the present invention LDPC check matrixes in the first multipair diagonal matrices structure submatrix signal
Figure；
Fig. 3 is the ldpc decoder structure chart of the embodiment of the present invention；And
Fig. 4 be the embodiment of the present invention LDPC check matrixes in second multipair diagonal matrices structure submatrix signal
Figure.
Specific implementation mode
The present invention proposes a kind of ldpc decoder of efficient general, is particularly suitable for needing the school of compatible processing quasi- cyclic
Test the check matrix of matrix and/or multipair diagonal structure.
Before illustrating scheme of the invention, first LDPC interpretation methods in the prior art are introduced as follows, LDPC decodings
Method uses common normalization minimum sum-product algorithm.
The LDPC interpretation methods of the minimum sum-product algorithm of common normalization, comprise the steps of：
1. initialization：Initial soft value information,
2. check-node updates：
3. variable node updates：
4. hard decision：
5. if meet check equations DHT=0 or current iteration number reach maximum iteration, then iteration terminates；
Otherwise k adds 1 and repeats step 2-5.
Wherein,Variable node i passes to the information of check-node j in expression kth time iteration,It indicates in k iteration
Check-node j passes to the information of variable node i.
NjIndicate all variable node set connected with check-node j, Nj\iIndicate all and school outside removal node i
Test the variable node set of node j connections；MiIndicate all check-node set connected with variable node i.
For initial soft value information,For kth time iteration posterior information.α is normalization factor.
Completion an iteration is can be seen that from above-mentioned decoding procedure to need to update all check-nodesAnd variable nodeCorrespond respectively to the row traversal and row traversal of check matrix.However, existing application is that requirement is more next to system throughput
It is higher, high-speed requirement cannot be met using serial decoding algorithm newer line by line in this way, therefore, it is possible to using parallel
Layer decoding algorithm higher throughput can be provided.
However during using parallel layer decoding algorithm, need to further contemplate check matrix need to be compatible with quasi- cycle
And/or as multipair diagonal structure when premise, when it is the quasi- cyclic in such as Fig. 1 to judge submatrix, can directly it update
Posterior information；However, it is noteworthy that when it is the multipair diagonal structure in such as Fig. 2 to judge submatrix, due to sub-matrix column
Weight is that the posterior information in same address ram can be caused accordingly to update the more of row tuple amount when updating posterior information more than or equal to 2
It is secondary, such as due to be updated 2 times in double diagonal line structure then same row, once being updated after causing in multiple renewal process in Fig. 2
A preceding updated value can be override, performance loss is caused.
In order to which more targetedly statement is convenient, illustrated using double diagonal line structure in the present embodiment, however
It is not limited to this, technical solution proposed by the invention includes the scheme for multipair diagonal structure, also includes in such as Fig. 4
The scheme of such matrix structure, that is to say, that go design storage size using multipair linea angulata maximum number, can more keep away
Exempt from unreasonable waste of storage space, which indicates to carry out layer processing to check matrix with certain degree of parallelism
When submatrix be multipair diagonal structure maximum number, i.e., in figure 4, it can be seen that wherein the row weights of several columns is 1, if having
The row weight of dry row is 2, and not each column row tuple amount is identical, is that multiple submatrixs carry out parallel update operation by verification matrix decomposition
When, there are submatrix for the submatrix that diagonal structure has be off-diagonal structure the case where.
In the present embodiment, quasi- cyclic submatrix is row weight and the square formation that row are 1 again；Double diagonal line structure is two
The superposition of different quasi- cyclic submatrixs.
Fig. 1 gives in the present embodiment submatrix schematic diagram in quasi- cyclic.Fig. 2 gives double in the present embodiment
The submatrix diagram of diagonal structure.
The unit matrix that I is q × q is defined, then quasi- cycle submatrix AijIt can be obtained by the ring shift right of I.Define I (τ m) table
Show I ring shift right τ m, then A as followsij=I (2).
Include the submatrix of quasi- cyclic and double diagonal line structure for check matrix, submatrix can unified definition be
Hij=β0I(τ0)+β1I(τ1), wherein τ0≠τ1,β0, β1=0 or 1. (1)
Further, multipair diagonal structure submatrix can be expressed as：
Existing layer decoding algorithm is optimized on normalization sum-product algorithm, and processing step is as follows：
1. initialization：Wherein Lch is initial soft value information (3)
2. variable node updates：
3. check-node updates：
4. posterior information updates：
5. repeating step 2-4 until completing all layers of update
6. hard decision：
7. if meet check equations DHT=0 or current iteration number reach maximum iteration, then iteration terminates；
Otherwise k adds 1 and repeats step 2-6.
It is above-mentioned that existing LDPC decoding schemes are described, a kind of LDPC decodings in the embodiment of the present invention are provided below
Scheme.Ldpc decoder in the embodiment of the present invention or LDPC interpretation methods, can reduce the memory space of decoder, avoid not
Necessary waste of storage space, no matter submatrix HijSubject to cycle or double diagonal line structure, can be transferred through a set of general translate
Code device structure is realized, without redesigning decoder, is illustrated below in conjunction with prior art emphasis to how to realize.
In conjunction with attached drawing 3, ldpc decoder of the invention and the specific implementation of LDPC interpretation methods are as follows：
Posterior information is stored using posterior information RAM in the present embodiment, is stored using multipair linea angulata information storage RAM more
Diagonal line handles information needed, and this method can reduce total memory space.To multipair linea angulata processing information needed specifically,
That is, when designing the size of multipair linea angulata information memory cell, degree arranged side by side, mostly cornerwise line based on check matrix
Several and multipair linea angulata maximum number designs.
Due to the case where needing that in view of check matrix quasi-cyclic matrix and/or multipair diagonal matrices need to be compatible with, to verification
Matrix is judged using quasi-cyclic matrix structure or multipair diagonal matrices structure：
When judge submatrix for quasi- cyclic when, directly according to formula (6) update posterior information；
When judge submatrix for double diagonal line structure when, due to sub-matrix column weight be 2, directly according to formula (6) update after
Testing information can cause the posterior information in same address ram to update twice, and rear primary update can override a preceding updated value,
Cause performance loss.Method by increasing multipair linea angulata information storage RAM can solve the problems, such as this, and detailed process is as follows：When
When submatrix is double diagonal line structure, it is as follows that submatrix is rewritten according to formula (1)：
Hij=I (τ0)+I(τ1), wherein τ0≠τ1
By the input of formula (4)Store multipair linea angulata information storage RAM.
Store LuSubmatrix is that the number of double diagonal line is related when required space is decoded to layer.
Because of submatrix HijFor double diagonal line structure, therefore it can be analyzed to I (τ0) and I (τ1) two submatrixs carry out it is corresponding
Update operation.Formula (4) can be decomposed into：
For submatrix I (τ0), variable node updates for the first time：
It is updatedPosterior information RAM is stored, the updated data of variable node as shown in Figure 3 pass through choosing
Select device deposit posterior information RAM.
For submatrix I (τ1), second of update of variable node：
It willMultipair linea angulata information storage RAM is stored, is storedSon when required space and layer decode
Matrix is that the number of double diagonal line is related.
The update of formula (5) check-node is constant.
The update of formula (6) posterior information can be decomposed into：
For submatrix I (τ0), when posterior information updates for the first time：
It is read from posterior information RAMAccording to formula (11) updated posterior informationStore posteriority
Information RAM.
For submatrix I (τ1), when posterior information updates for the second time：
It is read from multipair linea angulata information storage RAMAccording to formula (12) updated posterior informationIt deposits
Store up multipair linea angulata information storage RAM.Work as posterior informationBit wide be more than variable information bit wide when,According to
Variable information bit wide carries out saturated process, that is, works asIt, will when the maximum integer that can be indicated more than variable information bit wideIt is assigned a value of the maximum integer that variable information bit wide can indicate；WhenIt can be indicated less than variable information bit wide
Smallest positive integral when, willIt is assigned a value of the smallest positive integral that variable information bit wide can indicate.
Update posterior information RAM：
It is read from posterior information RAMMultipair linea angulata information storage RAM is readAnd Lu, according to formula
(13) updated posterior informationPosterior information RAM is stored, is used with successive iterations for sentencing firmly.
For the storage size of posterior information RAM, when submatrix is multipair diagonal structure, if diagonal line number
For K, variable node updates the respective extension as shown in above-mentioned example；Posterior information updates the respective extension as shown in above-mentioned example.More
The formula (13) of new posterior information RAM is extended to：
In the embodiment of the present invention, LDPC interpretation methods further include utilizing check matrix storage unit：For storage decoder
All check matrix information under the different code checks supported can configure and support different protocol standards.
Such as in ATSC3.0 consensus standards, short code 16200, submatrix size is 360 × 360, is with degree of parallelism
The maximum number of double diagonal line structure is 9 when 360 processing.If posterior information and variable node information are stored with 11, then
In order to solve the problems, such as that double diagonal line conflicts, existing method is to store posterior information and variable node information respectively, and what is needed deposits
Storage space size is 16200 × 11 × 2=356400 bits.Using scheme proposed by the present invention, using posterior information RAM and more
The mode of diagonal line information storage RAM, it is only necessary to 16200 × 11+360 × (11+11) × 9=249480 bits, compare it is found that
Memory space shared by the present invention program significantly reduces.
In addition, the RAM preserving types about the updated information R of check-node are consistent with traditional treatment method, i.e., only deposit
Store up sign bit, maximum value, maximum value index and second largest value.
In addition to above-mentioned LDPC interpretation methods, the present invention also provides a kind of ldpc decoder, which can lead to
The case where need to being compatible with quasi-cyclic matrix and/or multipair diagonal matrices with check matrix, specifically carries out introduced below.
The structural representation of general ldpc decoder proposed by the present invention, as shown in figure 3, decoder includes with lower module：
1. main control module：Generate the control logic of decoder：Including reading check matrix letter from check matrix storage unit
Submatrix control word is arrived in breath, update；It controls address generator and generates corresponding address, be output to check information RAM and posteriority letter
Cease RAM；Control the work of variable node update module, check-node update module and posterior information update module；According to sub- square
Battle array control word judges whether currently processed submatrix is double diagonal line structure, and double diagonal line structure in this way updates multipair linea angulata
Information storage RAM.Judge whether decoder reaches preset maximum iteration, control judging module output sentences result etc. firmly.
2. check matrix storage unit：All check matrixes letter under the different code checks supported for storage decoder
Breath.Belong to sparse matrix feature according to LDPC check matrixes, when realization only needs the information that storage includes non-zero matrix.In ATSC3.0
In, code length is divided into 16200 and 64,800 two kind, and corresponding code check is from 2/15 to 13/15.Therefore the check matrix of ATSC3.0 is supported
Memory module need to store the information of two kinds of code lengths and corresponding code check.To support different protocol standards, the module configurable.
3. posterior information RAM：RAM for storing posterior information is realized using a block RAM in the present embodiment.
4. multipair linea angulata information storage RAM：For storing the information handled needed for multipair linea angulata, aforementioned formula (8), (10)
(12) result of calculation.In the ldpc decoder of ATSC3.0 is realized, degree of parallelism is used for 360, such as posterior information and variable section
Point information is stored with 11, then the storage unit size is 71280 bits.
5. check information RAM：RAM for storing check information is realized using a block RAM in the present embodiment.It is aforementioned
The result of calculation of formula (5).
6. submatrix control word：It is quasi- cyclic or double diagonal line structure to be used to indicate currently processed submatrix.
7. variable node update module：Complete aforementioned formula (4) operation.
8. check-node update module：Complete aforementioned formula (5) operation.
9. posterior information update module：Subject to submatrix when loop structure, aforementioned formula (6) operation is completed；Group square
When battle array is double diagonal line structure, aforementioned formula (11) (12) (13) operation is completed.
10. address generation module：Under master control module controls, access posterior information RAM, multipair linea angulata information storage are generated
RAM and check information address ram.
11. judging module：Aforementioned formula (7) operation is completed, judgement sentences whether result meets check equations and sentence firmly firmly
As a result it exports.
Above-mentioned ldpc decoder structure and implementation method can be compatible with quasi-cyclic matrix and dual-diagonal matrix parallel processing punching
Prominent problem reduces the memory space needed for decoder.
The multipair linea angulata information storage RAM sizes that method proposed by the present invention uses are：
Degree of parallelism × (posterior information bit wide+variable information bit wide) × Ndiag (14)
Wherein NdiagIt indicates using submatrix when the progress layer processing of certain degree of parallelism as the maximum number of double diagonal line structure.It is aobvious
Right NdiagTest matrix row weight is not exceeded.The more existing decoder of general decoder structure is realized with smaller memory space
The efficient decoding of LDPC code.
When the submatrix in check matrix is there are when multipair diagonal structure, which still can be multiplexed.
Submatrix HijIt is as follows：
Wherein mi≠mj, diagonal line number is K.
The multipair linea angulata information storage RAM sizes that then method proposed by the present invention uses are：
Degree of parallelism × (posterior information bit wide+variable information bit wide × (K-1)) × Ndiag (15)
Method proposed by the present invention is also applied for submatrix structure shown in Fig. 4, if that is, in figure 4, it can be seen that wherein
The row weight of dry row is 1, and the row weight of some several columns is 2, and not each column row tuple amount is identical, is multiple sons by verification matrix decomposition
When matrix carries out parallel update operation, there are submatrix for the submatrix that diagonal structure has be off-diagonal structure
Situation.
Those of ordinary skill in the art it should be appreciated that more than specification be only the numerous embodiments of the present invention
One or more of embodiment, and not use limitation of the invention.Any equalization for embodiment described above becomes
The technical solutions such as change, modification and equivalent substitute will all fall the power in the present invention as long as meeting the spirit of the present invention
In the range of sharp claim is protected.
Claims (10)
1. a kind of ldpc decoder, which is characterized in that including：
Main control module；Check matrix storage unit；Submatrix controls word modules；And multipair linea angulata information memory cell,
Wherein, the main control module using check matrix carry out checksum update, variable information is updated to obtain intermediate variable as a result,
Multipair linea angulata information memory cell be used for store the intermediate variable as a result, based on the check matrix it is arranged side by side spend, it is more
Cornerwise line number and multipair linea angulata maximum number design the size of the multipair linea angulata information memory cell,
Submatrix submatrix current when controlling word modules to being subject to certain degree of parallelism to check matrix progress layer processing
Circular matrix or multipair diagonal matrices are judged,
When being determined as multipair diagonal matrices structure, main control module is stored using the multipair linea angulata information memory cell,
Wherein, the multipair linea angulata maximum number indicates with certain degree of parallelism submatrix when to check matrix progress layer processing
For the maximum number of multipair diagonal structure.
2. ldpc decoder as described in claim 1, which is characterized in that further include：
Check matrix storage unit；Posterior information storage unit；Check information storage unit；Variable node update module；Verification
Node updates module；Posterior information update module；And address generation module,
Wherein, check matrix storage unit：All check matrix information under the different code checks supported for storage decoder；
Main control module：Generate the control logic of decoder：Including reading check matrix information, update from check matrix storage unit
To submatrix control word；It controls address generator and generates corresponding address, be output to check information storage unit and posterior information
Storage unit；Control variable node update module, check-node update module and posterior information update module are updated processing；
Judge whether currently processed submatrix is multipair diagonal structure according to submatrix control word, multipair diagonal structure in this way, update
Multipair linea angulata information memory cell.
3. ldpc decoder as claimed in claim 2, it is characterised in that：
Wherein, when judging currently processed submatrix for quasi- cyclic, posterior information update module is done directly posterior information
Update.
4. ldpc decoder as claimed in claim 2, it is characterised in that：
Wherein, when judging that check matrix for multipair diagonal structure, is accordingly decomposed into more submatrixs by currently processed submatrix, profit
Operation is updated respectively to the submatrix after decomposition with posterior information update module, update result update is believed to multipair linea angulata
Cease storage unit.
5. ldpc decoder as claimed in claim 2, which is characterized in that further include：
Judging module：Whether meet check equations for judging to sentence firmly result and hard sentence result output.
6. ldpc decoder as claimed in claim 5, it is characterised in that：
Wherein, judging module carries out sentencing result output firmly, including：For judging whether decoder reaches preset greatest iteration time
Number, control judging module output sentence result firmly.
7. ldpc decoder as described in claim 1, which is characterized in that
Wherein, the size of the multipair linea angulata information memory cell is determined by following manner：
Degree of parallelism × (posterior information bit wide+variable information bit wide × (K-1)) × Ndiag
Wherein, degree of parallelism indicates the size of the submatrix for handling check matrix；Posterior information bit wide is expressed as posterior information
Width is preset needed for storage unit；Variable information bit wide is expressed as presetting width needed for variable information storage unit
Degree；NdiagSubmatrix is the maximum number of multipair diagonal structure when indicating to carry out layer processing with certain degree of parallelism；K indicates diagonal line
Number.
8. ldpc decoder as described in claim 1, which is characterized in that
Wherein, ldpc decoder further includes utilizing check matrix storage unit：The different code checks supported for storage decoder
Under all check matrix information, can configure support different protocol standards.
9. ldpc decoder as claimed in claim 8, which is characterized in that
Wherein, support ATSC3.0 standard agreements, check matrix memory module that need to store the information of two kinds of code lengths and corresponding code check,
Code length is divided into 16200 and 64,800 two kind, corresponding code check from 2/15 to 13/15 in any one.
10. ldpc decoder as claimed in claim 8, which is characterized in that
Wherein, in the realization of the ldpc decoder of ATSC3.0, it is 360 to use degree of parallelism, and posteriority nodal information and variable node are believed
Breath is disposed as 11 to store, and the size of multipair linea angulata information storage RAM is 71280 bits.
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