CN108807512A - Semiconductor device and forming method thereof - Google Patents

Semiconductor device and forming method thereof Download PDF

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Publication number
CN108807512A
CN108807512A CN201710310685.3A CN201710310685A CN108807512A CN 108807512 A CN108807512 A CN 108807512A CN 201710310685 A CN201710310685 A CN 201710310685A CN 108807512 A CN108807512 A CN 108807512A
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trap
conduction type
semiconductor device
top layer
doped region
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CN108807512B (en
Inventor
林鑫成
胡钰豪
林文新
吴政璁
马洛宜·库马
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Vanguard International Semiconductor Corp
Vanguard International Semiconductor America
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Vanguard International Semiconductor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A kind of semiconductor device of present invention proposition and forming method thereof, wherein semiconductor device includes the semiconductor base with the first conduction type, and it is set to the first trap in semiconductor base, wherein the first trap has second conduction type opposite with the first conduction type.Semiconductor device also includes the buried layer being set in semiconductor base and under the first trap, and wherein buried layer has the first conduction type and the first trap of contact.Semiconductor device further includes the source electrode, drain electrode and gate structure being set on semiconductor base, and wherein gate structure is between source electrode and drain electrode.

Description

Semiconductor device and forming method thereof
Technical field
The present invention relates to semiconductor devices, in particular to the semiconductor device of buried layer and its formation side Method.
Background technology
In the semiconductor industry, super-pressure (ultra high voltage, UHV) element is generally by drift region Trap and top layer of the setting with two films of opposite conductivity in (drift region), such as deep high-pressure N-shaped trap (deep high Voltage n-well, DHVNW) and in deep high-pressure N-shaped trap and close to the p-type top layer of component top surface so that two-phase is anti-ballistic The carrier of electric type maintains charge balance, so that super-pressure element is easy to reach completely vague and general, the collapse electricity of lift elements Pressure, and reduce conducting resistance.
However, in nonepitaxial semiconductor technology, the formation of deep high pressure trap need to pass through the diffusion and injection of high temperature (diffusion and drive in, D/I) so that carrier concentration can not be evenly distributed, and the carrier of high concentration is concentrated in half The top surface of conductor substrate.It is completely vague and general to be easy to reach in order to make carrier concentration be evenly distributed, it is necessary to improve in deep high pressure trap The carrier concentration of top layer, but therefore the conducting resistance of super-pressure element will improve.Further, since the carrier concentration of deep high pressure trap All concentrate on top, carrier be easy field oxidation (field oxide) layer is injected because of high electric field so that the reliability of element by To influence.
Although presently, there are semiconductor device and forming method thereof deal with their original scheduled purposes enough, it All do not meet the requirements thoroughly in all fields yet, therefore, regulation and control semiconductor device drift region carrier concentration skill Still there are some problems to need to improve at present in art.
Invention content
The present invention provides the embodiments of semiconductor device and forming method thereof.In order to reduce the surface electricity of semiconductor device So that semiconductor device is easy to reach completely vague and general, and the embodiment of the present invention provides the semiconductor with the first conduction type The first trap is arranged in substrate in semiconductor base, i.e., deep high pressure trap, the first trap has opposite with the first conduction type second to lead Electric type has first to lead to reduce by the way that the buried layer with the first conduction type is arranged under the first trap in the first trap Script is located at the top of semiconductor base and has the first conduction type by the carrier doping concentration of the first top layer of electric type Carrier concentration is distributed to the bottom of semiconductor base so that the carrier concentration close to the first trap of the top surface of semiconductor base will not Only by one layer, the first top layer with films of opposite conductivity balances, and then reduces the conducting resistance of semiconductor device.
In addition, by the way that the buried layer with films of opposite conductivity, the carrier concentration of deep high pressure trap are arranged under deep high pressure trap It is not concentrated in top, can effectively reduce the probability of carrier injection field oxide, and then promotes the reliability of semiconductor device.
According to some embodiments, semiconductor device is provided.Semiconductor device includes the semiconductor with the first conduction type Substrate, and the first trap for being set in semiconductor base, wherein the first trap has opposite with the first conduction type second to lead Electric type.Semiconductor device also include be set in semiconductor base and the first trap under buried layer, wherein buried layer has the One conduction type, and buried layer contacts the first trap.Semiconductor device further includes the source electrode being set on semiconductor base, leakage Pole electrode and gate structure, wherein gate structure is between source electrode and drain electrode.
According to some embodiments, the forming method of semiconductor device is provided.The method includes to provide to have the first conductive-type The semiconductor base of type forms the first trap in semiconductor base, wherein the first trap has opposite with the first conduction type the Two conduction types.The method is also included in semiconductor base and forms buried layer under the first trap, and wherein buried layer has first Conduction type, and buried layer contacts the first trap.The method further include on a semiconductor substrate formed source electrode, drain electrode and Gate structure, wherein gate structure is between source electrode and drain electrode.
Description of the drawings
Coordinate institute's accompanying drawings by detailed description below, can more understand the viewpoint of the embodiment of the present invention.It is noticeable It is that, according to industrial standard convention, the various parts (feature) in schema may be not to scale.In fact, In order to clearly discuss, the size of various parts may be increased or decreased arbitrarily.
Fig. 1-Fig. 7 is according to some embodiments of the present invention, to show that the section for the different phase for forming semiconductor device shows It is intended to.
Drawing reference numeral：
100~semiconductor device；
101~semiconductor base；
103~patterning photoresist layer；
105~buried layer；
107a, 107b~isolation structure；
109~the first traps；
111~the second traps；
113~the first top layers；
115~the second top layers；
117~gate structure；
119~the first doped regions；
121~the second doped regions；
123~third doped region；
125~interlayer dielectric layer；
127~source electrode；
127a, 127b, 129a~guide hole；
129~drain electrode；
D~depth.
Specific implementation mode
Following disclosure provides many different embodiments or example, for implementing provided semiconductor device Different elements.Each element and the concrete example of its configuration are described as follows, to simplify the embodiment of the present invention.Certainly, these are only It is example, is not limited to the present invention.For example, if being referred in narration, first element is formed on second element, can The embodiment that the first and second elements are in direct contact can be included, it is also possible to be formed in the first and second elements comprising additional element Between so that the embodiment that the first and second elements are not directly contacted with.In addition, the embodiment of the present invention may be in different examples Repeat reference numerals and/or letter.It so repeats to be in order to concise and clear, rather than to indicate the different embodiments discussed And/or the relationship between form.
Some variations of embodiment are described below.In the embodiment of different schemas and explanation, similar reference number quilt For indicating similar element.It is understood that before following methods, in and after additional operation, and one can be provided The operation described a bit can be substituted for the other embodiment of this method or be deleted.
Some embodiments of the present invention provide the method to form semiconductor device.Fig. 1-Fig. 7 is more according to the present invention Embodiment, display form the diagrammatic cross-section of the different phase of semiconductor device 100.
According to some embodiments, as shown in Figure 1, providing the semiconductor base 101 with the first conduction type.It is semiconductor-based Bottom 101 can be made of silicon or other semi-conducting materials, alternatively, semiconductor base 101 may include other elements semi-conducting material, example Such as germanium (Ge).In some embodiments, semiconductor base 101 is made of compound semiconductor, such as silicon carbide, gallium nitride, arsenic Gallium, indium arsenide or indium phosphide.In some embodiments, semiconductor base 101 is made of alloy semiconductor, such as SiGe, silicon carbide Germanium, arsenic phosphide gallium or InGaP.First conduction type of the present embodiment is p-type, therefore semiconductor base 101 is lightly doped P-type substrate.In other embodiments, the first conduction type can be N-type, therefore semiconductor base 101 is the N-type base being lightly doped Bottom.
Connect it is aforementioned, as shown in Figure 1, be formed selectively on semiconductor base 101 patterning photoresist layer 103.Not The region of overlay pattern photoresist layer 103 is the region for being subsequently formed buried layer and the first trap, overlay pattern photoresist layer 103 region is the region for being subsequently formed the second trap.In other embodiments, patterning photoresist layer 103 can not be formed, and In subsequent technique, buried layer is comprehensively formed in semiconductor base 101.
According to some embodiments, as shown in Fig. 2, being shade using patterning photoresist layer 103, pass through ion implantation technology And high-temperature diffusion process, the buried layer 105 with the first conduction type is formed in semiconductor base 101.In the present embodiment, Semiconductor base 101 is P-type substrate, and buried layer 105 passes through the implanting p-type dopant in semiconductor base 101, such as boron (B) it is formed.In other embodiments, semiconductor base 101 is N-type substrate, and buried layer 105 passes through in semiconductor base 101 Interior injection N-type dopant, for example, phosphorus (P) or arsenic (As) and formed.In addition, in some embodiments, the dopant concentration of buried layer 105 In about 1x1014Atoms/cm (atom/cm3) to about 1x1015Atoms/cm (atom/cm3) in the range of, and bury The depth D of layer 105 is set in the range of about 5 μm to about 15 μm.
Then, as shown in figure 3, removing patterning photoresist layer 103, isolation structure is formed on semiconductor base 101 107a and 107b.In some embodiments, the embedded semiconductor base 101 of a part of isolation structure 107a and 107b, and be isolated Another part of structure 107a and 107b are formed on semiconductor base 101.
In some embodiments, silicon selective oxidation (local oxidation of can be used in isolation structure 107a and 107b Silicon, LOCOS) isolation technology and formed.In other embodiments, isolation structure 107a and 107b can be shallow trench isolation (shallow trench isolation, STI) structure.In some embodiments, isolation structure 107a and 107b is by silica, nitrogen SiClx, silicon oxynitride or other suitable dielectric materials are formed.
According to some embodiments, as shown in figure 4, the first trap 109 is formed in semiconductor base 101 and on buried layer 105, First trap 109 has second conduction type opposite with the first conduction type.Connect it is aforementioned, in the present embodiment, the first trap 109 For deep high-pressure N-shaped trap, and the dopant concentration of the first trap 109 is in about 1x1015Atoms/cm (atom/cm3) to about 5x1015 Atoms/cm (atom/cm3) in the range of.It is worth noting that, the first trap 109 is contacted with buried layer 105, due to One trap 109 and buried layer 105 have opposite conduction type so that the interface of the first trap 109 and buried layer 105 generates P-N and connects Face (P-N junction).
First trap 109 can be formed by ion implanting, and in the present embodiment, the first trap 109 is only by two with buried layer 105 Vertical ion implantation technology is respectively formed.In other embodiments, the first trap 109 and buried layer 105 can by identical energy from Sub- injection technology is formed simultaneously, and for example, buried layer 105 is formed by injecting boron (B), and the first trap 109 passes through injection Phosphorus (P) or arsenic (As) and formed, since the ion of boron (B) is smaller, under the energy of identical ion implanting, boron (B) can be compared with In fast speed injection semiconductor base 101, therefore, the buried layer 105 of p-type may be formed at 109 lower section of the first trap of N-type.
Then, as shown in figure 4, forming the second trap 111 in the semiconductor base 101 with the first conduction type, second Trap 111 has the first conduction type, and is adjacent to the first trap 109, and the depth of the first trap 109 is deeper than the second trap 111, therefore the first trap 109 can be described as deep high pressure trap.Connect aforementioned, in the present embodiment, the second trap 111 is p-type trap, and the doping of the second trap 111 is dense Degree is in about 1x1016Atoms/cm (atom/cm3) to about 9x1016Atoms/cm (atom/cm3) in the range of.One In a little embodiments, isolation structure 107a covers the first trap 109 of a part on the first trap 109.Isolation structure 107b is On two traps 111, and cover the second trap 111 of a part.In the present embodiment, the length of buried layer 105 at least with the first trap 109 Length it is rough identical.In the embodiment of other being unpatterned photoresist layers 103, buried layer 105 extends to the second trap 111 lower section.
According to some embodiments, as shown in figure 5, forming the first top layer close to the top of the first trap 109 in the first trap 109 113 and second top layer 115.There is first top layer 113 first conduction type, the second top layer 115 to be located on the first top layer 113 and connect The first top layer 113 is touched, the second top layer 115 has the second conduction type.In the present embodiment, the first top layer 113 be p-type, second Top layer 115 is N-type, and the first top layer 113 and the second top layer 115 are fully set to the lower section of isolation structure 107a, that is, every The first top layer 113 and the second top layer 115 is completely covered in semiconductor from drop shadow spreads of the structure 107a on semiconductor base 101 Drop shadow spread in substrate 101.
Significantly, since the first top layer 113 and the first trap 109 have opposite conduction type so that the first top The interface of layer 113 and the first trap 109 generates P-N junctions.Similarly, since the second top layer 115 and the first top layer 113 have on the contrary Conduction type so that the interface of the second top layer 115 and the first top layer 113 also generates P-N junctions.In some embodiments, first The dopant concentration of top layer 113 and the second top layer 115 is all in about 1x1016Atoms/cm (atom/cm3) to about 9x1016It is former Son/cubic centimeter (atom/cm3) in the range of, and the dopant concentration of the first top layer 113 and the second top layer 115 is rough identical.
Generally speaking, the dopant concentration of the first top layer 113 and the second top layer 115 is all more than the dopant concentration of the first trap 109, And first trap 109 dopant concentration be more than buried layer 105 dopant concentration.
In addition, according to some embodiments of the present invention, the interface of buried layer 105 and the first trap 109, the first trap 109 and The interface of one top layer 113 and the interface of the first top layer 113 and the second top layer 115 are all P-N junctions, by semiconductor-based The multiple P-N junctions of setting are uniformly dispersed in bottom 101, can reduce multiplely surface field (reduced surface field, RESURF) so that semiconductor device can bear higher voltage, be easy to reach completely vague and general, and then reduce conducting resistance and carry High breakdown voltage.
Connect it is aforementioned, as shown in figure 5, semiconductor base 101 and a part isolation structure 107a on formed grid knot Structure 117, gate structure 117 cover the second trap 111 of the first trap 109 and a part of a part.In some embodiments, grid knot Structure 117 may include that the gate dielectric (not being painted) of single one layer or more, and the grid electrode layer of single one layer or more are set to grid It (is not painted) on the dielectric layer of pole.
Gate dielectric can be by silica, silicon nitride, silicon oxynitride, the dielectric material with high-k (low-k) Or combination above-mentioned is made.In some embodiments, gate dielectric passes through plasma enhanced chemical vapor deposition (plasma Enhanced chemical vapor deposition, PECVD) technique or rotary coating (spin coating) technique shape At.
Grid electrode layer is made of an electrically conducting material, such as aluminium (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), polysilicon Or other suitable materials.In some embodiments, grid electrode layer is formed by depositing operation and Patternized technique.Deposit work Skill can be chemical vapor deposition (chemical vapor deposition, CVD) technique, physical vapour deposition (PVD) (physical Vapor deposition, PVD) technique, atomic layer deposition (atomic layer deposition, ALD) technique, high density Plasma-based chemical vapor deposition (high density plasma CVD, HDPCVD) technique, metal organic chemical vapor deposition (metal-organic CVD, MOCVD) technique, plasma enhanced chemical vapor deposition (PECVD) technique or combination above-mentioned.
According to some embodiments, as shown in fig. 6, the first doped region 119 is formed in the first trap 109, in the second trap 111 Form the second doped region 121 and third doped region 123.In addition, third doped region 123 is adjacent to the second doped region 121.Some realities It applies in example, the conduction type of the first doped region 119 is identical as the first trap 109, the conduction type and the second trap of the second doped region 121 111 on the contrary, and the conduction type of third doped region 123 it is identical as the second trap 111.In the present embodiment, the first doped region 119 is N-type, the second doped region 121 are N-type, and third doped region 123 is p-type, and the first doped region 119, the second doped region 121 and third The doping concentration of doped region 123 is in about 1x1018Atoms/cm (atom/cm3) to about 1x1019Atoms/cm (atom/cm3) in the range of.
According to some embodiments, as shown in fig. 7, in semiconductor base 101, isolation structure 107a and 107b and grid knot Interlayer dielectric (inter-layer dielectric, ILD) layer 125 is formed on structure 117.In some embodiments, interlayer dielectric layer 125 by silica, silicon nitride, phosphosilicate glass (phosphosilicate glass, PSG), boron phosphorus silicate glass (borophosphosilicate glass, BPSG) and/or other suitable dielectric materials are formed.Interlayer dielectric layer 125 can By chemical vapor deposition (CVD), physical vapour deposition (PVD) (PVD), atomic layer deposition (ALD), rotary coating or other suitable works Skill and formed.
According to some embodiments, as shown in fig. 7, after forming interlayer dielectric layer 125, the shape on interlayer dielectric layer 125 At source electrode 127 and drain electrode 129.In addition, formed in the interlayer dielectric layer 125 guide hole (via) 127a, 127b and 129a.Drain electrode 129 is electrically connected to the first doped region 119 by guide hole 129a, and source electrode 127 by guide hole 127a and 127b is electrically connected in third doped region 123 and the second doped region 121.In some embodiments, source electrode 127, drain electrode electricity Pole 129 and guide hole 127a, 127b and 129a may include metal or other suitable conductive materials.
In some embodiments, gate structure 117 is set between source electrode 127 and drain electrode 129, and compared to leakage Pole electrode 129, gate structure 117 is closer to source electrode 127.It is formed after source electrode 127 and drain electrode 129, is completed Semiconductor device 100.
In order to reduce the surface field of semiconductor device so that semiconductor device is easy to reach completely vague and general, of the invention Embodiment provides the semiconductor base with the first conduction type, and the first trap is arranged in semiconductor base, i.e., deep high pressure trap, the One trap has second conduction type opposite with the first conduction type, by being arranged with the first conduction type under the first trap Script is located at half by buried layer to reduce the carrier doping concentration of the first top layer with the first conduction type in the first trap The top of conductor substrate and the bottom that there is the carrier concentration of the first conduction type to be distributed to semiconductor base so that close partly to lead The carrier concentration of first trap of the top surface of body substrate will not only by one layer, the first top layer with films of opposite conductivity balances, into And reduce the conducting resistance of semiconductor device.
In addition, by the way that the buried layer with films of opposite conductivity is arranged under the first trap, the carrier concentration of the first trap will not Top is concentrated on, the probability of carrier injection field oxide can be effectively reduced, and then promotes the reliability of semiconductor device.
The component of several embodiments outlined above, so as to can be more in related technical personnel in the technical field of the invention Understand the viewpoint of the embodiment of the present invention.In related technical personnel in the technical field of the invention it should be understood that they can be with this Based on inventive embodiments, the identical purpose of the embodiment that designs or modifies other process and structures to reach with introduce herein And/or advantage.In related technical personnel in the technical field of the invention it should also be appreciated that such equivalent structure has no and is contrary to From spirit and scope of the invention, and miscellaneous change, substitution can be made without prejudice under the spirit and scope of the present invention And replacement.

Claims (16)

1. a kind of semiconductor device, which is characterized in that including：
Semiconductor substrate has one first conduction type；
One first trap, is set in the semiconductor base, and wherein first trap has opposite with first conduction type 1 the Two conduction types；
One buried layer is set in the semiconductor base and under first trap, and wherein the buried layer has first conduction type, And the buried layer contacts first trap；And
One source electrode, a drain electrode and a gate structure, are set on the semiconductor base, and wherein the gate structure is located at Between the source electrode and the drain electrode.
2. semiconductor device as described in claim 1, which is characterized in that compared at a distance from the drain electrode, the grid Structure is closer to the source electrode.
3. semiconductor device as described in claim 1, which is characterized in that further include：
One second trap, is set in the semiconductor base, and is adjacent to first trap, and wherein second trap has first conduction Type；And
One isolation structure covers first trap of a part；
Wherein the gate structure is set on the isolation structure of a part, and covers first trap and a part of a part Second trap.
4. semiconductor device as claimed in claim 3, which is characterized in that further include：
One first doped region is set in first trap, has second conduction type；
One second doped region is set in second trap, has second conduction type；And
One third doped region is set in second trap, is had first conduction type and is adjacent to second doped region；
Wherein first doped region is electrically connected to the drain electrode, and second doped region and the third doped region are electrically connected to this Source electrode.
5. semiconductor device as claimed in claim 3, which is characterized in that the buried layer extends to below second trap.
6. semiconductor device as claimed in claim 3, which is characterized in that further include：
One first top layer is set in first trap, and has first conduction type；And
One second top layer, be set in first trap and first top layer on, and there is second conduction type, wherein this second Top layer contacts first top layer.
7. semiconductor device as claimed in claim 6, which is characterized in that first top layer and second top layer are fully arranged In the lower section of the isolation structure.
8. semiconductor device as claimed in claim 6, which is characterized in that the dopant concentration of first top layer and second top layer More than the dopant concentration of first trap, and the dopant concentration of first trap is more than the dopant concentration of the buried layer.
9. a kind of forming method of semiconductor device, which is characterized in that including：
Semiconductor substrate is provided, there is one first conduction type；
One first trap is formed in the semiconductor base, wherein first trap has opposite with first conduction type one second Conduction type；
In the semiconductor base and a buried layer is formed under first trap, wherein the buried layer has first conduction type, And the buried layer contacts first trap；And
A source electrode, a drain electrode and a gate structure are formed on the semiconductor base, the wherein gate structure is located at Between the source electrode and the drain electrode.
10. the forming method of semiconductor device as claimed in claim 9, which is characterized in that compared to the drain electrode Distance, the gate structure is closer to the source electrode.
11. the forming method of semiconductor device as claimed in claim 9, which is characterized in that further include：
One second trap is formed in the semiconductor base, wherein second trap is adjacent to first trap, and second trap has this First conduction type；And
Form first trap of an isolation structure covering part；
Wherein the gate structure is formed on the isolation structure of a part, and covers first trap and a part of a part Second trap.
12. the forming method of semiconductor device as claimed in claim 11, which is characterized in that further include：
One first doped region is formed in first trap, which has second conduction type；
One second doped region is formed in second trap, which has second conduction type；And
A third doped region is formed in second trap, which has first conduction type, and the third is adulterated Area is adjacent to second doped region；
Wherein first doped region is electrically connected to the drain electrode, and second doped region and the third doped region are electrically connected to this Source electrode.
13. the forming method of semiconductor device as claimed in claim 11, which is characterized in that the buried layer extend to this second Below trap.
14. the forming method of semiconductor device as claimed in claim 11, which is characterized in that further include：
One first top layer is formed in first trap, which has first conduction type；And
One second top layer is formed in first trap and on first top layer, which has second conduction type, In second top layer contact first top layer.
15. the forming method of semiconductor device as claimed in claim 14, which is characterized in that first top layer and second top Layer is completely formed to the lower section of the isolation structure.
16. the forming method of semiconductor device as claimed in claim 14, which is characterized in that first top layer and second top The dopant concentration of layer is more than the dopant concentration of first trap, and the dopant concentration of first trap is dense more than the admixture of the buried layer Degree.
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