CN108807332A - Encapsulating structure - Google Patents
Encapsulating structure Download PDFInfo
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- CN108807332A CN108807332A CN201711241412.4A CN201711241412A CN108807332A CN 108807332 A CN108807332 A CN 108807332A CN 201711241412 A CN201711241412 A CN 201711241412A CN 108807332 A CN108807332 A CN 108807332A
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- transistor
- crystal grain
- control terminal
- encapsulating structure
- electrically connected
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02331—Multilayer structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0239—Material of the redistribution layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/024—Material of the insulating layers therebetween
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
The present invention provides a kind of encapsulating structures comprising redistribution layer and crystal grain.Redistribution layer includes switching circuit and redistribution portion, and switching circuit includes transistor, and redistribution portion is adjacent to switching circuit, and crystal grain is overlapped in at least part in redistribution portion, and wherein transistor is electrically connected crystal grain.
Description
Technical field
The present invention relates to a kind of encapsulating structures, more particularly to the encapsulation knot for being provided with transistor in a kind of redistribution layer
Structure.
Background technology
With the evolution and development of electronic product, electronic product has become indispensable article in society now,
Chips (Chip) are even more to be widely used in electronic product.And after the completion of crystal grain (Die) is manufactured, in order to protect crystal grain to make it
The injury in structure is reduced, technique can be packaged to crystal grain to form chip, also, can also pass through setting while encapsulation
The path that conductive film layer makes crystal grain be electrically connected to external module (such as connection gasket of connection each joint sheet of crystal grain) is more elastic.So
And promoted with the increasingly complexity of diminution and chip functions of encapsulating structure, how to reach encapsulating structure simultaneously
Micro and accurately crystal grain complete encapsulation before can first complete test be industrial circle a big project.
Invention content
In one embodiment, the present invention provides a kind of encapsulating structures comprising redistribution layer (redistribution
Layer, RDL) and crystal grain (die).Redistribution layer includes switching circuit and redistribution portion, and switching circuit includes crystal
Pipe, redistribution portion are adjacent to switching circuit, and crystal grain is overlapped in at least part in redistribution portion, and wherein transistor electrical connection is brilliant
Grain.
In another embodiment, the present invention provides a kind of encapsulating structures comprising crystal grain, the first transistor, the second crystalline substance
Body pipe, the first control terminal, the second control terminal and an at least input/output terminal.Crystal grain includes multiple crystal grain ends, wherein crystal grain end
Including the first crystal grain end and the second crystal grain end.The first transistor includes switch control terminal, first end and second end, wherein
The first end of one transistor is electrically connected to the first crystal grain end.Second transistor includes switch control terminal, first end and second end,
The first end of wherein second transistor is electrically connected to the second crystal grain end.First control terminal is electrically connected to the switch control of the first transistor
End processed, the second control terminal are electrically connected to the switch control terminal of second transistor.An at least input/output terminal include first input/
Output end is electrically connected to the second end of the first transistor and the second end of second transistor.
Description of the drawings
Fig. 1 show the diagrammatic cross-section of the encapsulating structure of first embodiment of the invention.
Fig. 2 show the circuit diagram of the encapsulating structure of first embodiment of the invention.
Fig. 3 show the diagrammatic cross-section of the encapsulating structure of second embodiment of the invention.
Fig. 4 show the diagrammatic cross-section of the encapsulating structure of third embodiment of the invention.
Fig. 5 show the diagrammatic cross-section of the encapsulating structure of fourth embodiment of the invention.
Fig. 6 show the section schematic diagram of the encapsulating structure excision switching circuit of fourth embodiment of the invention.
Fig. 7 show the circuit diagram of the encapsulating structure of fifth embodiment of the invention.
Fig. 8 show the circuit diagram of the encapsulating structure of sixth embodiment of the invention.
Fig. 9 show the circuit diagram of the encapsulating structure of seventh embodiment of the invention.
Reference sign：100,200,300,400,500,600,700- encapsulating structures；The first insulating layers of 110-；
The first conductive layers of 120-；130- second insulating layers；The second conductive layers of 140-；150- third insulating layers；160- third conductive layers；
162- conductive pads；The 4th conductive layers of 170-；182- external connection pads；184,184 ' testing connection gaskets；190- crystal grain；192- is engaged
Pad；The first crystal grain of 192a- end；The second crystal grain of 192b- end；192c- third crystal grain end；The 4th crystal grain ends 192d-；194- is engaged
Material；702- electrostatic discharge protection circuits；C- capacitances；Electrode under C1-；C2- top electrodes；CH- semiconductor channel layers；CP- conductive patterns
Case；The first conductive patterns of CP1-；The second conductive patterns of CP2-；The first control terminals of CR1-；The second control terminals of CR2-；D,D1,D2,
D3, D4, D5, D6- drain；DV- overlook directions；G, G1, G2, G3, G4, G5, G6- grid；GO- gate insulating layers；IO1- first
Input/output terminal；The second input/output terminals of IO2-；ML- adhesive layers；RDL- redistribution layers；RDP- redistributions portion；S,S1,S2,
S3, S4, S5, S6- source electrode；SB- tin balls；SL- semiconductor layers；SWP- switching circuits；T- transistors；T1- the first transistors；
T2- second transistors；T3- third transistor；The 4th transistors of T4-；The 5th transistors of T5-；The 6th transistors of T6-.
Specific implementation mode
To enable those skilled in the art to be further understood that the present invention, following spy enumerates the embodiment of the present invention, and matches
Close the attached drawing constitution content that the present invention will be described in detail and it is to be reached the effect of.It is noted that attached drawing is simplified signal
Therefore figure only shows the component and syntagmatic related with the present invention, to provide basic framework or implementation of the invention
Clearer description, and actual component is likely more complexity with layout.In addition, for convenience of explanation, each attached drawing of the invention
Shown in component equal proportion drafting not done with the number, shape, size of actual implementation, detailed ratio can be according to design
Demand be adjusted.
In addition, when using term " include (containing) " and/or " having " in the present specification, which specify the feature,
Region, step, operation and/or the presence of component, but other one or more features, region, step, operation, group is not precluded
The presence or increase of part and/or a combination thereof.When the component of such as layer or region is referred to as in another component (or its modification) " upper "
Or when extending to another component " upper ", it can directly on another component or be extended directly on another component, or both
Between there may also be the components of insertion.On the other hand, when claiming in a component " directly existing " another component (or its modification) or "
Directly " another component is extended to " to go up " when, plug-in package is not present between the two.Also, when a component is arrived referred to as " electrical connection "
When another component (or its modification), it can be directly connected to another component or is connected indirectly to separately by one or more components
One component.
Referring to FIG. 1, Fig. 1 show the diagrammatic cross-section of the encapsulating structure of first embodiment of the invention.As shown in Figure 1,
The encapsulating structure 100 of the present embodiment includes redistribution layer (redistribution layer) RDL and crystal grain (die) 190, weight
Distribution layer RDL includes redistribution portion (redistribution portion) RDP and switching circuit SWP, and switching circuit
Portion SWP includes transistor T, and is adjacent to redistribution portion RDP, and citing may be provided at the side of redistribution portion RDP, but not as
Limit.To be clearly painted encapsulating structure 100, Fig. 1 only shows a transistor T, and is exemplified as thin film transistor (TFT) (thin film
Transistor), but invention is not limited thereto.The quantity of transistor T of the present invention can determine according to different demands, in detail
It carefully can refer to following different embodiments.In the present embodiment, redistribution portion RDP and switching circuit SWP is respectively redistribution layer
The different piece of RDL, and it is adjacent to each other, but not limited to this.Crystal grain 190 is located on redistribution layer RDL, and is fixed in redistribution
On layer RDL, and crystal grain 190 is overlapped in redistribution portion RDP on the overlook direction DV of redistribution layer RDL, and wherein crystal grain 190 has
Multiple joint sheets 192.By redistribution layer RDL, it is input to the signal contact of crystal grain 190 or is connect from 190 received signal of crystal grain
Point can be reconfigured or be extended, to help subsequently being connect with the signal of crystal grain 190.
Redistribution layer RDL may include multiple conductive film layers and multiple insulating film layers, to reach matching again for signal contact
It sets or widened function.In the present embodiment, redistribution portion RDP may include there are multiple conductive pattern CP, and conductive pattern CP with
Transistor T is formed with insulating film layer by the conductive film layer in redistribution layer RDL, and wherein transistor T is to pass through conductive pattern
Case CP is electrically connected to crystal grain 190.Specifically, in the present embodiment, redistribution layer RDL may include the first insulating layer 110, first
Conductive layer 120, second insulating layer 130, semiconductor layer SL and the second conductive layer 140, the setting of the first conductive layer 120 are exhausted first
In edge layer 110, second insulating layer 130 is arranged on the first conductive layer 120, and semiconductor layer SL is arranged in second insulating layer 130,
And second conductive layer 140 be arranged in second insulating layer 130.Second conductive layer 140 of the present embodiment is additionally arranged at semiconductor layer
On SL, but not limited to this.In alternate embodiment, it is exhausted that the second conductive layer of part 140 may also be arranged on semiconductor layer SL and second
Between edge layer 130.In Fig. 1 of the present embodiment, the transistor T of switching circuit SWP is with bottom-gate-type transistor (bottom
Gate transistor) for, therefore, the grid G of transistor T can be formed by the first conductive layer 120, gate insulating layer GO
It can be formed by second insulating layer 130, semiconductor channel layer CH can be formed by semiconductor layer SL, and source S can with drain D
It is formed by the second conductive layer 140, but forms film layer and be not limited with transistor T types.In alternate embodiment, switch electricity
The transistor T of road portion SWP can be other kinds of transistor, may be, for example, top gate-type transistors (top gate
transistor)。
In the part of conductive pattern CP, conductive pattern CP can pass through the first conductive layer 120, the second conductive layer 140, semiconductor
Other conductive film layers in layer SL or redistribution layer RDL are formed, and are formed as the conductive structure of single-layer or multi-layer.At this
In embodiment, conductive pattern CP be single layer conductive structure, conductive pattern CP may include at least one first conductive pattern CP1 with extremely
Few one second conductive pattern CP2, and at least one of which of the first conductive pattern CP1 includes identical with the first conductive layer 120
Material, and at least one of which of the second conductive pattern CP2 includes material identical with the second conductive layer 140.For example,
Conductive pattern CP may include multiple first conductive pattern CP1 and multiple second conductive pattern CP2.First conductive pattern CP1 can lead to
It crosses the first conductive layer 120 and forms single layer of conductive structure, therefore the grid G of the first conductive pattern CP1 and transistor T is by same film layer
(the first conductive layer 120) is constituted, so the material of each first conductive pattern CP1 is identical as the material meeting of the first conductive layer 120.
Second conductive pattern CP2 forms single layer of conductive structure, therefore the second conductive pattern CP2 and transistor T by the second conductive layer 140
Source S and drain D be made of same film layer (the second conductive layer 140), so the material of each second conductive pattern CP2 and
The material of two conductive layers 140 can be identical, and but not limited to this.The conductive pattern CP of the present invention can also only include the first conductive pattern
CP1 or the second conductive pattern CP2.In this present embodiment, conductive pattern CP may extend in switching circuit SWP, with crystal
Grid G, source S or the drain D electrical connection of pipe T.
In addition, the redistribution layer RDL of the present embodiment also may include more conductive film layers, (such as third in Fig. 1 is conductive
Layer 160), insulating film layer (such as third insulating layer 150 in Fig. 1) or the film layer needed for other, or with different storehouse sides
Above-mentioned film layer is arranged in formula.For example, third insulating layer 150 is set in the second conductive layer 140 and second insulating layer 130, and
Third insulating layer 150 can have opening, expose the second conductive pattern CP2.Third conductive layer 160 in redistribution portion RDP can
It including multiple conductive pads 162, is electrically connected respectively with corresponding second conductive pattern CP2 by opening, and conductive pad 162 is in face of crystalline substance
The joint sheet 192 of grain 190 is arranged.Each conductive pad 162 can be by grafting material 194, such as tin, with connecing for corresponding crystal grain 190
Conjunction pad 192 engages and the mode of this engagement can be the modes such as eutectic bonding, and thereby each conductive pad 162 can be used to crystal grain 190
Joint sheet 192 is electrically connected to corresponding second conductive pattern CP2.In another alternate embodiment, third insulating layer 150 and second
Insulating layer 130 can also have opening to expose the first conductive pattern CP1, and conductive pad 162 then can be conductive with first by opening
Pattern CP1 electrical connections.Therefore, conductive pad 162 also can be used to the joint sheet 192 of crystal grain 190 being electrically connected to corresponding first and lead
Electrical pattern CP1.
In addition to this, the encapsulating structure 100 of the present embodiment may also include an at least external connection pad 182, be located at redistribution
Layer RDL is in contrast to the side (be located at the 1st figure in the first insulating layer 110 under) of crystal grain 190, and external connection pad 182 also is located at
In redistribution portion RDP, but not limited to this, and wherein conductive pattern CP is also electrically coupleable to the joint sheet 192 of crystal grain 190 and outer
Between portion's connection gasket 182.For example, external connection pad 182 can pass through the opening and the first conductive pattern of the first insulating layer 110
CP1 is electrically connected, to be electrically connected to transistor T by the first conductive pattern CP1.Therefore, the joint sheet 192 of crystal grain 190 can pass through
Conductive pattern CP is electrically connected to transistor T, and is further electrically coupled to external connection pad 182.It is electrically connected the outer of each joint sheet 192
The position of portion's connection gasket 182 can be designed according to demand, such as the distance between external connection pad 182 can be more than crystal grain 190
The distance between joint sheet 192 so that it is more elastic that crystal grain 190 is connected to external connection type.In addition, optionally,
The encapsulating structure 100 of the present embodiment may also include an at least tin ball (solder ball) SB, be set on external connection pad 182,
So that when encapsulating structure 100 is linked with other external structures (such as when being set on circuit board) can be improved connect it is accurate
Degree.In the present embodiment, encapsulating structure 100 may also include adhesive layer (Molding layer) ML, be covered in crystal grain 190, again
On distribution portion RDP and switching circuit SWP, that is, adhesive layer ML is covered on crystal grain 190 and redistribution layer RDL, by crystal grain
190 are sealed on redistribution layer RDL, and cover the circuit that redistribution portion RDP and switching circuit SWP is exposed, and thereby protect
Circuit structure in encapsulating structure 100, but the installation position of adhesive layer ML is not limited.
In the manufacture of the encapsulating structure 100 of the present embodiment, the first insulating layer 110 can be first provided, wherein the first insulating layer
110 can be substrate, may be, for example, hard substrate, including glass substrate, quartz base plate or sapphire substrate or flexible base plate, example
Such as include polyurethane material (polyimide, PI), makrolon (polycarbonate, PC) or poly terephthalic acid second two
Ester material (polyethylene terephthalate, PET).Then, the first conductive layer is formed on the first insulating layer 110
120, second insulating layer 130, semiconductor layer SL and the second conductive layer 140.For example, prior to being covered on the first insulating layer 110
First conductive layer 120, then patterned first conductive layer 120 is formed by photoetching process, that is, complete the first conductive pattern CP1's
It makes.Then, in covering second insulating layer 130 on the first conductive layer 120.Then, in covering semiconductor in second insulating layer 130
Layer SL, and patterned semiconductor layer SL is formed by photoetching process.Then, in covering the second conductive layer on semiconductor layer SL
140, and patterned second conductive layer 140 is formed by photoetching process, and then complete the second conductive pattern CP2 and transistor T
Making.In this present embodiment, third insulating layer 150 can be formed on the second conductive layer 140, and exhausted in third by photoetching process
Opening is formed in edge layer 150.Then, in covering third conductive layer 160 on third insulating layer 150 and the second conductive layer 140, and lead to
It crosses photoetching process and forms patterned third conductive layer 160, thereby form redistribution layer RDL.Then, in the first insulating layer 110
Lower formation external connection pad 182.First conductive layer 120, the second conductive layer 140, third conductive layer 160 and external connection pad 182
Both wherein at least identical or different metal material can be used manufacture, or made, illustrated using different process conditions
For the first conductive layer 120 can be formed by copper with the second conductive layer 140, third conductive layer 160 and external connection pad 182 can be by
Aluminium is formed, but not limited to this.Second insulating layer 130 and the equal insulating film layers of third insulating layer 150 can be for example by silica or nitrogen
The insulating materials such as SiClx are formed, but not limited to this.In addition, when there is the formation of other conductive film layers, material also can be with first
One of conductive layer 120, the second conductive layer 140, third conductive layer 160 and external connection pad 182 are identical or with first
Conductive layer 120, the second conductive layer 140, third conductive layer 160 and external connection pad 182 are all different.
After redistribution layer RDL to be done, it is arranged on being formed by redistribution layer RDL by crystal grain 190, and by crystal grain
190 joint sheet 192 is electrically connected (such as being electrically connected to each other by grafting material 194) with the conductive pad 162 exposed so that brilliant
Grain 190 can be electrically connected with transistor T, and it is more elastic so that crystal grain 190 is connected to external connection type.Finally, by adhesive layer
ML is covered on crystal grain 190, redistribution portion RDP and switching circuit SWP, but the production method of the present invention is not limited.?
In alternate embodiment, directly there can be the side of joint sheet 192 directly to form above-mentioned conductive film layer and insulating film in crystal grain 190
Layer thereby forms conductive pattern CP, transistor T and external connection pad 182, to complete the making of encapsulating structure 100.It must explanation
, since manufacture variation inevitably occurring in the fabrication process, no matter in conductive pattern CP and transistor T
Whether part-structure is formed with identical film layer, the semiconductor channel layer CH of transistor T, source S, drain D, the thickness of grid G
Degree may differ from the thickness of conductive pattern CP, and but not limited to this.
Referring to FIG. 2, Fig. 2 show the circuit diagram of the encapsulating structure of first embodiment of the invention.Such as Fig. 1 and Fig. 2
Shown, the encapsulating structure 100 of the present embodiment includes crystal grain 190, the first transistor T1, second transistor T2, the first control terminal
CR1, the second control terminal CR2 and an at least input/output terminal, will be described below setting for the circuit framework of encapsulating structure 100
Meter.Crystal grain 190 includes multiple crystal grain ends, each joint sheet 192 of the crystal grain 190 of the present embodiment can respectively as a crystal grain end,
Middle crystal grain end may include the first crystal grain end 192a and the second crystal grain end 192b.The first transistor T1 distinguishes with second transistor T2
With switch control terminal, first end and second end, in the present embodiment, the first transistor T1 can be arranged with second transistor T2
In redistribution layer RDL, that is, the first transistor T1 and second transistor T2 may be, for example, the transistor T in Fig. 1, and switch control
End processed can be grid, and first end may respectively be drain electrode and source electrode or respectively source electrode and drain electrode with second end.In Fig. 2, first
Transistor T1 and second transistor T2 is by taking N-type transistor as an example, and the drain D 1 of the first transistor T1 is electrically connected to the first crystal grain
192a, the drain D 2 of second transistor T2 is held to be electrically connected to the second crystal grain end 192b, but not limited to this.In alternate embodiment
In, the first transistor T1 and second transistor T2 also can be P-type transistor.In addition, the first control terminal CR1 and the second control terminal
CR2 is connected to switch control terminal and between the control module of controlling transistor, and control module can position in encapsulating structure
In 100 or be position outside encapsulating structure 100 external module or board.In the present embodiment, the first control terminal CR1 electrical connections
To the grid G 1 of the first transistor T1, the second control terminal CR2 is electrically connected to the grid G 2 of second transistor T2.Input/output terminal
The signal provided to crystal grain 190 or by crystal grain 190 to input signal exports, and input/output terminal may be, for example, in Fig. 1
The external connection pad 182 of encapsulating structure 100, that is to say, that external connection pad 182 can be used as to input signal to crystal grain 190
Input terminal, or the output end as the signal to export crystal grain 190.In the present embodiment, an at least input/output terminal
Including the first input/output terminal IO1, is electrically connected to the source S 1 of the first transistor T1 and the source S 2 of second transistor T2, also
That is the source S 2 of the source S 1 of the first transistor T1 and second transistor T2 are electrically connected to the same external connection pad 182, and the
One input/output terminal IO1 can be electrically connected to the first crystal grain end 192a by the first transistor T1, or pass through second transistor T2 electricity
It is connected to the second crystal grain end 192b.
In the present embodiment, control module can provide control signal to the first control terminal CR1 and the second control terminal CR2, by
The switch of this control the first transistor T1 and second transistor T2.That is, brilliant by controlling the first transistor T1 and second
The switch of body pipe T2, may be selected the first input/output terminal IO1 be electrically connected with the first crystal grain end 192a, and the second crystal grain end
192b is electrically connected or is electrically connected simultaneously the first crystal grain end 192a and the second crystal grain end 192b.Specifically, when control module pair
First control terminal CR1 provides open signal (such as high levle voltage) and to provide shutdown signal to the second control terminal CR2 (such as low
Level voltage) when, the first crystal grain end 192a, the first transistor T1 and the first input/output terminal IO1 (external connections being connect
Pad 182) guiding path can be formed；When the first control terminal of control module pair CR1 provides shutdown signal and to the second control terminal CR2
When providing open signal, (outside connects with the first input/output terminal IO1 for being connect by the second crystal grain end 192b, second transistor T2
Connection pad 182) another guiding path can be formed；When control module pair the first control terminal CR1 and the second control terminal CR2 are provided and opened
When opening signal, the first crystal grain end 192a, the first transistor T1, the first input/output terminal IO1, the second transistor T2 connected
Guiding path can be formed with the second crystal grain end 192b.It follows that by being input to the first control terminal CR1 and the second control terminal
The signal of CR2 can control the conductive path to be used, and the function that is thereby provided to crystal grain 190, signal select.Citing comes
It says, the first crystal grain is exported respectively in different time points using the same first input/output terminal IO1 (external connection pad 182)
The signal that end 192a and the second crystal grain end 192b (two joint sheets 192 for corresponding to crystal grain 190 respectively) is exported, alternatively, can profit
Input signal, such as test signal are distinguished in different time points with the same first input/output terminal IO1, until the first crystal grain end
192a and the second crystal grain end 192b, or input a signal into simultaneously to the first crystal grain end 192a and the second crystal grain end 192b.
Therefore, it can be seen from the above, by above-mentioned design, the quantity of the input/output terminal of the present embodiment can be less than the crystalline substance of crystal grain 190
The quantity at grain end, that is, the quantity of the external connection pad 182 of encapsulating structure 100 can be less than the number of the joint sheet 192 of crystal grain 190
Amount, therefore, the case where each joint sheet compared to traditional crystal grain need to be correspondingly connected with a connection gasket, the encapsulation of the present embodiment
100 required external connection of structure pads 182 quantity and can be reduced, and then reduces the size of encapsulating structure 100.
In addition, in order to keep the function of foregoing circuit more polynary and perfect, the switch electricity of the encapsulating structure 100 of the present embodiment
SWP also washabilitys in road portion include passive device, such as capacitance or resistance.Passive device in Fig. 1 of the present embodiment is with capacitance C
For, wherein capacitance C is electrically connected with transistor T so that can maintain the signal by transistor T.In addition, an electrode of capacitance C
Material may include material identical with the first conductive layer 120 or the second conductive layer 140.In Fig. 1 of the present embodiment, capacitance C
Lower electrode C1 can be that single layer of conductive structure is formed by with the first conductive layer 120, top electrode C2 can be the second conductive layer 140 with
Semiconductor layer SL is formed by multi-layered conductive structure, and but not limited to this.The lower electrode C1 and top electrode C2 of the present invention can foundation
Design requirement and formed by different conductive film layers.In addition, redistribution layer RDL may also include the 4th conductive layer 170, setting
On third insulating layer 150, and capacitance C can be electrically connected to transistor T by the 4th conductive layer 170, wherein the 4th conductive layer
170 can be for example including well-illuminated conductive material, and such as tin indium oxide (ITO), but not limited to this, and capacitance C and transistor T can also pass through
First conductive layer 120, the second conductive layer 140 and third conductive layer 160 at least one of which and be electrically connected to each other.
On the other hand, in conventional package, since each joint sheet of crystal grain need to be correspondingly connected with a connection gasket,
In test, it may be desirable to acupuncture treatment test is carried out to each connection gasket, whether the function to confirm each joint sheet of crystal grain is good, but
Opposite, if the joint sheet quantity of crystal grain is excessive, the acupuncture treatment quantity of test can be made excessive, testing cost is caused to be promoted, and
The contraposition precision of acupuncture treatment can be caused to decline and influence test result.It, can be by by portion and in another conventional test methodologies
Point crystal grain joint sheet short circuit, thereby test these joint sheets together, however such test mode and can not accurately test
Whether the function of all joint sheets is good.In the present embodiment, since the joint sheet 192 of two crystal grain 190 can be connected to together
One connection gasket, therefore the quantity of acupuncture treatment can be reduced in test, thereby reduce testing cost or promoted acupuncture treatment contraposition it is accurate
Degree, also, due to being provided with the foregoing circuit framework comprising transistor T in redistribution layer RDL, it can profit in test
182 pairs of two joint sheets 192 are padded with the same external connection and carry out one-to-one test, to improve the accuracy of test.In addition,
The different types of signal such as analog signal, digital signal may be exported in crystal grain 190, but to these letters of energy interpretation simultaneously
Number detection device it is typically more complicated and expensive, and in the present embodiment, since foregoing circuit framework has selection test brilliant
The function of the joint sheet 192 of grain 190, therefore the joint sheet 192 for exporting different types of signal can separately be tested, thereby reduce
Testing cost or test degree of difficulty.In addition to this, since connection mat structure would generally be destroyed when test is had an acupuncture treatment, and it is unfavorable for tin ball
The setting of SB, therefore, in order to make external connection pad 182 not destroyed by acupuncture treatment, the present embodiment is when being arranged external connection pad 182
Testing connection gaskets 184 can be also additionally set, and be electrically connected with corresponding external connection pad 182, to replace external connection pad 182
Carry out acupuncture treatment test.Further, since the connection gasket quantity of the encapsulating structure 100 of the present embodiment can be reduced, therefore, in connection gasket
Also optionally its size is promoted in design, to promote the contraposition precision of acupuncture treatment.
The encapsulating structure of the present invention is not limited with above-described embodiment, will hereafter continue to disclose other embodiments, so for letter
Change and illustrate and highlight the difference between each embodiment and above-described embodiment, hereinafter marks same components using identical label, and
The repeated section will not be repeated.
Referring to FIG. 3, Fig. 3 show the diagrammatic cross-section of the encapsulating structure of second embodiment of the invention.As shown in figure 3,
Compared to first embodiment, the crystal grain 190 of the present embodiment is overlapped at least one of switching circuit SWP on overlook direction DV
Point, that is to say, that switching circuit SWP and redistribution portion RDP is at least part of to be overlapped in crystal grain 190, for example, weight
Distribution portion RDP can be located at the periphery of switching circuit SWP, and crystal grain 190 is completely covered switching circuit SWP, but not as
Limit.It in the present embodiment,, can due under such configuration although encapsulating structure 200 additionally has switching circuit SWP
So that the region set by switching circuit SWP is located at 190 lower section of crystal grain so that the size of encapsulating structure 200 can more reduce.
Referring to FIG. 4, Fig. 4 show the diagrammatic cross-section of the encapsulating structure of third embodiment of the invention.As shown in figure 4,
Compared to first embodiment, at least one of which of the conductive pattern CP of the encapsulating structure 300 of the present embodiment can be leading for multilayer
Electric structure.For example, the second conductive pattern CP2 of the present embodiment, capacitance C top electrode C2 can pass through the second conductive layer 140
Multi-layered conductive structure is formed with semiconductor layer SL, that is to say, that the second conductive pattern CP2 can simultaneously be schemed by same photoetching process
The second conductive layer of caseization 140 and semiconductor layer SL is formed, therefore the second conductive pattern CP2 can include simultaneously and the second conductive layer
140 material material identical with semiconductor layer SL, but not limited to this, that is to say, that in Fig. 1 and Fig. 4, conductive pattern CP
At least one of which can be identical as at least one of which of the material of conductive layer and the material of semiconductor layer SL, to form single layer
Or the conductive structure of multilayer.In addition, since the second conductive pattern CP2 of the present embodiment is by the second conductive layer 140 and semiconductor
The conductive structure of layer the formed multilayers of SL, therefore, the thickness of the second conductive pattern CP2 can lead to different from the semiconductor of transistor T
The thickness of channel layer CH.
Referring to FIG. 5, Fig. 5 show the diagrammatic cross-section of the encapsulating structure of fourth embodiment of the invention.As shown in figure 5,
Compared to first embodiment, the adhesive layer ML of the encapsulating structure 400 of the present embodiment is covered in crystal grain 190 and redistribution portion RDP
On, and do not cover at least part of switching circuit SWP.Since at least part of switching circuit SWP is not sealed
Glue-line ML is covered, therefore when designing testing connection gaskets 184 ', can be formed and be tested by the conductive film layer in redistribution layer RDL
It is formed with the 4th conductive layer 170 with the first conductive layer 120 in connection gasket 184 ', such as Fig. 5, and third insulating layer 150 and
Two insulating layers 130 have opening to expose the first conductive layer 120 of testing connection gaskets 184 ' so that can be straight when being tested
It is connected on the side with crystal grain 190 and carries out acupuncture treatment test, but not limited to this, and the design of testing connection gaskets also can be such as first in fact
Apply example.And in the present embodiment, all can be carried out after the test of crystal grain 190 and cut technique, by what is do not covered by adhesive layer ML
Switching circuit SWP excision, that is, transistor T, passive device or the testing connection gaskets 184 ' not covered by adhesive layer ML can be
It being cut off after test, that is to say, that at least part of circuit is only used for the test of crystal grain 190, it should be noted that, since transistor T exists
It can be removed after test, therefore, in the present embodiment, testing connection gaskets 184 ' can be for example as input/output shown in Fig. 2
End, and testing connection gaskets 184 ' can not be electrically connected with external connection pad 182, that is, each external connection pad 182 can only be electrically connected crystalline substance
The single joint sheet 192 of grain 190, and design down herein, it can still be reduced when the crystal grain 190 to encapsulating structure 400 is tested
Testing cost reduces test degree of difficulty or promotes the contraposition precision of acupuncture treatment.Referring to FIG. 6, Fig. 6 show the present invention the 4th in fact
Apply example encapsulating structure excision switching circuit section schematic diagram, in figure 6, encapsulating structure 400 after carrying out cutting technique,
Its section can expose the structure positioned at conductive film layer, such as the conductive pattern being electrically connected between transistor T and crystal grain 190
CP, and in Fig. 6 by taking exposed first conductive pattern CP1 and the second conductive pattern CP2 as an example, in excision only to as test use
After the partial circuit on way, the size of encapsulating structure 400 can reduce again.
Referring to FIG. 7, Fig. 7 show the circuit diagram of the encapsulating structure of fifth embodiment of the invention.As shown in fig. 7,
Compared to the circuit framework of first embodiment, the encapsulating structure 500 of the present embodiment further includes third transistor T3, the 4th transistor
T4, the 5th transistor T5 and the 6th transistor T6 are set in the switching circuit SWP in redistribution layer RDL, for example,
Transistor T in Fig. 1 of first embodiment can be used as third transistor T3, the 4th transistor T4, the 5th transistor T5 and the 6th
Any of transistor T6, but not limited to this.Also include third crystal grain end 192c and the 4th crystal grain in multiple crystal grain ends of crystal grain 190
Hold 192d.Third transistor T3, the 4th transistor T4, the 5th transistor T5 and the 6th transistor T6 include switch control respectively
End, first end and second end, and the present embodiment is respectively grid, drain electrode and source electrode with switch control terminal, first end and second end
For, but not limited to this, and in alternate embodiment, switch control terminal, first end and second end also may respectively be grid, source electrode
With drain electrode.In the present embodiment, the drain D 3 of third transistor T3 is electrically connected to the first crystal grain end 192a, and third transistor T3
Source S 3 be electrically connected to the drain D 1 of the first transistor T1 so that the drain D 1 of the first transistor T1 can pass through third transistor
T3 is electrically connected to the first crystal grain end 192a, and the grid G 3 of third transistor T3 is electrically connected to the second control terminal CR2；4th crystal
The drain D 4 of pipe T4 is electrically connected to third crystal grain end 192c, and the source S 4 of the 4th transistor T4 is electrically connected to the first transistor T1
Drain D 1 so that the drain D 1 of the first transistor T1 can also be electrically connected to third crystal grain end 192c by the 4th transistor T4,
And the 4th the grid G 4 of transistor T4 be electrically connected to the second control terminal CR2；The drain D 5 of 5th transistor T5 is electrically connected to second
The source S 2 of transistor T2, and the source S 5 of the 5th transistor T5 is electrically connected to the first input/output terminal IO1 so that second is brilliant
The source S 2 of body pipe T2 can be electrically connected to the first input/output terminal IO1, and the grid of the 5th transistor T5 by the 5th transistor T5
Pole G5 is electrically connected to the first control terminal CR1；The drain D 6 of 6th transistor T6 is electrically connected to the 4th crystal grain end 192d, and the 6th
The source S 6 of transistor T6 is electrically connected to the drain D 5 of the 5th transistor T5, therefore is also electrically connected to the source of second transistor T2
Pole S2, and the drain D 5 of the 5th transistor T5 can be electrically connected to the 4th crystal grain end 192d by the 6th transistor T6, and the 6th is brilliant
The grid G 6 of body pipe T6 is electrically connected to the second control terminal CR2, that is, the first crystal grain end 192a of the present embodiment, the second crystal grain end
192b, third crystal grain end 192c and the 4th crystal grain end 192d are all electronically connected to the first input/output terminal IO1, that is, crystal grain
190 four connection pad joint sheets 192 are electrically connected to the same external connection pad 182.And in the present embodiment, the first transistor T1
There can be different conduction types from the 5th transistor T5, that is, when the first transistor T1 is N-type transistor, then the 5th crystal
Pipe T5 is exactly P-type transistor, vice versa, and third transistor T3 can have different conduction types from the 4th transistor T4,
Be exactly third transistor T3 be N-type transistor when, then the 5th transistor T5 is exactly P-type transistor, and vice versa, second transistor
T2 and the 6th transistor T6 can have different conduction types, that is, when second transistor T2 is N-type transistor, then and the 6th
Transistor T6 is exactly P-type transistor, and vice versa, for example, in the figure 7, the first transistor T1, second transistor T2 and
Three transistor T3 can be N transistor npn npns, and the 4th transistor T4, the 5th transistor T5 and the 6th transistor T6 can be P-type crystal
Pipe, but not limited to this, but should be noted that, in the figure 7, since the first control terminal CR1 controls the first transistor T1 and the 5th
The switch of transistor T5, the second control terminal CR2 control second transistors T2, third transistor T3, the 4th transistor T4, the 6th crystalline substance
The switch of body pipe T6, therefore there is different conduction types, the second control terminal from the 4th transistor T4 by third transistor T3
The signal of CR2 can be used to open one of third transistor T3 and the 4th transistor T4, and close it is another, therefore second
The signal difference of control terminal CR2 can be used to determine that the drain D 1 of the first transistor T1 is brilliant with the first crystal grain end 192a or third
Grain end 192c conductings.Similarly, the signal of the second control terminal CR2 also can be used to open second transistor T2's and the 6th transistor T6
One of them, and close it is another, to determine that the drain D 5 of the 5th transistor T5 is and the second crystal grain end 192b or the 4th crystal grain end
192d is connected.Also, the signal of the first control terminal CR1 can be used to open the first transistor T1 and the 5th transistor T5 wherein it
One, and close it is another, with determine the first input/output terminal IO1 be with third transistor T3 and the 4th transistor T4 wherein it
One conducting is connected with one of second transistor T2 and the 6th transistor T6.In the present embodiment, pass through above-mentioned electricity
Road design, using by the first input/output terminal IO1 representated by the same external connection pad 182 to respectively by crystal grain 190
Four connection pad joint sheets 192 representated by the first crystal grain end 192a, the second crystal grain end 192b, third crystal grain end 192c and the 4th
Crystal grain end 192d carries out the input of selectivity, or makes the signal of the first crystal grain end 192a, the signal of the second crystal grain end 192b, the
The signal of three crystal grain end 192c and the signal of the 4th crystal grain end 192d are exported by 182 selectivity of the same external connection pad, by
This reduces the quantity of external connection pad 182, and thereby the size of diminution encapsulating structure 500, reduction testing cost, reduction test are difficult
Degree or the contraposition precision for promoting test acupuncture treatment.In another embodiment, the circuit framework of the encapsulating structure of the 5th embodiment
It is applicable in the encapsulating structure of second embodiment, 3rd embodiment and fourth embodiment.
In addition, in the present invention, the circuit framework with selection function is not limited with above-described embodiment, in other embodiment
In, also using multiple transistor T make an input/output terminal (connection gasket) with three, five, ten or other be suitble to count
The crystal grain end (joint sheet 192 of crystal grain 190) of amount is electrically connected, and the mode of operation of circuit is different according to circuit framework,
Therefore also it is not limited with above-described embodiment in the operation of circuit.
Referring to FIG. 8, Fig. 8 show the circuit diagram of the encapsulating structure of sixth embodiment of the invention.As shown in figure 8,
Compared to the circuit framework of first embodiment, the encapsulating structure 600 of the present embodiment further includes third transistor T3 and the 4th crystal
Pipe T4 is set in the switching circuit SWP in redistribution layer RDL, for example, the transistor T in Fig. 1 of first embodiment
Any of which of third transistor T3 and the 4th transistor T4 are can be used as, also, an at least input/output terminal also includes second defeated
Enter/output end IO2.Third transistor T3 and the 4th transistor T4 distinguish including switch control terminal, first end and second end, and
The switch control terminal, first end and second end of the present embodiment are respectively by taking grid, drain electrode and source electrode as an example, and but not limited to this,
In alternate embodiment, switch control terminal, first end and second end are respectively with grid, source electrode and drain electrode.In the present embodiment, third
The grid G 3 of transistor T3 is electrically connected to the first control terminal CR1, and the drain D 3 of third transistor T3 is electrically connected to the second crystal grain
192b, the source S 3 of third transistor T3 is held to be electrically connected to the second input/output terminal IO2；4 electricity of grid G of 4th transistor T4
It is connected to the second control terminal CR2, and the drain D 4 of the 4th transistor T4 is electrically connected to the first crystal grain end 192a, the 4th transistor T4
Source S 4 be electrically connected to the second input/output terminal IO2, that is, the first crystal grain end 192a of the present embodiment, the second crystal grain end
192b is also all electronically connected to the second input/output terminal IO2, that is, crystal grain 190 two joint sheets 192 be all electronically connected to it is identical
Two external connection pads 182.In the present embodiment, the first transistor T1 and third transistor T3 citings can be all N-type crystal
Pipe T, and second transistor T2 and the 4th transistor T4 citings also can be all N-type transistor T, but not limited to this.In this circuit
In framework, when the first control terminal of control module pair CR1 provides an open signal and provides a shutdown signal to the second control terminal CR2
When, the first transistor T1 and third transistor T3 can be opened, and close second transistor T2 and the 4th transistor T4 so that first
It is connected between crystal grain end 192a and the first input/output terminal IO1, between the second crystal grain end 192b and the second input/output terminal IO2
Conducting；When the first control terminal of control module pair CR1 provides a shutdown signal and provides an open signal to the second control terminal CR2
When, second transistor T2 and the 4th transistor T4 can be opened, and close the first transistor T1 and third transistor T3 so that the
It is connected between one crystal grain end 192a and the second input/output terminal IO2, the second crystal grain end 192b and the first input/output terminal IO1
Between be connected so that the electrical connection between connection pad joint sheet 192 and external connection pad 182 is commutative, without setting again
Meter and remanufacturing encapsulating structure 600, thereby reduce manufacturing cost.In another embodiment, the encapsulating structure of sixth embodiment
Circuit framework be equally applicable in the encapsulating structure of second embodiment, 3rd embodiment and fourth embodiment.
Referring to FIG. 9, Fig. 9 show the circuit diagram of the encapsulating structure of seventh embodiment of the invention.As shown in figure 9,
In the encapsulating structure 700 of the present embodiment, switching circuit SWP be include electrostatic discharge protection circuit 702, and electrostatic discharge protection circuit
702 are electrically connected between crystal grain 190 and the first input/output terminal IO1, are entered with to avoid from the first input/output terminal IO1
Electrostatic breakdown crystal grain 190.For example, electrostatic discharge protection circuit 702 includes the first transistor T1 and second transistor T2, and first
Transistor T1 and second transistor can transistor T shown in Fig. 1 of such as first embodiment, that is, the transistor T in Fig. 1
Any that can for example as the first transistor T1 and second transistor T2 in Fig. 9, it should be noted that, depicted electrostatic in Fig. 9
Protection circuit is only an example, and the framework of electrostatic discharge protection circuit of the invention is without being limited thereto.In the present embodiment, the first transistor
The grid of T1 can be electrically connected, the source of the first transistor T1 with drain electrode with the crystal grain end (such as first crystal grain end 192a) of crystal grain 190
Pole can be electrically connected with input/output terminal (such as first input/output terminal IO1), and the grid of second transistor T2 and drain electrode can be with
Input/output terminal (such as first input/output terminal IO1) is electrically connected, and the source electrode of second transistor T2 can be with the crystalline substance of crystal grain 190
Grain end (such as first crystal grain end 192a) is electrically connected, and thereby forms the electricity with bilateral diode (back to back diode)
Crystal grain 190 to prevent the destruction of electrostatic, and is protected in road.Therefore, the circuit framework in switching circuit SWP is not limited to above-mentioned
One embodiment, the 5th embodiment and the circuit framework with selection or function of exchange described in sixth embodiment, this circuit framework
Also can be electrostatic discharge protection circuit as described in the 7th embodiment or other need the circuit of transistor T.In another embodiment
In, the encapsulating structure with electrostatic discharge protection circuit, which also can allow, above-mentioned first embodiment, the 5th embodiment and sixth embodiment
The circuit framework that there is selection or function of exchange.
In conclusion since the redistribution layer in the encapsulating structure of the present invention includes the switching circuit with transistor
It portion therefore can be by the design of circuit framework so that the connection gasket of encapsulating structure, the size for reducing encapsulating structure, drop can be reduced
Low testing cost or manufacturing cost promote the contraposition precision having an acupuncture treatment when test, promote test accuracy or increase electrostatic protection
And other effects.
Example the above is only the implementation of the present invention is not intended to restrict the invention, for those skilled in the art
For member, the invention may be variously modified and varied.Any modification made by all within the spirits and principles of the present invention,
Equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (20)
1. a kind of encapsulating structure, which is characterized in that including：
One redistribution layer, including：
One switching circuit, including a transistor；And
One redistribution portion, is adjacent to the switching circuit；And
One crystal grain is overlapped in the redistribution portion,
The wherein described transistor is electrically connected the crystal grain.
2. encapsulating structure as described in claim 1, which is characterized in that the redistribution portion includes multiple conductive patterns, and institute
Stating transistor includes：
One insulating layer；
Semi-conductor layer is set on the insulating layer；
One conductive layer is set on the insulating layer；
At least one of which of the conductive pattern in the wherein described redistribution portion includes material identical with the conductive layer.
3. encapsulating structure as claimed in claim 2, which is characterized in that the conductive pattern in the redistribution portion wherein extremely
One of few with the semiconductor layer is identical material.
4. encapsulating structure as claimed in claim 2, which is characterized in that the thickness of the semiconductor layer is different from the conductive pattern
The thickness of one of case.
5. encapsulating structure as claimed in claim 2, which is characterized in that the switching circuit further includes a passive device.
6. encapsulating structure as claimed in claim 5, which is characterized in that the passive device is a capacitance, and the capacitance has
One electrode, and the material of the electrode includes the material of the conductive layer.
7. encapsulating structure as described in claim 1, which is characterized in that the redistribution portion includes multiple conductive patterns, and institute
Stating transistor includes：
One conductive layer；
One insulating layer is set on the conductive layer；
Semi-conductor layer is set on the insulating layer；
At least one of which of the conductive pattern in the wherein described redistribution portion includes material identical with the conductive layer.
8. encapsulating structure as claimed in claim 7, which is characterized in that the conductive pattern in the redistribution portion wherein extremely
One of few with the conductive layer is same film layer.
9. encapsulating structure as described in claim 1, which is characterized in that the crystal grain is overlapped in the switching circuit.
10. encapsulating structure as described in claim 1, which is characterized in that further include an adhesive layer, adhesive layer is covered in the crystalline substance
On grain and the redistribution portion.
11. encapsulating structure as claimed in claim 10, which is characterized in that the adhesive layer is covered in the switching circuit
On.
12. encapsulating structure as described in claim 1, which is characterized in that the redistribution portion further includes multiple conductive pads, multiple to lead
Electrical pad is arranged in face of the crystal grain, to be engaged with the crystal grain.
13. encapsulating structure as described in claim 1, which is characterized in that the switching circuit further includes electrostatic protection electricity
Road, and the electrostatic discharge protection circuit includes the transistor.
14. a kind of encapsulating structure, which is characterized in that including：
One crystal grain, including multiple crystal grain ends, wherein the crystal grain end includes one first crystal grain end and one second crystal grain end；
One the first transistor, including a switch control terminal, a first end and a second end, wherein the institute of the first transistor
It states first end and is electrically connected to first crystal grain end；
One second transistor, including a switch control terminal, a first end and a second end, wherein the institute of the second transistor
It states first end and is electrically connected to second crystal grain end；
One first control terminal is electrically connected to the switch control terminal of the first transistor；
One second control terminal is electrically connected to the switch control terminal of the second transistor；And
An at least input/output terminal, including one first input/output terminal, is electrically connected to described the second of the first transistor
The second end at end and the second transistor.
15. encapsulating structure as claimed in claim 14, which is characterized in that further include：
One third transistor, including a switch control terminal, a first end and a second end, wherein the institute of the third transistor
It states switch control terminal and is electrically connected to first control terminal, and the first end of the third transistor is electrically connected to described
Two crystal grain ends；
One the 4th transistor, including a switch control terminal, a first end and a second end, wherein the institute of the 4th transistor
It states switch control terminal and is electrically connected to second control terminal, and the first end of the 4th transistor is electrically connected to described
One crystal grain end；And
The wherein described at least input/output terminal includes also one second input/output terminal, is electrically connected to the third transistor
The second end of the second end and the 4th transistor.
16. encapsulating structure as claimed in claim 14, which is characterized in that the crystal grain end also includes a third crystal grain end and one
4th crystal grain end, and the encapsulating structure further includes：
One third transistor, including a switch control terminal, a first end and a second end, wherein the third transistor is electrically connected
It is connected between first crystal grain end and the first end of the first transistor, and the switch of the third transistor
Control terminal is electrically connected to second control terminal；
One the 4th transistor, including a switch control terminal, a first end and a second end, wherein the 4th transistor is electrically connected
It is connected between third crystal grain end and the first end of the first transistor, and the switch of the 4th transistor
Control terminal is electrically connected to second control terminal；
One the 5th transistor, including a switch control terminal, a first end and a second end, wherein the 5th transistor is electrically connected
It is connected between the second end of the second transistor and first input/output terminal, and the institute of the 5th transistor
It states switch control terminal and is electrically connected to first control terminal；And
One the 6th transistor, including a switch control terminal, a first end and a second end, wherein the 6th transistor is electrically connected
It is connected between the 4th crystal grain end and the 5th transistor, and the switch control terminal electrical connection of the 6th transistor
To second control terminal.
17. encapsulating structure as claimed in claim 16, which is characterized in that the first transistor has with the 5th transistor
There is different conduction types.
18. encapsulating structure as claimed in claim 16, which is characterized in that the third transistor has with the 4th transistor
There is different conduction types.
19. encapsulating structure as claimed in claim 16, which is characterized in that the second transistor has with the 6th transistor
There is different conduction types.
20. encapsulating structure as claimed in claim 14, which is characterized in that the quantity of an at least input/output terminal is less than
The crystal grain end quantity of the crystal grain.
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| CN202010596072.2A CN111710657B (en) | 2017-05-05 | 2017-11-30 | Packaging structure |
| US15/943,736 US10910285B2 (en) | 2017-05-05 | 2018-04-03 | Package structure with TFTS and die covered RDL |
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| US201762501758P | 2017-05-05 | 2017-05-05 | |
| US62/501,758 | 2017-05-05 |
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| CN1848668A (en) * | 2005-04-12 | 2006-10-18 | 松下电器产业株式会社 | Differential amplifier circuitry formed on semiconductor substrate with rewiring technique |
| CN101924040A (en) * | 2009-06-10 | 2010-12-22 | 财团法人工业技术研究院 | Chip repairing method and chip stack structure |
| CN104465576A (en) * | 2013-09-17 | 2015-03-25 | 南亚科技股份有限公司 | Semiconductor device and method of fabricating the same |
| US20160095221A1 (en) * | 2014-09-27 | 2016-03-31 | Qualcomm Incorporated | Integration of electronic elements on the backside of a semiconductor die |
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| Publication number | Publication date |
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| CN111710657B (en) | 2022-06-10 |
| CN108807332B (en) | 2020-07-24 |
| CN111710657A (en) | 2020-09-25 |
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