CN108781074B

CN108781074B - Integrated semiconductor circuit, in particular microcontroller

Info

Publication number: CN108781074B
Application number: CN201780015902.4A
Authority: CN
Inventors: A.克内尔; Y.绍韦特; A.奥厄; M.W.哈斯; M.格吕内瓦尔德
Original assignee: Robert Bosch GmbH
Current assignee: Robert Bosch GmbH
Priority date: 2016-03-10
Filing date: 2017-03-03
Publication date: 2022-05-24
Anticipated expiration: 2037-03-03
Also published as: WO2017153293A1; CN108781074A; DE102016203907A1

Abstract

The invention relates to an integrated semiconductor circuit (10), in particular a microcontroller, for operating a transistor (301), wherein the integrated semiconductor circuit (10) has an output interface circuit (200) having an output terminal (a), wherein the output terminal (a) can be connected to a control terminal (302) of the transistor (301), and wherein the integrated semiconductor circuit (10) has a first input interface circuit (100) having a first input terminal (b 1), wherein the first input terminal (b 1) can be connected to a first terminal (304) of the transistor (301) that is different from the control terminal (302). The integrated semiconductor circuit (10) has a device (310) for operating the output interface circuit (200) as a function of an electrical signal at a first input terminal (b 1) of the first input interface circuit (100).

Description

Integrated semiconductor circuit, in particular microcontroller

Technical Field

The present invention relates to an integrated semiconductor circuit according to the preamble of claim 1, and to a circuit arrangement and a method according to the parallel claims.

Background

Electronic circuits are known from the market, which can operate power transistors, for example field effect transistors. In this case, the following operating situations may occur: in this operating situation, the load to be switched is short-circuited and therefore the power transistor (ziehen) may draw an unacceptably high current. Also, the following operating conditions may occur: in the operating situation, the electrical connection to the load to be switched (or the load itself) is interrupted. Both of these situations are generally undesirable.

Disclosure of Invention

Disclosure of the invention

The problem on which the invention is based is solved by an integrated semiconductor circuit according to claim 1, and by a circuit arrangement and a method according to the parallel claims. Advantageous embodiments are specified in the dependent claims. Features which are essential to the invention can also be found in the following description and the drawings, wherein these features can be essential for the invention not only individually but also in various combinations, without this needing to be specified in any more detail.

The present invention relates to integrated semiconductor circuits, in particular microcontrollers, for operating transistors, wherein the integrated semiconductor circuits have an output interface circuit (for example "gate control port" in english) having an output terminal, wherein the output terminal can be connected to a control terminal of a transistor (for example a gate terminal of a field effect transistor), and wherein the integrated semiconductor circuit has a first input interface circuit (for example "drain/source monitoring port" in english) having a first input terminal, wherein the first input terminal can be connected to a first terminal of the transistor (for example a drain or source terminal of a field effect transistor) that is different from the control terminal. The integrated semiconductor circuit has a device for operating the output interface circuit as a function of an electrical signal at the first input terminal of the first input interface circuit.

In short, one terminal of the transistor is connected (preferably directly) to an output terminal of the integrated semiconductor circuit, and the other terminal of the transistor is connected (preferably directly) to an input terminal of the integrated semiconductor circuit, i.e. for example to a "port" of a microcontroller which operates the transistor, respectively. In this case, on the one hand, the load connected to the transistor ("load") can be monitored in view of possible short circuits, and on the other hand, a possible disconnection of the load can be detected.

The load is, for example, an ohmic resistor, a heating element, an inductor, a relay, etc., which is then switched by a transistor to an operating voltage or to a reference potential, so that a (comparatively large) current can flow through the load.

Monitoring of the transistor with respect to possible shorts in parallel with the load can be carried out by determining a so-called "residual voltage" (voltage drop across the on-resistance (e.g. RDSon) of the transistor) which is applied to the transistor in the on-state. For example, a possible short circuit in parallel with the load can be inferred as soon as the residual voltage exceeds a predefinable value. The device realizes under this short circuit condition: the actuation of the transistor at the output terminal is terminated, for example, in a time period of 10 microseconds. Thereby, the transistor may advantageously be protected against damage. In one embodiment, the time period is 0.5 microseconds, in another embodiment the time period is 1 milliseconds, and in yet another embodiment the time period has a value between 0.5 microseconds and 1 millisecond.

The transistor may be, for example, a bipolar transistor, a blocking layer field effect transistor, an FET, a MOSFET (metal-oxide-semiconductor field-effect transistor), a VMOS transistor (V-gated MOS field-effect transistor), or an IGBT (insulated gate bipolar transistor) with an insulated gate electrode.

The invention has the following advantages: the transistor can be operated directly by means of an integrated semiconductor circuit, in particular by means of a microcontroller, without special components. For example, it is possible for the control terminal of the transistor to be connected directly to an output terminal ("port") of the integrated semiconductor circuit. For example, it may be sufficient that: a first terminal of a transistor, which is different from the control terminal, is connected to an input terminal ("port") of the integrated semiconductor circuit only by means of a series ohmic resistor. If necessary, no additional components are even required at all between the integrated semiconductor circuit and the transistor. In this case, it is possible to monitor the transistor with regard to possible short-circuits and/or possible open-circuits of the load to be switched by the transistor.

In addition, the invention has the following advantages: a transistor can be protected quickly and efficiently against an overcurrent, wherein in particular when the transistor is controlled into a conducting state, a voltage or a potential across the transistor is determined. No additional final stage and/or monitoring circuit and/or protective circuit, in particular no additional integrated circuit, for the transistor is necessary. The proposed solution can be applied to the monitoring transistor more flexibly than this particular additional integrated circuit. Accordingly, a bus (bussorientier) connection between the microcontroller and the transistor or a specific additional integrated circuit is not required.

The transistor can advantageously be operated very quickly and/or in short pulses by removing the bus-oriented connection, wherein costs can be saved. For example, here: the transistor actuation is interrupted for a short time, in particular in a manner that is shorter than the possible reaction time of a load switched by the transistor, for example a mechanical element, for example a relay. This enables certain diagnostics to be carried out, which diagnostics would otherwise not be possible with continuous operation of the transistor.

The reaction time of a load switched by a transistor is characterized by a respective specific characteristic of the load. For example, in the case of a relay, the reaction time can be characterized by a time period during which the relay has not closed the contacts after switching on the operating voltage, or during which the relay has not opened the contacts in the case of a sudden switching off of the operating voltage. In the case of electromagnetically actuatable valves, comparable indications of the reaction times are obtained. If the load is, for example, a heating element or the like, the reaction time can be characterized by a thermal time constant or the like.

Furthermore, it is advantageously achieved that a transistor, for example a FET, is particularly effectively controlled. For example, the G terminal ("gate") of the FET is controlled via an RC filter (resistor-capacitor filter, first-order low-pass filter) by means of a pulse-width-modulated signal (pulse-width modulation, PBM, PWM), so that the FET can be operated at least for a short time in a linear operating range. For example, the on-current with respect to the load can be limited or reduced or the switching edge at the FET or at the load can be slowed, as a result of which the emission of undesirable electromagnetic waves (EMV, electromagnetic compatibility) can be reduced.

Furthermore, the direct coupling of the transistor to the integrated semiconductor circuit which controls it advantageously enables: the actuation is coordinated in time with other events and/or switching processes. For example, this can advantageously prevent: a plurality of transistors operated by the integrated semiconductor circuit simultaneously switch on high currents.

In one embodiment, the above-described device is implemented as a hardware circuit and is integrated in an integrated semiconductor circuit. Additional components and costs can thereby be saved.

In a further embodiment, the device comprises at least one delay device in order to delay at least one signal in time. This advantageously achieves that: the transistor is monitored with regard to a short-circuit in parallel with the load and/or the load is monitored with regard to a disconnection which occurs only after a predefinable period of time after the start of the respective switching process. Thereby, a wrong diagnosis can advantageously be avoided.

In a further embodiment, the integrated semiconductor circuit has a second input interface circuit having a second input terminal, wherein the second input terminal can be connected to a second terminal of the transistor, wherein the second terminal of the transistor is different from the control terminal. This makes it possible, for example, to simultaneously determine the potentials at the S terminal ("source") and the D terminal ("drain") of the FET, thereby improving the diagnostic possibilities.

In one embodiment, a capacitor is connected between the first and/or second input terminal and the reference potential or operating voltage potential on the one hand and the other hand. In this way, the first and/or second input terminal can be protected particularly well against possible voltage peaks at the first and/or second terminal of the transistor.

In a further embodiment, the first and/or second input interface circuit comprises a comparator with a predefinable threshold value or a transistor arrangement with different switching thresholds or an analog-digital converter. The voltage applied to the input terminal can therefore advantageously be compared with this threshold value and then evaluated.

In one embodiment, the "predeterminable" threshold value is fixedly predetermined by the design of the integrated semiconductor circuit and corresponds, for example, to a value specified by the semiconductor manufacturer. In a further embodiment, the threshold value that can be specified can be changed or influenced by a user of the integrated semiconductor circuit afterwards, for example by means of programming. The threshold value can also be "settable" or "changeable" as long as it can be specified. This may even be done during operation of the integrated semiconductor circuit.

In particular, a comparatively small threshold value can be predefined as a result. For example, the on-resistance of a transistor (e.g. field effect transistor, FET) is 100 milliohms, where a transistor overcurrent of 5 amps should be monitored. A threshold of 500 millivolts may then be set to enable monitoring.

Furthermore, it is possible to use a fixedly predefined threshold value, which is comparatively small, and to scale (Skallieren) the voltage applied to the input terminals by means of an ohmic voltage divider in a desired manner. The ohmic voltage divider can be arranged internally or externally in the integrated semiconductor circuit.

The voltage applied to the input terminal can therefore also be compared with a variable threshold value, so that, for example, the transistor can be monitored particularly precisely as a function of the transistor type and/or as a function of the operating state of the transistor or of a load switched by the transistor, in view of possible short-circuits in parallel with the load. In a similar manner, the monitoring can also be improved with respect to the disconnection of the load connected to the transistor.

By means of transistor arrangements with different switching thresholds (which are realized, for example, by means of different doping and/or by means of switching means, such as diodes or resistors), the different thresholds can accordingly be used in parallel for comparison with the voltage applied to the input terminals. By means of an analog-digital converter (for example a so-called "direct-conversion analog-digital converter"), a particularly precise determination of the voltage applied to the input terminals can be carried out.

In one embodiment, the threshold value of the comparator, which can be specified, can be programmed within the integrated semiconductor circuit. Thereby, the threshold value can be changed quickly and accurately when necessary.

In a further embodiment, the first and/or second input interface circuit comprises a current source which interacts with the first or second input terminal. Preferably, the current source is switched internally in the integrated semiconductor circuit in parallel with the respective input terminal and the reference potential or operating voltage potential. For example, the current source is designed as a so-called "pull-down" current source. The value of the current is preferably so small that the monitoring of the transistor with respect to possible short circuits in parallel with the load is not significantly affected. This advantageously improves the diagnostic possibilities of the transistor.

In one embodiment, the current source is switched on (activated) only when the transistor is switched into the non-conducting state and/or when the load is to be monitored with regard to a possible disconnection.

If the transistor is switched off (sperren), the load is advantageously subjected to a small current by means of the current source. While the voltage applied to the respective input terminal is determined. As long as this voltage is greater than a predefinable threshold value, it can be concluded that a load is present. As long as the voltage is below a predefinable threshold value, the load break can be concluded.

In a further embodiment, the device comprises at least one of the following elements: digital gate, one-stable trigger stage, two-stable trigger stage, shift register, ohmic resistor, capacitor, inductor and delay circuit. By means of these components, logic operations and/or delay means for logic operations and/or signal delays can be implemented in the integrated semiconductor circuit. In this way, it is particularly advantageously achieved that the output interface circuit is operated as a function of the electrical signal at the first input terminal of the first input interface circuit.

In a further embodiment, the device comprises an or gate, an and gate and a one-shot stage, wherein the output of the input interface circuit is connected to a first input of the or gate, and wherein the internal control output of the integrated semiconductor circuit is connected to an input of the one-shot stage, and wherein the output of the one-shot stage is connected to a second input of the or gate, and wherein the internal control output is connected to a first input of the and gate, and wherein the output of the or gate is connected to a second input of the and gate, and wherein the output of the and gate is connected to an input of the output interface circuit. In this way, an advantageous embodiment of the device is described, which is therefore arranged within the integrated semiconductor circuit.

The invention further relates to a circuit arrangement having an integrated semiconductor circuit according to at least one of the preceding embodiments, wherein the circuit arrangement comprises at least one transistor, and wherein a control terminal of the transistor is connected to an output terminal of the output interface circuit, and wherein a first terminal of the transistor is connected to a first input terminal of the first input interface circuit, and wherein a corresponding connection between the output terminal or the first input terminal and the transistor comprises only passive (passiv), electrical components. In this way, the transistor and/or the load ("load") switched by the transistor can be advantageously monitored in the conductive and/or non-conductive state of the transistor.

Such passive electrical components are, for example: one or more ohmic resistors, capacitors, inductors, diodes, electrical lines, or delay lines, among others.

In a configuration of the circuit arrangement, a second terminal of the transistor, which is different from the control terminal, is connected to an input of the second input interface circuit. The transistor is, for example, a FET, wherein the control terminal corresponds to the G terminal ("gate"), the first terminal corresponds to the D terminal ("drain"), and the second terminal corresponds to the S terminal ("source") of the FET. This advantageously extends the possibilities for operating the at least one transistor.

The invention further relates to a method for operating an integrated semiconductor circuit, in particular a microcontroller, for operating a transistor, wherein the integrated semiconductor circuit has an output interface circuit having an output terminal, and wherein the output terminal can be connected to a control terminal of the transistor, and wherein the integrated semiconductor circuit has a first input interface circuit having a first input terminal, and wherein the first input terminal can be connected to a first terminal of the transistor that is different from the control terminal. The integrated semiconductor circuit has means for operating an output interface circuit as a function of electrical signals at the first input terminal of the first input interface circuit, the output interface circuit being operated as a function of electrical signals at the first input terminal of the input interface circuit. Results in comparable advantages as described above for the integrated semiconductor circuit according to the invention.

In one development of the method, the transistor is monitored with regard to an inadmissibly high current. For this purpose, when the transistor is controlled into a conducting state by means of the output terminal, the voltages applied to the first and/or second input terminal are compared with respect to the threshold value, wherein the comparison result is masked for a predefinable time as a function of a signal at the internal control output of the integrated semiconductor circuit, and wherein the comparison result is used to evaluate the operating state of the transistor, in particular in order to detect an inadmissibly high current flowing through the transistor, and wherein the output interface circuit is operated with the inadmissibly high current such that the transistor is controlled into a nonconducting state. Thereby, the transistor may advantageously be protected against possible damage.

The internal control output of the integrated semiconductor circuit represents an internal network which firstly operates logically with the output terminal and secondly can operate logically with the first and/or second input terminal.

It can be advantageous to switch off the actuation quickly if an inadmissibly high current is detected in a transistor, for example a Field Effect Transistor (FET). For example, the input terminal of the input interface circuit is connected to the D terminal ("drain") of a FET and the voltage or potential on the D terminal of the FET is monitored when the FET is controlled into a conductive state. In the case of an inadmissibly high current in the FET, the residual voltage between the D terminal and the S terminal of the FET is also comparatively large. This is derived from the simple relationship Beziehung from the on-resistance of the FET (the so-called "RDSon"). When this residual voltage exceeds the threshold, the FET should be switched off quickly. The voltage applied at the input terminal is therefore compared with the threshold value that can be specified by means of the comparator described above and is thus digitized. These digital variables can be logically operated in an advantageous manner in order to switch off the FET, i.e. to be controlled from a conductive state into a non-conductive state.

Since the transistor or FET requires a defined time period after the beginning of the non-conducting actuation into the conducting state until the residual voltage reaches its respective final value (Endwert), this signal is delayed in time at the internal actuation output of the integrated semiconductor circuit by means of the above-described delay device and then logically operated with the digital signal derived from the input terminal. The result of the logic operation is logically operated with the undelayed signal at the internal control output, the latter logic operation preferably acting directly on the output terminal.

The logic and/or delay means can be implemented in any manner known per se, for example by means of digital gates or the monostable trigger stages ("monoflops") described above. Also, the logic operation and/or delay means may be implemented by means of a computer program ("software"). The time period characterized by the delay means is for example 10 microseconds. In one embodiment, the time period is adjustable, i.e., different values of the time period can be (variably) predefined. This can be done even during operation of the integrated semiconductor circuit.

In a further embodiment of the method, the disconnection of the load switched by the transistor is monitored. For this purpose, when the transistor is controlled by means of the output terminal into a non-conducting state, the respective current source interacting with the first or second input terminal is switched on, wherein the voltage applied to the respective first or second input terminal is compared with respect to a threshold value, and wherein the state of the load (i.e. the load) connected to the transistor is deduced from the comparison. This advantageously also makes it possible to detect a possible disconnection of the load.

In a further embodiment of the method, a further diagnosis of the transistor and/or of the load switched by the transistor is carried out. For this purpose, the output interface circuit is then operated for a short period of time when the transistor is controlled into a conductive state by means of the output terminal, such that the transistor is controlled or can be controlled into a non-conductive state, wherein the short period of time is less than the response time of the consumer connected to the transistor and/or wherein the short period of time lies within the range of the response time of the transistor, and wherein the voltages applied to the first or second input terminal are compared with respect to a threshold value, and wherein the state of the transistor and/or consumer is deduced from the comparison.

After the transistor has been controlled at its control terminal with a pulsed signal, the response time of the transistor is characterized, for example, by the rise time or fall time of the current, for example the drain current, of the field effect transistor FET.

For example, the load is a relay and therefore has a long reaction time with respect to the transistor. The transistor can therefore advantageously be controlled into the non-conducting state for a short time in order to check, for example, in view of a possible disconnection of the load, as has already been described above.

In a further embodiment, the last-described diagnosis is carried out in reverse. For this purpose, the output interface circuit is then operated for a short period of time when the transistor is controlled by means of the output terminal into a non-conducting state, such that the transistor is controlled or can be controlled into a conducting state, wherein the short period of time is less than the response time of the load connected to the transistor and/or wherein the short period of time lies within the range of the response time of the transistor, and wherein the voltages applied to the first or second input terminal are compared with respect to a threshold value, and wherein the state of the transistor and/or load is deduced from the comparison. This advantageously makes it possible to expand the diagnostic possibilities.

In a further embodiment of the invention, the following method is carried out for advantageously improving the accuracy of the monitoring in view of an impermissibly high current in the transistor ("short detection"):

-operating a transistor operated by the integrated semiconductor circuit using a known current;

determining the respectively associated residual voltage (voltage drop across the on-resistance RDSon) at the transistor;

-storing the measured value pairs and/or other parameters of these currents and residual voltages in a memory of the integrated semiconductor circuit;

-storing a temperature model characterizing these currents and residual voltages in a memory of the integrated semiconductor circuit;

-compensating the threshold value which can be predetermined according to the temperature of the integrated semiconductor circuit and the temperature model.

In a further embodiment of the invention, a plurality of transistors (in particular FETs) are switched in parallel, wherein the control terminals of the transistors are controlled jointly or separately by means of one or more output terminals of the integrated semiconductor circuit, and wherein the plurality of transistors are monitored jointly in view of an impermissibly high current and/or the load switched by the transistors is monitored in view of a possible disconnection.

Drawings

Next, exemplary embodiments of the present invention will be explained with reference to the drawings. In the drawings;

fig. 1 shows a circuit diagram of an input interface circuit with an integrated semiconductor circuit capable of predetermining a threshold value;

fig. 2 shows a first block circuit diagram of an integrated semiconductor circuit, of a transistor which can be operated by the integrated semiconductor circuit, and of a load which can be switched by the transistor;

fig. 3 shows a second block circuit diagram of an integrated semiconductor circuit, of a transistor which can be operated by the integrated semiconductor circuit, and of a load which can be switched by the transistor;

fig. 4 shows a first flowchart of a method for operating an integrated semiconductor circuit;

fig. 5 shows a second flowchart of a method for operating an integrated semiconductor circuit;

FIG. 6 shows a third flowchart of a method for operating an integrated semiconductor circuit;

fig. 7 shows a fourth flowchart of a method for operating an integrated semiconductor circuit.

In various embodiments, the same reference numbers are used in all the figures for functionally equivalent elements and variables.

Detailed Description

Fig. 1 shows a first or second input interface circuit 100 of an integrated semiconductor circuit 10, wherein the first and/or second input interface circuit 100 comprises a comparator 110 with a predefinable threshold 112. The diagram of fig. 1 shows only a fragment of an integrated semiconductor circuit 10 which is extremely large in its entirety.

The circuit according to fig. 1 is implemented bidirectionally, i.e. it also shows an output interface circuit 200 of the integrated semiconductor circuit 10. Accordingly, the "port" of the integrated semiconductor circuit 10, which is shown on the right in fig. 1, may optionally have the function of the input terminal b and/or the function of the output terminal a. This is possible if necessary even simultaneously.

Specifically, fig. 1 also shows: a reference potential 130, which is currently the electrical ground of the integrated semiconductor circuit 10; an operating voltage potential 132, which corresponds to a dc voltage of +3.3 volts, for example; an output stage, which is currently implemented by means of two mutually

complementary MOS transistors

134 and 136; an output control line 138 connected to G terminals ("gates") of the

MOS transistors

134 and 136; two

protection diodes

140 and 142 which are switched on between the reference potential 130, the operating voltage potential 132 and the input terminal b or the output terminal a.

Further, fig. 1 shows: the first or second input interface circuit 100 comprises a current source 152 which cooperates with the first or second input terminal b1, b 2. Currently, the input interface circuit 100 comprises a further current source 150. Two

current sources

150 and 152 are coupled in parallel with the

protection diodes

140 and 142, respectively.

The non-inverting input terminal of the comparator 110 is connected to the input terminal b or the output terminal a. The inverting input of the comparator 110 is connected to a dc voltage source 114, which directly generates the threshold 112. The output of comparator 110 may transmit digital signal 116 to further elements of integrated semiconductor circuit 10 that are not shown in fig. 1.

Currently,

current sources

150 and 152 are continuously active. In one embodiment,

current sources

150 and 152 are individually activatable or deactivatable. In an embodiment (not shown), the input interface circuit comprises transistor devices with different switching thresholds or analog-to-digital converters at the location of the comparator 110. From this, at least similar effects result as in the case of the comparator 110.

Fig. 2 shows a circuit arrangement 300 with an integrated semiconductor circuit 10, in particular a microcontroller, for operating a transistor 301, wherein the integrated semiconductor circuit 10 has an output interface circuit 200 ("gate control port") which has an output terminal a, wherein the output terminal a can be connected to a control terminal 302 of the transistor 301, and wherein the integrated semiconductor circuit 10 has a first input interface circuit 100 ("drain/source monitor port") which has a first input terminal b1, wherein the first input terminal b1 can be connected to a first terminal 304 (D terminal "drain") of the transistor 301 which is different from the control terminal 302. The integrated semiconductor circuit 10 has a device 310 for operating the output interface circuit 200 as a function of an electrical signal (no reference numeral) at the first input terminal b1 of the first input interface circuit 100. A second terminal 306 (S-terminal, "source") different from the control terminal 302 is switched on in this embodiment of fig. 2 with respect to the reference potential 130.

In one embodiment, the voltage of dc voltage source 114 and thus threshold 112 is implemented in input interface circuit 100 in a variable or adjustable manner.

The transistor 301 is currently implemented as a MOSFET (metal-oxide-semiconductor field-effect transistor) in the english language. Alternatively, however, the transistor 301 may be a bipolar transistor, a blocking layer field effect transistor FET, a VMOS transistor (in the english "V-grooved MOS field-effect transistor"), or an IGBT (in the english "insulated gate bipolar transistor") with an insulated gate electrode.

Furthermore, the circuit arrangement 300 of fig. 2 comprises a load 350 ("consumer") connected to the first terminal 304 of the transistor 301, which is characterized, for example, by an ohmic resistance. A first terminal 352 of the load 350 is connected to the first terminal 304 of the transistor 301 and to a first terminal 354 of an ohmic resistor 356, wherein a second terminal 358 of the ohmic resistor 356 is connected to the input terminal b 1. A second terminal 360 of the load 350 is connected to a dc voltage source 362. The voltage of the dc voltage source 362 is now positive with respect to the reference potential 130 and has a higher value than the operating voltage potential 132.

In a very simplified manner, the circuit arrangement 300 according to fig. 2 comprises a transistor 301, wherein a control terminal 302 of the transistor 301 is connected to the output terminal a of the output interface circuit 200, and wherein a first terminal 304 of the transistor 301 is connected to the first input terminal b1 of the first input interface circuit 100, and wherein the respective connection between the output terminal a or the first input terminal b1 and the transistor 301 comprises only passive electrical components.

The apparatus 310 is currently implemented as a hardware circuit and integrated into the integrated semiconductor circuit 10. Here, the device 310 comprises at least one delay device 312 in order to delay in time at least one electrical signal 314. This signal 314 is currently provided by an internal steering output 316.

In this embodiment, the device 310 includes at least one of the following elements: digital gate, one-stable trigger stage, two-stable trigger stage, shift register, ohmic resistor, capacitor, inductor and delay circuit. The digital signals can thus be logically operated upon and/or delayed in time from one another in a manner known per se. Currently, the delay device 312 is implemented as a mono-stable trigger stage ("monoflo").

In particular, the embodiment of fig. 2 shows: the arrangement 310 comprises an or gate 318, an and gate 320, and a one-shot stage 312, wherein an output of the input interface circuit 100 is connected to a first input of the or gate 318, and wherein an internal manipulation output 316 of the integrated semiconductor circuit 10 is connected to an input of the one-shot stage 312, and wherein an output of the one-shot stage 312 is connected to a second input of the or gate 318, and wherein the internal manipulation output 316 is connected to a first input of said and gate 320, and wherein an output of the or gate 318 is connected to a second input of said and gate 320, and wherein an output of the and gate 320 is connected to an input of the output interface circuit 200.

In one specific embodiment, device 310 functions as follows for a first operating state of circuit arrangement 300:

for the non-conducting state of transistor 301, signal 314 has a binary value of "0". The output 220 of the device 310 also has a binary value "0" due to the AND gate 320. Likewise, the voltage at the output terminal a is at least approximately zero, whereby the transistor 301 is switched off accordingly.

For the next on-state of transistor 301, signal 314 has a binary value of "1". The output of the one-shot stage 312 (on the right in fig. 2) therefore likewise has a binary value "1" first. The output of or gate 318 and the upper input of and gate 320 in the figure therefore also assume the binary value "1". Accordingly, output 220 of device 310 also assumes a binary value of "1", whereby output interface circuit 200 may control transistor 301 into a conductive state. Here, the potential at the D terminal can become rapidly smaller.

As long as there is no short circuit at transistor 301 or at load 350, the voltage at input terminal b1 quickly assumes a value that is lower than threshold 112 predefined by dc voltage source 114. Thus, the input 120 of the device 310 assumes a binary value of "0", whereby the output of the OR gate 318 continues to remain at a binary value of "1", regardless of the state of the one-shot stage 312.

But as long as, for example, load 350 has a short, the voltage on the D terminal of transistor 301 remains relatively high and exceeds threshold 112, see fig. 1. Thus, the input 120 of the device 310 assumes a binary value of "1". After a time period predetermined by the one-shot stage 312 has elapsed, the output of the one-shot stage 312 first assumes a binary value "0". Consequently, the input of and gate 320 at the top in the figure likewise assumes the binary value "0". Thus, output 220 of device 310 likewise assumes a binary value of "0", whereby transistor 301 is controlled into a non-conductive state. Damage to the transistor 301 can thereby advantageously be prevented.

It is to be understood that the and gate 320 or the or gate 318 may also be implemented differently depending on the respective polarity of the signals and taking into account the morgan rule, for example as NAND gate NAND-Gatter (Nicht-UND) or as nor gate (Nicht-odd), etc. Currently, the bottom input of the or gate 318 in the figure has an inverter in order to satisfy the logic described above.

In a second operating condition of circuit arrangement 300, transistor 301 is controlled into a non-conductive state by means of output terminal a. At the same time, the current source 152 (see also fig. 1) is active in the figure below. As long as the load 350 does not have a disconnection, the voltage at the input terminal b1 is therefore relatively high and at least above the threshold 112. Digital signal 116 thus has a binary value of "1".

However, as long as the load 350 has an open circuit in the event of an error, the voltage at the input terminal b1 is very low due to the current source 152 and is at least less than the threshold 112. The digital signal 116 therefore has a binary value "0", from which a faulty disconnection of the load 350 can be inferred.

Fig. 3 shows a further embodiment, in which the integrated semiconductor circuit 10 has a second input interface circuit 100' which has a second input terminal b2 (in the figure below), and in which the second input terminal b2 can be connected to a second terminal 306 of the transistor 301 which is different from the control terminal 302. The second terminal 306 is now the S terminal ("source") of the transistor 301.

As can be seen from fig. 3, the terminal 306 of the transistor 301 is connected, on the one hand, to the input terminal b2 of the input interface circuit 100' and, on the other hand, to the reference potential 130 via a comparatively low-ohmic resistor 364 (measuring resistor or conductor line resistor or so-called "shunt").

The function of the input interface circuit 100 (above in the figure) is comparable to the input interface circuit 100 of fig. 2. However, this only follows for monitoring in view of a possible disconnection of the load 350 as already described above.

The function of the input interface circuit 100' (in the figure below) is comparable to the input interface circuit 100 of fig. 2. However, this is only to be seen for monitoring in view of possible shorts on the load 350 or the transistor 301 as already described above. In a similar manner, as in the case of a short, the voltage across the first terminal 304 (D-terminal "drain") of the transistor 301 is relatively high, so the voltage across the resistor 364 is also relatively high and can therefore be used as a criterion for the short.

In particular, the circuit arrangement 300 of fig. 3 has the following advantages: the respective threshold values 112 in the input interface circuits 100 and 100' can be predefined differently. Thereby, an additional degree of freedom with respect to monitoring for short or open circuits is achieved.

Fig. 4 shows a flowchart of a method for operating an integrated semiconductor circuit 10, in particular a microcontroller, for operating a transistor 301, wherein the integrated semiconductor circuit 10 has an output interface circuit 200, which has an output terminal a, and wherein the output terminal a can be connected to a control terminal 302 of the transistor 301, and wherein the integrated semiconductor circuit 10 has a first input interface circuit 100, which has a first input terminal b1, and wherein the first input terminal b1 can be connected to a first terminal 304 of the transistor 301, which is different from the control terminal 302. The integrated semiconductor circuit 10 has a device 310 for operating the output interface circuit 200 as a function of an electrical signal at the first input terminal b1 of the first input interface circuit 100, the output interface circuit 200 being operated as a function of an electrical signal at the first input terminal b1 of the input interface circuit 100. For this, see for example the circuit arrangement 300 according to fig. 2.

Fig. 4 shows, in particular, the monitoring in view of a short-circuit of load 350 or transistor 301. In this case, when transistor 301 is controlled by means of output terminal a into a conducting state, the voltages applied to first and/or second input terminals b1 or b2 are then compared with respect to threshold 112, the result of the comparison being masked for a predefinable time as a function of the signal at internal control output 316 of integrated semiconductor circuit 10, and the result of the comparison being used to evaluate the operating state of transistor 301, in particular in order to detect an inadmissibly high current through transistor 301, and output interface circuit 200 being operated in the event of inadmissibly high current such that transistor 301 is controlled into an inadmissibly high state.

The procedure shown in fig. 4, which can be applied, for example, to the circuit arrangement 300 of fig. 2 or 3, begins in a block 400. In a following block 402, the internal control output 316 is operated in such a way that the transistor 301 is controlled into the conductive state. At the same time, the signal at the internal control output 316 is delayed by a delay device 312, for example by a one-shot stage 312, for a predefinable period of time.

In a following block 404, the voltage applied at the first or second input terminal b1 or b2 is compared with respect to the threshold 112, wherein the digital signal 116 or 116' has a corresponding binary value.

In a subsequent block 406, the digital signal 116 or 116' is logically operated with the delayed signal at the internal control output 316, with the already performed control of the transistor 301 being terminated if necessary.

In a following block 408, the process shown in fig. 4 is ended, wherein an error report is made to the units in the upper level of the integrated semiconductor circuit 10 if necessary.

Fig. 5 shows a method for operating the integrated semiconductor circuit 10, in which the monitoring takes place in view of a possible disconnection of the load 350. In particular, when the transistor 301 is controlled by means of the output terminal a into a non-conducting state, the respective current source 152 interacting with the first or second input terminal b1, b2 is switched on, the voltage applied to the respective first or second input terminal b1 or b2 being compared with respect to the threshold 112, and the state of the load (or load 350) connected to the transistor being ascertained from the comparison. In the circuit arrangement 300 of fig. 2 or 3, this relates in particular to the input interface circuit 100, which is located at the top in the figure and has the input terminal b 1.

The routine shown in fig. 5 begins in block 500. In a following block 502, the internal control output 316 is operated in such a way that the transistor 301 is controlled into a non-conducting state. At the same time (as long as it has not already been done), the current source 152 of the input interface circuit 100 is activated.

In a following block 504, the voltage applied to the first input terminal b1 is compared with respect to the threshold 112, wherein the digital signal 116 has a corresponding binary value.

In a following block 506, a waiting period is provided, which can be specified, for example, as a function of the one-shot stage 312 or other delay means 312 or timer means. During this time period, there is sufficient time for the transistor 301 to actually assume a non-conductive state.

In a following block 508, the digital signal 116 is evaluated. As long as there is no disconnection of the load 350, the voltage at the input terminal b1 is comparatively high and the digital signal 116 accordingly has a binary value "1". However, as long as load 350 has an open circuit, the voltage at input terminal b1 is comparatively low due to the current flowing through current source 152 and digital signal 116 accordingly has a binary value "0".

In a following block 510, the procedure shown in fig. 5 ends, with an error report being made to the units in the upper level of the integrated semiconductor circuit 10 if necessary.

Fig. 6 shows a flow chart of a method for operating integrated semiconductor circuit 10, in which output interface circuit 200 is then operated for a short period of time when transistor 301 is controlled into a conductive state by means of output terminal a, so that transistor 301 is controlled or can be controlled into a non-conductive state, and in which the short period of time is less than the response time of a load (i.e., load 350, for example) connected to transistor 301, and/or in which the short period of time lies within the response time range of transistor 301, and in which the voltages applied to first or second input terminals b1, b2 are compared with respect to threshold value 112, and in which the state of transistor 301 and/or the load (i.e., load 350) is inferred from the comparison.

The routine shown in fig. 6 begins in block 600. In a following block 602, the internal control output 316 is operated in such a way that the transistor 301 is controlled into the conductive state. Next, a predefined period of time is waited, wherein the period of time is predefined, for example, depending on the characteristics of the transistor 301 and/or the load 350. At the same time (as long as it has not already been done), the current source 152 of the input interface circuit 100 is activated.

In a following block 604, the internal control output 316 and therefore the output interface circuit 200 are operated for a short period of time in such a way that the transistor 301 is controlled into a non-conducting state. The monitoring is then carried out in view of a possible disconnection aspect of the load 350, for example as it has already been described in detail above with reference to fig. 5.

In a following block 606, the internal control output 316 and thus the output interface circuit 200 are operated for a short period of time in such a way that the transistor 301 is again controlled into the conductive state. Thereby ending the routine shown in fig. 6.

Fig. 7 shows a flowchart of a method for improving the accuracy of the monitoring ("short recognition") in view of an inadmissibly high current in the transistor 301:

-in block 700: operating transistor 301 operated by integrated semiconductor circuit 10 using a known current;

-in block 702: determining the respective associated residual voltage (RDSon) at the transistor 301;

-in block 704: storing the measured values of the current and the residual voltage and/or other parameters in a memory of the integrated semiconductor circuit 10;

-in block 706: storing a temperature model characterizing the current and the residual voltage in a memory of the integrated semiconductor circuit 10;

in block 708: the threshold 112 that can be specified is compensated for on the basis of the temperature of the integrated semiconductor circuit 10 during operation of the integrated semiconductor circuit 10 and a temperature model in order to improve the monitoring accuracy.

Claims

1. An integrated semiconductor circuit (10) for operating a transistor (301), wherein the integrated semiconductor circuit (10) has an output interface circuit (200) having an output terminal (a), wherein the output terminal (a) is connectable with a control terminal (302) of the transistor (301), and wherein the integrated semiconductor circuit (10) has a first input interface circuit (100) having a first input terminal (b 1), wherein the first input terminal (b 1) is connectable with a first terminal (304) of the transistor (301) which is different from the control terminal (302), characterized in that the integrated semiconductor circuit (10) has means (310) for operating the output interface circuit (200) as a function of an electrical signal on the first input terminal (b 1) of the first input interface circuit (100), wherein the device (310) comprises at least one delay device (312) to delay in time at least one signal (314).

2. An integrated semiconductor circuit (10) as claimed in claim 1, wherein the means (310) are implemented as a hardware circuit and are integrated into the integrated semiconductor circuit (10).

3. An integrated semiconductor circuit (10) as claimed in any one of the preceding claims, wherein the integrated semiconductor circuit has a second input interface circuit (100') having a second input terminal (b 2), and wherein the second input terminal (b 2) is connectable to a second terminal (306) of the transistor (301) different from the control terminal (302).

4. An integrated semiconductor circuit (10) as claimed in claim 3, wherein the first and/or the second input interface circuit (100, 100') comprises a comparator (110) with a predeterminable threshold value (112) or a transistor arrangement with different switching thresholds or an analog-digital converter.

5. An integrated semiconductor circuit (10) as claimed in claim 3, wherein the first and/or the second input interface circuit (100, 100') comprises a current source (152) which cooperates with the first or the second input terminal (b 1, b 2).

6. An integrated semiconductor circuit (10) as claimed in any of claims 1 to 2, wherein the means (310) comprises at least one of the following elements: digital gates (318, 320), one-shot stages (312), two-shot stages, shift registers, ohmic resistors, capacitors, inductors, delay lines.

7. The integrated semiconductor circuit (10) of any of claims 1 to 2, the device (310) comprises an OR gate (318), an AND gate (320) and a monostable trigger stage (312), and wherein an output of said input interface circuit (100) is connected to a first input (120) of said OR-gate (318), and wherein an internal manipulation output (316) of said integrated semiconductor circuit (10) is connected to an input of said one shot stage (312), and wherein an output of said one shot stage (312) is connected to a second input of said OR gate (318), and wherein said internal control output (316) is connected to a first input of said AND gate (320), and wherein an output of said OR gate (318) is connected to a second input of said AND gate (320), and wherein an output (220) of the and gate (320) is connected to an input of the output interface circuit (200).

8. An integrated semiconductor circuit (10) as claimed in claim 1, wherein the integrated semiconductor circuit (10) is a microcontroller.

9. A circuit arrangement (300) with an integrated semiconductor circuit (10) as claimed in any one of the preceding claims, wherein the circuit arrangement (300) comprises at least one transistor (301), and wherein a control terminal (302) of the transistor (301) is connected with the output terminal (a) of the output interface circuit (200), and wherein a first terminal of the transistor (301) is connected with the first input terminal (b 1) of the first input interface circuit (100).

10. A circuit arrangement (300) as claimed in claim 9, wherein the respective connection between the output terminal (a) or the first input terminal (b 1) and the transistor (301) comprises only passive electric devices.

11. A method for operating an integrated semiconductor circuit (10) for operating a transistor (301), wherein the integrated semiconductor circuit (10) has an output interface circuit (200) having an output terminal (a), and wherein the output terminal (a) is connectable to a control terminal (302) of the transistor (301), and wherein the integrated semiconductor circuit (10) has a first input interface circuit (100) having a first input terminal (b 1), and wherein the first input terminal (b 1) is connectable to a first terminal of the transistor (301) which is different from the control terminal (302), characterized in that the integrated semiconductor circuit (10) has a circuit for operating the output interface circuit (200) depending on an electrical signal on the first input terminal (b 1) of the first input interface circuit (100) And wherein said output interface circuit (200) is operated in dependence on an electrical signal at said first input terminal (b 1) of said input interface circuit (100), wherein said apparatus (310) comprises at least one delay means (312) for delaying in time at least one signal (314).

12. Method for operating an integrated semiconductor circuit (10) as claimed in claim 11, wherein the integrated semiconductor circuit has a second input interface circuit (100') which has a second input terminal (b 2), and wherein the second input terminal (b 2) can be connected to a second terminal (306) of the transistor (301) which is different from the control terminal (302), wherein a voltage applied to the first and/or second input terminal (b 1, b 2) is compared with respect to a threshold value (112) when the transistor (301) is controlled into a conductive state by means of an output terminal (a), and wherein the result of the comparison is masked for a predefinable time as a function of a signal (314) at an internal control output (316) of the integrated semiconductor circuit (10), and wherein the result of the comparison is used to evaluate the operating state of the transistor (301), and wherein the output interface circuit (200) is operated in the presence of an impermissibly high current such that the transistor (301) is controlled into a non-conductive state.

13. Method for operating an integrated semiconductor circuit (10) as claimed in claim 12, wherein the result of the comparison is used to identify an impermissibly high current flowing through the transistor (301).

14. Method for operating an integrated semiconductor circuit (10) as claimed in claim 12, wherein the respective current source (152) interacting with the first or second input terminal (b 1, b 2) is switched on when the transistor (301) is controlled into a non-conductive state by means of the output terminal (a), and wherein the voltage applied to the respective first or second input terminal (b 1, b 2) is compared with respect to a threshold value (112), and wherein the state of a load (350) connected to the transistor (301) is deduced from the comparison.

15. Method for operating an integrated semiconductor circuit (10) as claimed in claim 12, wherein the output interface circuit (200) is operated for a short period of time when the transistor (301) is controlled into a conducting state by means of the output terminal (a), such that the transistor (301) is controlled or can be controlled into a non-conducting state, and wherein the short period of time is smaller than a reaction time of an electrical consumer (350) connected to the transistor (301) and/or wherein the short period of time is in the range of the reaction time of the transistor (301), and wherein the voltages applied at the first or second input terminals (b 1, b 2) are compared with respect to a threshold value (112), and wherein the state of the transistor (301) and/or the consumer (350) is deduced from the comparison.

16. The method of claim 12, wherein the method comprises the steps of:

-operating a transistor (301) operated by the integrated semiconductor circuit (10) with a known current in the transistor (301);

-determining the respectively associated residual voltage at the transistor (301);

-storing the measured value pairs and/or other parameters of the current and the residual voltage in a memory of the integrated semiconductor circuit (10);

-storing a temperature model characterizing the current and the residual voltage in a memory of the integrated semiconductor circuit (10);

-compensating the threshold (112) according to a temperature of the integrated semiconductor circuit (10) and according to the temperature model.