CN108768347B - Slope generator and compensation circuit thereof - Google Patents
Slope generator and compensation circuit thereof Download PDFInfo
- Publication number
- CN108768347B CN108768347B CN201810680813.8A CN201810680813A CN108768347B CN 108768347 B CN108768347 B CN 108768347B CN 201810680813 A CN201810680813 A CN 201810680813A CN 108768347 B CN108768347 B CN 108768347B
- Authority
- CN
- China
- Prior art keywords
- input end
- switch
- control module
- compensation circuit
- reference voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K4/00—Generating pulses having essentially a finite slope or stepped portions
- H03K4/06—Generating pulses having essentially a finite slope or stepped portions having triangular shape
- H03K4/08—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape
- H03K4/48—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices
Landscapes
- Electronic Switches (AREA)
Abstract
The invention relates to the technical field of power electronics, in particular to a slope generator and a compensation circuit thereof, which comprise: the ramp generation module comprises a MOS tube for outputting a ramp signal through a source electrode or a drain electrode; a charging control module; the charging control module compares the voltage at the serial node with a first reference voltage received by a first reference input end and controls the on-off of the first switch according to a comparison result; a discharge control module; the discharge control module compares the voltage at the serial node with a second reference voltage received by a second reference input end and controls the on-off of a second switch according to a comparison result; the interval formed between the first reference voltage and the second reference voltage corresponds to a proportional variation interval of a parasitic capacitance curve of the MOS tube; the slope generator adopting the MOS tube can be compensated, and the slope generator is prevented from being influenced by nonlinear change of grid capacitance of the MOS tube along with grid voltage.
Description
Technical Field
The invention relates to the technical field of power electronics, in particular to a slope generator and a compensation circuit thereof.
Background
The ramp generator is a device commonly used in power electronics technology for generating a ramp signal. With the development of semiconductor processes, the cost of semiconductor devices is gradually reduced, so that they can be applied to ramp generators. In a ramp generator using a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), since the unit area capacitance value of the gate capacitance Cgs of the MOS Transistor varies with the magnitude of the gate voltage Vgs, and the variation is non-proportional throughout the variation range, the output of the ramp generator is greatly affected.
Disclosure of Invention
In view of the above problem, the present invention provides a compensation circuit for a ramp generator, including:
the ramp generation module comprises a first switch and a second switch which are connected between a power supply and the ground in series, wherein the first switch and the second switch are connected in series to form a series node;
the slope generation module further comprises an MOS tube for outputting a slope signal through a source electrode or a drain electrode, and a grid electrode of the MOS tube is connected with the series node;
the charging control module comprises a first input end, a first reference input end and a first output end, the first input end is connected with the series node, and the first output end is connected with the first switch;
the charging control module compares the voltage at the serial node with a first reference voltage received by the first reference input end and controls the on-off of the first switch according to a comparison result;
the discharge control module comprises a second input end, a second reference input end and a second output end, the second input end is connected with the series node, and the second output end is connected with the second switch;
the discharge control module compares the voltage at the serial node with a second reference voltage received by a second reference input end and controls the on-off of the second switch according to a comparison result;
and the interval formed between the first reference voltage and the second reference voltage corresponds to the proportional change interval of the parasitic capacitance curve of the MOS tube.
The above compensation circuit, wherein the charging control module comprises:
a positive phase input end of the first comparison unit is used as the first input end and connected with the series node, and an inverted phase input end of the first comparison unit receives the first reference voltage;
the input end of the first control unit is connected with the comparison output end of the first comparison unit, and the output end of the first control unit is connected with the first switch, so that the on-off of the first switch is controlled according to the comparison result of the first comparison unit.
The above compensation circuit, wherein the discharge control module comprises:
a second comparing unit, a positive phase input end of which is used as the second input end and connected with the series node, and an inverted phase input end of which receives the second reference voltage;
the input end of the second control unit is connected with the comparison output end of the second comparison unit, and the output end of the second control unit is connected with the second switch, so that the on-off of the second switch is controlled according to the comparison result of the second comparison unit.
In the compensation circuit, the first control unit further has a first clock input port, and the first clock input port is used for receiving a clock signal; and
the second control unit also has a second clock input port for receiving the clock signal.
In the compensation circuit, the first reference voltage is 3-4V.
In the compensation circuit, the second reference voltage is 4.5-5.5V.
In the above compensation circuit, the MOS transistor is an NMOS transistor.
In the above compensation circuit, the substrate of the NMOS transistor is grounded.
A ramp generator employing a compensation circuit as claimed in any one of the preceding claims.
Has the advantages that: the slope generator and the compensation circuit thereof can compensate the slope generator adopting the MOS tube, and avoid the slope generator from being influenced by the nonlinear change of the grid capacitance of the MOS tube along with the grid voltage.
Drawings
FIG. 1 is a schematic circuit diagram of a compensation circuit of a ramp generator according to an embodiment of the present invention;
FIG. 2 is a graph of gate capacitance versus gate voltage according to an embodiment of the present invention;
fig. 3 is a waveform diagram of a ramp signal and a conventional ramp signal according to an embodiment of the present invention.
Detailed Description
The invention is further illustrated with reference to the following figures and examples.
Example one
In a preferred embodiment, as shown in fig. 1, a compensation circuit of a ramp generator is provided, which includes:
the ramp generating module 10 comprises a first switch SW1 and a second switch SW2 connected in series between a power supply VDD and the ground, wherein the first switch SW1 and the second switch SW2 are connected in series to form a series node n;
the ramp generating module 10 further includes a MOS transistor M1 for outputting a ramp signal through the source or the drain, and the gate of the MOS transistor M1 is connected to the series node n;
a charging control module 20, including a first input terminal, a first reference input terminal and a first output terminal, the first input terminal being connected to the series node n, the first output terminal being connected to the first switch SW 1;
the charging control module 20 compares the voltage at the series node n with a first reference voltage Vref1 received at a first reference input terminal, and controls the on/off of the first switch SW1 according to the comparison result;
the discharge control module 30 comprises a second input end, a second reference input end and a second output end, wherein the second input end is connected with the series node n, and the second output end is connected with the second switch SW 2;
the discharge control module 30 compares the voltage at the series node n with a second reference voltage Vref2 received by a second reference input terminal, and controls the on/off of a second switch SW2 according to the comparison result;
the interval formed between the voltage values of the first reference voltage Vref1 and the second reference voltage Vref2 corresponds to a proportional variation interval of a parasitic capacitance curve of the MOS transistor M1.
In the above technical solution, the source and/or the drain of the MOS transistor M1 in the ramp generating module 10 may also be connected with other elements for generating a ramp signal, which is a conventional technical means in the field and is not described herein again; under the control of the charging control module 20 and the discharging control module 30, the first switch SW1 and the second switch SW2 should be turned on alternately, so that the MOS transistor M1 can generate the current/voltage required for forming the ramp signal between the source and the drain; the first switch SW1 and the second switch SW2 can be implemented by MOS transistors.
In a preferred embodiment, the charging control module 20 may include:
a first comparing unit CP1, wherein a non-inverting input terminal of the first comparing unit CP1 is connected to the series node n as a first input terminal, and an inverting input terminal receives a first reference voltage Vref 1;
an input end of the first control unit CT1, an input end of the first control unit CT1 is connected to the comparison output end of the first comparison unit CP1, and an output end of the first control unit CT1 is connected to the first switch SW1, so as to control the on/off of the first switch SW1 according to the comparison result of the first comparison unit CP 1.
In the above embodiment, preferably, the discharge control module 30 may include:
a second comparing unit CP2, a non-inverting input terminal of the second comparing unit CP2 being connected as a second input terminal to the series node n, an inverting input terminal of the second comparing unit CP2 receiving a second reference voltage Vref 2;
an input end of the second control unit CT2, an input end of the second control unit CT2 is connected to the comparison output end of the second comparison unit CP2, and an output end of the second control unit CT2 is connected to the second switch SW2, so as to control on/off of the second switch SW2 according to the comparison result of the second comparison unit CT 2.
In the above technical solution, the signals output by the output terminals of the first control unit CT1 and the second control unit CT2 may be pulse signals that are opposite in phase to each other.
In the above embodiment, preferably, the first control unit CT1 may further have a first clock input port, the first clock input port being configured to receive a first clock signal ck 1; and
the second control unit CT2 also has a second clock input port for receiving a second clock signal ck 2.
In the above technical solution, the first clock signal ck1 and the second clock signal ck2 may be the same clock signal.
In a preferred embodiment, the first reference voltage is 3-4V (volts), for example, 3.2V, 3.4V, 3.5V, 3.6V, or 3.8V.
In a preferred embodiment, the second reference voltage is 4.5-5.5V, for example, 4.7V, 4.9V, 5.1V, 5.2V, or 5.3V.
In a preferred embodiment, the MOS transistor M1 may be an NMOS transistor.
In a preferred embodiment, the substrate of the NMOS transistor M1 is grounded.
Example two
In a preferred embodiment, a ramp generator is also provided, which may employ any of the compensation circuits described above.
For example, as shown in fig. 2, the slope generator of the present invention can be used to control the parasitic capacitance curve of the MOS transistor M1 between the proportional change sections AB, so as to implement compensation for the slope generator.
As shown in fig. 3, the ramp signal waveform a 'of the present invention can be improved compared to the conventional ramp signal waveform B'.
In summary, the present invention provides a ramp generator and a compensation circuit thereof, including: the ramp generation module comprises a first switch and a second switch which are connected between a power supply and the ground in series, and a series node is formed at the serial connection position of the first switch and the second switch; the slope generation module also comprises an MOS tube used for outputting a slope signal through a source electrode or a drain electrode, and the grid electrode of the MOS tube is connected with the series node; the charging control module comprises a first input end, a first reference input end and a first output end, wherein the first input end is connected with the series node, and the first output end is connected with the first switch; the charging control module compares the voltage at the serial node with a first reference voltage received by a first reference input end and controls the on-off of the first switch according to a comparison result; the discharge control module comprises a second input end, a second reference input end and a second output end, the second input end is connected with the series node, and the second output end is connected with the second switch; the discharge control module compares the voltage at the serial node with a second reference voltage received by a second reference input end and controls the on-off of a second switch according to a comparison result; the interval formed between the first reference voltage and the second reference voltage corresponds to a proportional variation interval of a parasitic capacitance curve of the MOS tube; the slope generator adopting the MOS tube can be compensated, and the slope generator is prevented from being influenced by nonlinear change of grid capacitance of the MOS tube along with grid voltage.
While the specification concludes with claims defining exemplary embodiments of particular structures for practicing the invention, it is believed that other modifications will be made in the spirit of the invention. While the above invention sets forth presently preferred embodiments, these are not intended as limitations.
Various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above description. Therefore, the appended claims should be construed to cover all such variations and modifications as fall within the true spirit and scope of the invention. Any and all equivalent ranges and contents within the scope of the claims should be considered to be within the intent and scope of the present invention.
Claims (9)
1. A compensation circuit for a ramp generator, comprising:
the ramp generation module comprises a first switch and a second switch which are connected between a power supply and the ground in series, wherein the first switch and the second switch are connected in series to form a series node;
the slope generation module further comprises an MOS tube for outputting a slope signal through a source electrode or a drain electrode, and a grid electrode of the MOS tube is connected with the series node;
the charging control module comprises a first input end, a first reference input end and a first output end, the first input end is connected with the series node, and the first output end is connected with the first switch;
the charging control module compares the voltage at the serial node with a first reference voltage received by the first reference input end and controls the on-off of the first switch according to a comparison result;
the discharge control module comprises a second input end, a second reference input end and a second output end, the second input end is connected with the series node, and the second output end is connected with the second switch;
the discharge control module compares the voltage at the serial node with a second reference voltage received by a second reference input end and controls the on-off of the second switch according to a comparison result;
the interval formed between the first reference voltage and the second reference voltage corresponds to a proportional variation interval of a parasitic capacitance curve of the MOS tube;
under the control of the charging control module and the discharging control module, the first switch and the second switch are alternately conducted, so that the MOS tube generates current or voltage required for forming a ramp signal between the source electrode and the drain electrode.
2. The compensation circuit of claim 1, wherein the charge control module comprises:
a positive phase input end of the first comparison unit is used as the first input end and connected with the series node, and an inverted phase input end of the first comparison unit receives the first reference voltage;
the input end of the first control unit is connected with the comparison output end of the first comparison unit, and the output end of the first control unit is connected with the first switch, so that the on-off of the first switch is controlled according to the comparison result of the first comparison unit.
3. The compensation circuit of claim 2, wherein the discharge control module comprises:
a second comparing unit, a positive phase input end of which is used as the second input end and connected with the series node, and an inverted phase input end of which receives the second reference voltage;
the input end of the second control unit is connected with the comparison output end of the second comparison unit, and the output end of the second control unit is connected with the second switch, so that the on-off of the second switch is controlled according to the comparison result of the second comparison unit.
4. The compensation circuit of claim 3, wherein the first control unit further has a first clock input port for receiving a clock signal; and
the second control unit also has a second clock input port for receiving the clock signal.
5. The compensation circuit of claim 1, wherein the first reference voltage is 3-4V.
6. The compensation circuit of claim 1, wherein the second reference voltage is 4.5-5.5V.
7. The compensation circuit of claim 1, wherein the MOS transistor is an NMOS transistor.
8. The compensation circuit of claim 7, wherein the substrate of the NMOS transistor is grounded.
9. A ramp generator, characterized in that a compensation circuit as claimed in any one of claims 1 to 8 is applied.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810680813.8A CN108768347B (en) | 2018-06-27 | 2018-06-27 | Slope generator and compensation circuit thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810680813.8A CN108768347B (en) | 2018-06-27 | 2018-06-27 | Slope generator and compensation circuit thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108768347A CN108768347A (en) | 2018-11-06 |
| CN108768347B true CN108768347B (en) | 2022-04-01 |
Family
ID=63974189
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810680813.8A Active CN108768347B (en) | 2018-06-27 | 2018-06-27 | Slope generator and compensation circuit thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108768347B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20120037757A (en) * | 2010-10-12 | 2012-04-20 | 삼성전기주식회사 | Relaxation oscillator |
| CN103825433A (en) * | 2014-02-27 | 2014-05-28 | 成都芯源系统有限公司 | Switch converter and control circuit thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI441005B (en) * | 2012-05-24 | 2014-06-11 | Richtek Technology Corp | Constant on time mode power supplier for improving load transient and method thereof |
-
2018
- 2018-06-27 CN CN201810680813.8A patent/CN108768347B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20120037757A (en) * | 2010-10-12 | 2012-04-20 | 삼성전기주식회사 | Relaxation oscillator |
| CN103825433A (en) * | 2014-02-27 | 2014-05-28 | 成都芯源系统有限公司 | Switch converter and control circuit thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108768347A (en) | 2018-11-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7427889B2 (en) | Voltage regulator outputting positive and negative voltages with the same offsets | |
| US8643443B1 (en) | Comparator and relaxation oscillator employing same | |
| JP5026368B2 (en) | Circuit and method for gate control circuit with reduced voltage stress | |
| US20090315530A1 (en) | Pulse controlled soft start scheme for buck converter | |
| US7142028B2 (en) | Clock duty ratio correction circuit | |
| US7535284B2 (en) | Switching control circuit | |
| WO2019116825A1 (en) | Gate drive circuit | |
| KR101353670B1 (en) | Triangular wave generation circuit | |
| JP2015180061A (en) | Apparatus and methods for input bias current reduction | |
| US20070052452A1 (en) | Sample/hold circuit module | |
| JP2011152014A (en) | Dc/dc converter circuit | |
| US9354647B2 (en) | Adjustable reference current generating circuit and method for driving the same | |
| US20230387105A1 (en) | Device with a High Efficiency Voltage Multiplier | |
| CN108768347B (en) | Slope generator and compensation circuit thereof | |
| US9768685B2 (en) | Bootstrap circuit | |
| CN112994659A (en) | Relaxation oscillator and method of controlling a relaxation oscillator | |
| US10873256B1 (en) | Charge-pump boosting circuit | |
| KR20030072527A (en) | Generator of dc-dc converter | |
| US8604845B2 (en) | Triangular wave generator and method generating triangular wave thereof | |
| US9065433B2 (en) | Capacitor charging circuit with low sub-threshold transistor leakage current | |
| JPH09261016A (en) | Trapezoidal wave signal output device | |
| CN112152446B (en) | Charge pump booster circuit | |
| US9473018B2 (en) | High efficiency voltage level multiplier | |
| US7898350B2 (en) | Frequency stabilizing device of an oscillator | |
| CN113014240B (en) | Control circuit of signal switch tube and analog switch circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |