CN108763105B - Method and device for improving writing performance of solid-state storage equipment and computer equipment - Google Patents
Method and device for improving writing performance of solid-state storage equipment and computer equipment Download PDFInfo
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Abstract
The invention relates to a method, a device and computer equipment for improving the writing performance of solid-state storage equipment, wherein the method comprises the steps of receiving a writing request; judging whether the read-write units in the current group of erasing units are distributed completely; if yes, distributing a group of new erasing units; updating a Meta template of the NAND controller; if not, directly entering the next step; distributing read-write units from the current erasing unit; generating a command descriptor; and submitting the command descriptor to the NAND controller to complete the write request. According to the method, when the new erasing unit is distributed and user data is written, the Meta template of the NAND controller is updated, Meta information is not generated, after the command descriptor is generated, the command descriptor is submitted to the NAND controller according to the command descriptor, and the generation of the Meta information is completed by using ASIC logic, so that the write command processing time is reduced, and the write performance of the solid-state storage device is improved.
Description
Technical Field
The invention relates to a solid state disk, in particular to a method and a device for improving the writing performance of a solid state storage device and a computer device.
Background
For the SSD system, the logical address and the physical address are not statically bound, so the SSD needs to store additional information while writing the user data into the NAND, so that the mapping relationship can be reconstructed at the system initialization stage. This additional stored information is referred to as Meta information, which is typically generated by software in the SSD and stored in the lower access speed DRAM.
For the SSD system described above, the whole write request processing flow is as follows: the system receives a write request, judges whether the read-write units in a group of erasing units are distributed completely, if so, distributes a group of new erasing units and distributes the read-write units in the current erasing unit, if not, directly distributes the read-write units in the current erasing unit, generates Meta information and a write request descriptor after distributing the read-write units, submits the descriptor to the NAND controller, waits for the NAND controller to complete the write request, and becomes a write performance bottleneck in a high-performance solid-state storage device because the software generates the Meta information when time is long.
Therefore, it is necessary to design a new write request processing method to reduce the write command processing time and improve the write performance of the solid-state storage device.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a method and a device for improving the writing performance of a solid-state storage device and a computer device.
In order to achieve the purpose, the invention adopts the following technical scheme: a method for improving write performance of a solid-state storage device, the method comprising:
receiving a write request;
judging whether the read-write units in the current group of erasing units are distributed completely;
if yes, distributing a group of new erasing units;
updating a Meta template of the NAND controller;
distributing read-write units from the current erasing unit;
generating a command descriptor;
submitting the command descriptor to the NAND controller to complete the write request, specifically, after submitting the command descriptor to the NAND controller, finding a matched template by the ASIC according to the project command, and automatically generating Meta information according to the matched template and information in advance from the project command;
if not, executing the read-write unit distributed from the current erasing unit;
the Meta template comprises fixed information and variable information, one Meta template comprises eight bytes, and the eight bytes are distributed as follows: the first four bytes are used for writing fixed information; the middle four bytes are used for writing variable information, and the last four bytes are used for writing variable information, wherein the fixed information is specified when the Meta template is generated by software; and the variable information is extracted from the command descriptor when performing the generation Meta with the ASIC;
the command descriptor comprises erasing unit information, command attribute and content, and the erasing unit information, the command attribute and the content are combined into a character string according to a certain sequence;
the step of submitting the command descriptor to the NAND controller to complete the write request comprises the following specific steps:
judging whether the command descriptor is a write command descriptor;
if yes, generating Meta information according to the Meta template and the command descriptor;
if not, entering the ending step;
the step of generating Meta information according to the Meta template and the command descriptor comprises the following specific steps:
judging whether Meta information can be generated according to the Meta template;
if yes, extracting erasure unit information from the command descriptor;
acquiring a Meta template according to the erasing unit information;
generating Meta information according to the Meta template;
the erasing unit information comprises a physical address, a logical address and a time stamp of the erasing unit; after the step of judging whether the Meta information can be generated according to the Meta template, the method further comprises the following steps:
if not, the software generates Meta information.
The invention also provides a device for improving the writing performance of the solid-state storage equipment, which comprises a receiving unit, an allocation judging unit, a new allocation unit, an updating unit, a reading and writing allocation unit, a descriptor generating unit and a submitting unit;
the receiving unit is used for receiving a write request;
the distribution judging unit is used for judging whether the read-write units in the current group of erasing units are distributed completely; if not, executing the read-write unit distribution from the current erasing unit;
the new distribution unit is used for distributing a group of new erasing units if the number of the erasing units is equal to the number of the erasing units;
the updating unit is used for updating a Meta template of the NAND controller;
the read-write distribution unit is used for distributing the read-write unit from the current erasing unit;
the descriptor generating unit is used for generating a command descriptor;
the submitting unit is used for submitting the command descriptor to the NAND controller to complete the writing request, and specifically, after the command descriptor is submitted to the NAND controller, the ASIC finds a matched template according to the project command and automatically generates Meta information according to the matched template and information in advance from the project command;
the Meta template comprises fixed information and variable information, one Meta template comprises eight bytes, and the eight bytes are distributed as follows: the first four bytes are used for writing fixed information; the middle four bytes are used for writing variable information, and the last four bytes are used for writing variable information, wherein the fixed information is specified when the Meta template is generated by software; and the variable information is extracted from the command descriptor when performing the generation Meta with the ASIC;
the command descriptor comprises erasing unit information, command attribute and content, and the erasing unit information, the command attribute and the content are combined into a character string according to a certain sequence;
the submitting unit comprises an attribute judging module and an information generating module;
the attribute judging module is used for judging whether the command descriptor is a write command descriptor;
the information generation module is used for generating Meta information according to the Meta template and the command descriptor if the Meta information is generated;
the information generation module comprises a template judgment submodule, an information extraction submodule, a template acquisition submodule and a generation submodule;
the template judgment submodule is used for judging whether Meta information can be generated according to the Meta template;
the information extraction submodule is used for extracting the information of the erasing unit from the command descriptor if the information of the erasing unit is extracted from the command descriptor;
the template obtaining submodule is used for obtaining a Meta template according to the erasing unit information;
the generation submodule is used for generating Meta information according to the Meta template;
the erasing unit information comprises a physical address, a logical address and a time stamp of the erasing unit;
the information generation module also comprises a software generation submodule;
and the software generation sub-module is used for generating Meta information by software. The invention also provides a computer device, which comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor implements the method for improving the writing performance of the solid-state storage device when executing the computer program.
Compared with the prior art, the invention has the beneficial effects that: according to the method for improving the writing performance of the solid-state storage device, the Meta template of the NAND controller is updated when a new erasing unit is distributed and user data is written, Meta information is not generated, after a command descriptor is generated, the command descriptor is submitted to the NAND controller, and the generation of the Meta information is completed by using ASIC logic, so that the writing command processing time is reduced, and the writing performance of the solid-state storage device is improved.
The invention is further described below with reference to the accompanying drawings and specific embodiments.
Drawings
Fig. 1 is a flowchart of a method for improving write performance of a solid-state storage device according to an embodiment of the present invention;
FIG. 2 is a flow diagram of the commit command descriptor of FIG. 1 to a NAND controller completing a write request;
FIG. 3 is a flowchart of FIG. 2 for generating Meta information from a Meta template and command descriptors;
fig. 4 is a block diagram illustrating an apparatus for improving write performance of a solid-state storage device according to an embodiment of the present invention;
FIG. 5 is a block diagram of a commit unit according to the embodiment of FIG. 4;
fig. 6 is a block diagram of an information generating module provided in the embodiment of fig. 4;
fig. 7 is a schematic block diagram of a computer device according to an embodiment of the present invention.
Detailed Description
In order to more fully understand the technical content of the present invention, the technical solution of the present invention will be further described and illustrated with reference to the following specific embodiments, but not limited thereto.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the specification of the present application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
As shown in specific embodiments of fig. 1 to 7, the method, the apparatus, and the computer device for improving write performance of a solid-state storage device provided in this embodiment can be applied to a process of processing a write request by a solid-state storage device such as a fixed hard disk, so as to reduce write command processing time and improve write performance of the solid-state storage device.
As shown in fig. 1, the present embodiment provides a method for improving write performance of a solid-state storage device, where the method includes steps S1 to S7:
and S1, receiving a write request.
A write data request is initiated by a user, and the solid-state storage device receives a write request to write user data to the NAND.
S2, judging whether the read-write unit in the current group of erasing units is distributed completely.
Specifically, when the cache erase unit is full, the cache erase unit needs to be reallocated for writing of user data.
S3, if yes, a new group of erasing units is distributed.
And S4, updating the Meta template of the NAND controller.
When processing a write request, software updates Meta template information when distributing a group of new erasing units without generating Meta information, and the generation of Meta information is completed by ASIC logic in FLASH, thereby avoiding the problems of reducing the access speed of DRAM and influencing write bandwidth.
Whenever a new set of erase units is allocated, the Meta template of the NAND controller needs to be updated, indicating that a new set of erase units has been established, requiring the Meta template to cooperate in writing user data.
And S5, distributing the read-write unit from the current erasing unit.
When user data is written, the user data is written into the read-write unit first, and the particles of the storage unit of the user data are refined, so that subsequent calling or maintenance is facilitated.
And S6, generating a command descriptor.
In this embodiment, the command descriptor includes the erasure unit information and the attribute and content of the command, and these three pieces of information are combined into a character string in a certain order, similar to the character string in the form of erasure unit information + command attribute + command content, etc.
And S7, submitting the command descriptor to the NAND controller to complete the write request.
After the command descriptor is submitted to the NAND controller, the ASIC finds out a matched template according to the project command, and then automatically generates Meta information according to the matched template and the information in advance from the project command.
From the command descriptor submitted to the NAND controller, it can be determined whether Meta is generated by software or automatically by the NAND controller.
If not, the step S5 is executed.
Specifically, as shown in fig. 2, the step S7, submitting the command descriptor to the NAND controller, completing the write request, includes the following steps S71 to S72:
s71, judging whether the command descriptor is a write command descriptor.
Specifically, the command descriptor is analyzed from its composition, for example, characters of non-command attribute are removed, the attribute characters of the command are left, and the attribute of the command is analyzed by means of language analysis and other technical means.
And S72, if yes, generating Meta information according to the Meta template and the command descriptor.
And acquiring a Meta template matched with the erasing unit information according to the erasing unit information in the command descriptor, and generating the Meta information by combining user data, wherein the step is completed by ASIC logic in a FLASH placed in the NAND controller.
Specifically, it is determined whether the Meta information is generated by software or automatically by the NAND controller, by a command descriptor submitted to the NAND controller.
If not, entering the ending step.
In addition, the step of generating Meta information from the Meta template and the command descriptor in the above step S72 includes steps S721 to S724:
s721, judging whether the Meta information can be generated according to the Meta template.
In this embodiment, the Meta template includes fixed information and variable information. One Meta template consists of eight bytes, which are distributed as follows: the first four bytes are used for writing fixed information; the middle four bytes are used for writing variable information, and the last four bytes are used for writing variable information, wherein the fixed information is specified when the Meta template is generated by software, such as a time stamp of an erasing unit; and the variable information is extracted from a command descriptor, such as a logical address, which is erasure unit information, when the generation Meta is performed with the ASIC.
And S722, if yes, extracting the erasing unit information from the command descriptor.
When the Meta information can be generated according to the Meta template, the erasure unit information is extracted from the command descriptor, and the erasure unit information comprises the following steps: the physical address, the logical address and the time stamp of the erasing unit are known from the physical address.
And S723, acquiring the Meta template according to the erasing unit information.
After the affiliated erasure unit is known, the Meta template matched with the erasure unit can be obtained.
And S724, generating Meta information according to the Meta template.
And forming Meta information according to the content of the Meta template.
And the customized ASIC logic is used for replacing a general controller to complete the generation of Meta information, so that the write command processing time is reduced, and the write performance of the solid-state storage device is improved.
In addition, after the step of determining whether or not the Meta information can be generated according to the Meta template in the step of S721, the method further includes:
and S725, if not, generating Meta information by the software.
When the Meta information can not be generated by using the Meta template, the Meta information is generated by adopting a software generation mode.
According to the method for improving the writing performance of the solid-state storage device, the Meta template of the NAND controller is updated when the new erasing unit is allocated to write user data, Meta information is not generated, the command descriptor is submitted to the NAND controller according to the command descriptor after being generated, and the generation of the Meta information is completed by using ASIC logic, so that the writing command processing time is reduced, and the writing performance of the solid-state storage device is improved.
Referring to fig. 4, fig. 4 is a schematic block diagram of an apparatus for improving write performance of a solid-state storage device according to the present embodiment. As shown in fig. 4, the apparatus for improving write performance of a solid-state storage device includes a receiving unit 1, an allocation judging unit 2, a new allocating unit 3, an updating unit 4, a read-write allocating unit 5, a descriptor generating unit 6, and a submitting unit 7.
A receiving unit 1 for receiving a write request.
And the distribution judging unit 2 is used for judging whether the read-write units in the current group of erasing units are distributed completely, and if not, executing the distribution of the read-write units from the current erasing unit.
And a new allocation unit 3, configured to allocate a new group of erase units if yes.
And the updating unit 4 is used for updating the Meta template of the NAND controller.
And the read-write distribution unit 5 is used for distributing the read-write unit from the current erasing unit.
A descriptor generating unit 6 for generating a command descriptor.
And the submitting unit 7 is used for submitting the command descriptor to the NAND controller to complete the write request.
Specifically, as shown in fig. 5, the submission unit 7 includes an attribute judgment module 71 and an information generation module 72.
And an attribute judging module 71, configured to judge whether the command descriptor is a write command descriptor.
And an information generating module 72, configured to generate Meta information according to the Meta template and the command descriptor if the Meta information is the same as the command descriptor.
In addition, as shown in fig. 6, the information generating module 72 includes a template determining sub-module 721, an information extracting sub-module 722, a template obtaining sub-module 723, and a generating sub-module 724.
The template determining sub-module 721 is configured to determine whether Meta information can be generated according to the Meta template.
And the information extraction submodule 722 is used for extracting the erasure unit information from the command descriptor if the erasure unit information is extracted.
And the template obtaining sub-module 723 is used for obtaining the Meta template according to the erasing unit information.
And a generation submodule 724 for generating Meta information according to the Meta template.
Preferably, the information generating module 72 further includes a software generating submodule 724.
A software generation submodule 724 for generating Meta information by software.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working process of the apparatus and the unit for improving the writing performance of the solid-state storage device described above may refer to the corresponding process in the foregoing method embodiment, and is not described herein again.
The apparatus for improving the writing performance of the solid-state storage device may be implemented in the form of a computer program, and the computer program may be run on a computer device as shown in fig. 7.
According to the device for improving the writing performance of the solid-state storage device, the Meta template of the NAND controller is updated when a new erasing unit is allocated to write user data, Meta information is not generated, after a command descriptor is generated, the command descriptor is submitted to the NAND controller according to the command descriptor, and the generation of the Meta information is completed by using ASIC logic, so that the writing command processing time is reduced, and the writing performance of the solid-state storage device is improved.
Referring to fig. 7, fig. 7 is a schematic block diagram of a computer device according to an embodiment of the present application. The computer device 700 may be a terminal or a server.
Referring to fig. 7, the computer device 700 includes a processor 720, a memory, which may include a non-volatile storage medium 730 and an internal memory 740, and a network interface 750, which are connected by a system bus 710.
The non-volatile storage medium 730 may store an operating system 731 and computer programs 732. The computer programs 732, when executed, enable the processor 720 to perform any of a number of methods for improving write performance of a solid-state storage device.
The processor 720 is used to provide computing and control capabilities, supporting the operation of the overall computer device 700.
The internal memory 740 provides an environment for the execution of the computer program 732 in the non-volatile storage medium 730, and when executed by the processor 720, the computer program 732 may cause the processor 720 to perform any method for improving the write performance of a solid-state storage device.
The network interface 750 is used for network communication such as sending assigned tasks and the like. Those skilled in the art will appreciate that the architecture shown in fig. 7 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing device 700 to which the disclosed aspects apply, as a particular computing device 700 may include more or less components than those shown, or may combine certain components, or have a different arrangement of components. Wherein the processor 720 is configured to execute the program code stored in the memory to perform the following steps:
receiving a write request;
judging whether the read-write units in the current group of erasing units are distributed completely;
if yes, distributing a group of new erasing units;
updating a Meta template of the NAND controller;
if not, directly entering the next step;
distributing read-write units from the current erasing unit;
generating a command descriptor;
and submitting the command descriptor to the NAND controller to complete the write request.
It should be understood that, in the embodiment of the present Application, the Processor 720 may be a Central Processing Unit (CPU), and the Processor 720 may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, and the like. Wherein a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
Those skilled in the art will appreciate that the configuration of computer device 700 depicted in FIG. 7 is not intended to be limiting of computer device 700 and may include more or less components than those shown, or some components in combination, or a different arrangement of components.
According to the computer equipment, when the new erasing unit is distributed and user data is written, the Meta template of the NAND controller is updated, Meta information is not generated, after the command descriptor is generated, the command descriptor is submitted to the NAND controller according to the command descriptor, and the ASIC logic is utilized to complete the generation of the Meta information, so that the write command processing time is reduced, and the write performance of the solid-state storage equipment is improved.
The technical contents of the present invention are further illustrated by the examples only for the convenience of the reader, but the embodiments of the present invention are not limited thereto, and any technical extension or re-creation based on the present invention is protected by the present invention. The protection scope of the invention is subject to the claims.
Claims (3)
1. A method for improving write performance of a solid-state storage device, the method comprising:
receiving a write request;
judging whether the read-write units in the current group of erasing units are distributed completely;
if yes, distributing a group of new erasing units;
updating a Meta template of the NAND controller;
distributing read-write units from the current erasing unit;
generating a command descriptor;
submitting the command descriptor to the NAND controller to complete the write request, specifically, after submitting the command descriptor to the NAND controller, finding a matched template by the ASIC according to the project command, and automatically generating Meta information according to the matched template and information in advance from the project command;
if not, executing the read-write unit distributed from the current erasing unit;
the Meta template comprises fixed information and variable information, one Meta template comprises eight bytes, and the eight bytes are distributed as follows: the first four bytes are used for writing fixed information; the middle four bytes are used for writing variable information, and the last four bytes are used for writing variable information, wherein the fixed information is specified when the Meta template is generated by software; and the variable information is extracted from the command descriptor when performing the generation Meta with the ASIC;
the command descriptor comprises erasing unit information, command attribute and content, and the erasing unit information, the command attribute and the content are combined into a character string according to a certain sequence;
the step of submitting the command descriptor to the NAND controller to complete the write request comprises the following specific steps:
judging whether the command descriptor is a write command descriptor;
if yes, generating Meta information according to the Meta template and the command descriptor;
if not, entering the ending step;
the step of generating Meta information according to the Meta template and the command descriptor comprises the following specific steps:
judging whether Meta information can be generated according to the Meta template;
if yes, extracting erasure unit information from the command descriptor;
acquiring a Meta template according to the erasing unit information;
generating Meta information according to the Meta template;
the erasing unit information comprises a physical address, a logical address and a time stamp of the erasing unit; after the step of judging whether the Meta information can be generated according to the Meta template, the method further comprises the following steps:
if not, the software generates Meta information.
2. The device for improving the writing performance of the solid-state storage equipment is characterized by comprising a receiving unit, an allocation judging unit, a new allocation unit, an updating unit, a reading and writing allocation unit, a descriptor generating unit and a submitting unit;
the receiving unit is used for receiving a write request;
the distribution judging unit is used for judging whether the read-write units in the current group of erasing units are distributed completely; if not, executing the read-write unit distribution from the current erasing unit;
the new distribution unit is used for distributing a group of new erasing units if the number of the erasing units is equal to the number of the erasing units;
the updating unit is used for updating a Meta template of the NAND controller;
the read-write distribution unit is used for distributing the read-write unit from the current erasing unit;
the descriptor generating unit is used for generating a command descriptor;
the submitting unit is used for submitting the command descriptor to the NAND controller to complete the writing request, and specifically, after the command descriptor is submitted to the NAND controller, the ASIC finds a matched template according to the project command and automatically generates Meta information according to the matched template and information in advance from the project command;
the Meta template comprises fixed information and variable information, one Meta template comprises eight bytes, and the eight bytes are distributed as follows: the first four bytes are used for writing fixed information; the middle four bytes are used for writing variable information, and the last four bytes are used for writing variable information, wherein the fixed information is specified when the Meta template is generated by software; and the variable information is extracted from the command descriptor when performing the generation Meta with the ASIC;
the command descriptor comprises erasing unit information, command attribute and content, and the erasing unit information, the command attribute and the content are combined into a character string according to a certain sequence;
the submitting unit comprises an attribute judging module and an information generating module;
the attribute judging module is used for judging whether the command descriptor is a write command descriptor;
the information generation module is used for generating Meta information according to the Meta template and the command descriptor if the Meta information is generated;
the information generation module comprises a template judgment submodule, an information extraction submodule, a template acquisition submodule and a generation submodule;
the template judgment submodule is used for judging whether Meta information can be generated according to the Meta template;
the information extraction submodule is used for extracting the information of the erasing unit from the command descriptor if the information of the erasing unit is extracted from the command descriptor;
the template obtaining submodule is used for obtaining a Meta template according to the erasing unit information;
the generation submodule is used for generating Meta information according to the Meta template;
the erasing unit information comprises a physical address, a logical address and a time stamp of the erasing unit;
the information generation module also comprises a software generation submodule;
and the software generation sub-module is used for generating Meta information by software.
3. A computer device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing the method of improving write performance of a solid state storage device as claimed in claim 1 when executing the computer program.
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