CN108738035B

CN108738035B - Data processing method and device of multi-system baseband chip and processing equipment

Info

Publication number: CN108738035B
Application number: CN201710241639.2A
Authority: CN
Inventors: 刘万江; 刘新良; 李晓莎
Original assignee: Sanechips Technology Co Ltd
Current assignee: Sanechips Technology Co Ltd
Priority date: 2017-04-13
Filing date: 2017-04-13
Publication date: 2021-07-20
Anticipated expiration: 2037-04-13
Also published as: CN108738035A

Abstract

The invention discloses a data processing method, a device and a processing device of a multi-standard baseband chip, wherein the method comprises the following steps: acquiring data to be processed, and determining the system type of the data to be processed; if the data to be processed is first standard data, performing bit level processing on the first standard data through BLA, and performing symbol level processing on the first standard data through xDSP, wherein the symbol level processing process is accelerated through an FFT accelerator when the symbol level processing is performed; and if the data to be processed is second system data, performing bit-level processing on the second system data through BLA, and performing symbol-level processing on the second system data through a UMTS accelerator.

Description

Data processing method and device of multi-system baseband chip and processing equipment

Technical Field

The invention relates to the technical field of mobile communication, in particular to a data processing method, a data processing device and data processing equipment of a multi-system baseband chip based on a multi-core cluster structure.

Background

With the continuous development of wireless communication technology, higher requirements are put forward in the aspects of user data rate, system capacity, base station processing delay, integration level of a baseband board and the like. At present, various large operators have the current situation that multiple communication systems coexist, and the communication systems exist for a long time, and the operators generally adopt a mode that a base station cabinet is inserted with baseband board cards of different systems to realize an integrated base station, so that the construction expenditure of a base station machine room is huge, and the operation and maintenance cost is very high. Operators hope that base station equipment provided by communication equipment providers can support 2G/3G/4G smooth upgrade coexistence, and equipment cabinets are miniaturized, green and low in power consumption, so that equipment investment is reduced, and operation and maintenance cost is reduced.

However, for a hardware chip, the larger the scale is, the higher the complexity is, a reasonable chip architecture and a system scheme are key points for satisfying the leading performance and competitiveness of the chip, and the existing technology has a bottleneck, especially a higher system capacity, and a smaller data processing delay, especially a low-delay processing requirement of multi-user high-speed data in a Long Term Evolution (LTE) system, is a difficult problem to be solved urgently by the current baseband chip.

Disclosure of Invention

In order to solve the technical problem, embodiments of the present invention provide a data processing method, an apparatus, and a processing device for a multi-standard baseband chip, which can meet the requirements of high integration and high performance for multi-standard baseband data.

The data processing method of the multi-system baseband chip provided by the embodiment of the invention comprises the following steps:

acquiring data to be processed, and determining the system type of the data to be processed;

if the data to be processed is first standard data, performing bit level processing on the first standard data through BLA, and performing symbol level processing on the first standard data through xDSP, wherein the symbol level processing process is accelerated through an FFT accelerator when the symbol level processing is performed;

and if the data to be processed is second system data, performing bit-level processing on the second system data through BLA, and performing symbol-level processing on the second system data through a UMTS accelerator.

In the embodiment of the present invention, the method further includes:

and if the data to be processed is the data of the third system, demodulating and modulating the data of the third system through xDSP and ANTP.

In the embodiment of the present invention, the acquiring data to be processed includes:

judging whether the data to be processed is located in the SDM of the cluster;

if the data to be processed is located in the SDM of the cluster, accessing the SDM of the cluster to obtain the data to be processed;

and if the data to be processed is not located in the SDM of the cluster, accessing the SDM across the cluster to acquire the data to be processed.

In this embodiment of the present invention, when the first format data is first format downlink data, the performing bit-level processing on the first format data by BLA and performing symbol-level processing on the first format data by xDSP includes:

the method comprises the steps that a general direct memory access module GDMA stores data to be sent into an SDM in a cluster, wherein the cluster comprises at least one xDSP;

the BLA acquires a first control parameter, performs bit-level processing on data in the SDM according to the first control parameter, and writes the processed data back to the SDM for storage;

the xDSP performs symbol-level processing on the data in the SDM based on the acceleration processing of the FFT accelerator, and writes the processed data back to the SDM for storage;

and the ANTP acquires a second control parameter, demodulates and modulates the data in the SDM according to the second control parameter, and sends the processed data to a Radio Remote Unit (RRU) to complete antenna interface processing.

In this embodiment of the present invention, when the first standard data is first standard uplink data, the performing bit-level processing on the first standard data by BLA and performing symbol-level processing on the first standard data by xDSP includes:

the ANTP acquires a third control parameter, demodulates and modulates the received data according to the third control parameter, and writes the processed data into the SDM for storage;

the BLA acquires a fourth control parameter, performs bit-level processing on the data in the SDM according to the fourth control parameter, and writes the processed data back to the SDM for storage;

the GDMA sends data from the SDM to an external storage module for Media Access Control (MAC) level processing.

In this embodiment of the present invention, when the second-system data is second-system downlink data, the performing bit-level processing on the second-system data by using BLA and performing symbol-level processing on the second-system data by using a UMTS accelerator includes:

the GDMA stores data to be sent into an SDM in a cluster, wherein the cluster comprises at least one xDSP;

the BLA acquires a fifth control parameter, performs bit-level processing on the data in the SDM according to the fifth control parameter, and writes the processed data back to the SDM for storage;

the UMTS accelerator acquires a sixth control parameter, performs symbol-level processing on the data in the SDM according to the sixth control parameter, and writes the processed data back to the SDM for storage;

and the ANTP acquires a seventh control parameter, demodulates and modulates the data in the SDM according to the seventh control parameter, and sends the processed data to the RRU to complete antenna interface processing.

In this embodiment of the present invention, when the second system data is second system uplink data, the performing bit-level processing on the second system data by using BLA and performing symbol-level processing on the second system data by using a UMTS accelerator includes:

the ANTP acquires an eighth control parameter, demodulates and modulates the received data according to the eighth control parameter, and writes the processed data into the SDM for storage;

the UMTS accelerator acquires a ninth control parameter, performs symbol-level processing on the data in the SDM according to the ninth control parameter, and writes the processed data back to the SDM for storage;

the BLA acquires a tenth control parameter, performs bit-level processing on the data in the SDM according to the tenth control parameter, and writes the processed data back to the SDM for storage;

and the GDMA sends the data from the SDM to an external storage module for MAC-level processing.

In this embodiment of the present invention, when the third system data is third system downlink data, the performing demodulation and modulation processing on the third system data by xDSP and ANTP includes:

the xDSP acquires data from a high-speed interface, demodulates and modulates the data and stores the data into the SDM;

and the ANTP acquires an eleventh control parameter, demodulates and modulates the data in the SDM according to the eleventh control parameter, and sends the processed data to the RRU to complete antenna interface processing.

In this embodiment of the present invention, when the third system data is third system uplink data, the performing demodulation and modulation processing on the third system data by xDSP and ANTP includes:

the ANTP acquires a twelfth control parameter, demodulates and modulates the received data according to the twelfth control parameter, and writes the processed data into the SDM;

and after the data in the SDM is demodulated and modulated by the xDSP, the data is sent to the RRU through a high-speed interface to complete antenna interface processing.

The data processing device of the multi-system baseband chip provided by the embodiment of the invention comprises:

an acquisition unit for acquiring data to be processed;

the determining unit is used for determining the system type of the data to be processed;

the first processing unit is used for carrying out bit level processing on the first standard data through BLA and carrying out symbol level processing on the first standard data through xDSP if the data to be processed is the first standard data, wherein the symbol level processing process is accelerated through a Fast Fourier Transform (FFT) accelerator when the symbol level processing is carried out;

and the second processing unit is used for performing bit-level processing on the data of the second system through BLA and performing symbol-level processing on the data of the second system through a UMTS accelerator if the data to be processed is the data of the second system.

In the embodiment of the present invention, the apparatus further includes:

and the third processing unit is used for demodulating and modulating the data of the third system by xDSP and ANTP if the data to be processed is the data of the third system.

In an embodiment of the present invention, the obtaining unit is specifically configured to: judging whether the data to be processed is located in the SDM of the cluster; if the data to be processed is located in the SDM of the cluster, accessing the SDM of the cluster to obtain the data to be processed; and if the data to be processed is not located in the SDM of the cluster, accessing the SDM across the cluster to acquire the data to be processed.

In an embodiment of the present invention, the first processing unit includes:

a first downlink processing subunit, configured to store, by using the GDMA, data to be sent to an SDM in a cluster, where the cluster includes at least one xDSP; the BLA acquires a first control parameter, performs bit-level processing on data in the SDM according to the first control parameter, and writes the processed data back to the SDM for storage; the xDSP performs symbol-level processing on the data in the SDM based on the acceleration processing of the FFT accelerator, and writes the processed data back to the SDM for storage; and the ANTP acquires a second control parameter, demodulates and modulates the data in the SDM according to the second control parameter, and sends the processed data to the RRU to complete antenna interface processing.

In an embodiment of the present invention, the first processing unit includes:

the first uplink processing subunit is configured to acquire a third control parameter through the ANTP, perform demodulation and modulation processing on the received data according to the third control parameter, and write the processed data into the SDM for storage; the xDSP performs symbol-level processing on the data in the SDM based on the acceleration processing of the FFT accelerator, and writes the processed data back to the SDM for storage; the BLA acquires a fourth control parameter, performs bit-level processing on the data in the SDM according to the fourth control parameter, and writes the processed data back to the SDM for storage; and the general GDMA sends data from the SDM to an external storage module for MAC-level processing.

In an embodiment of the present invention, the second processing unit includes:

a second downlink processing subunit, configured to store, by using the GDMA, data to be sent to an SDM in a cluster, where the cluster includes at least one xDSP; the BLA acquires a fifth control parameter, performs bit-level processing on the data in the SDM according to the fifth control parameter, and writes the processed data back to the SDM for storage; the UMTS accelerator acquires a sixth control parameter, performs symbol-level processing on the data in the SDM according to the sixth control parameter, and writes the processed data back to the SDM for storage; and the ANTP acquires a seventh control parameter, demodulates and modulates the data in the SDM according to the seventh control parameter, and sends the processed data to the RRU to complete antenna interface processing.

In an embodiment of the present invention, the second processing unit includes:

the second uplink processing subunit is configured to acquire an eighth control parameter through the ANTP, perform demodulation and modulation processing on the received data according to the eighth control parameter, and write the processed data into the SDM for storage; the UMTS accelerator acquires a ninth control parameter, performs symbol-level processing on the data in the SDM according to the ninth control parameter, and writes the processed data back to the SDM for storage; the BLA acquires a tenth control parameter, performs bit-level processing on the data in the SDM according to the tenth control parameter, and writes the processed data back to the SDM for storage; and the GDMA sends the data from the SDM to an external storage module for MAC-level processing.

In an embodiment of the present invention, the third processing unit includes:

the third downlink processing subunit is used for acquiring data from the high-speed interface through the xDSP, demodulating and modulating the data and storing the data into the SDM; and the ANTP acquires an eleventh control parameter, demodulates and modulates the data in the SDM according to the eleventh control parameter, and sends the processed data to the RRU to complete antenna interface processing.

In an embodiment of the present invention, the third processing unit includes:

a third uplink processing subunit, configured to obtain a twelfth control parameter through the ANTP, perform demodulation and modulation processing on the received data according to the twelfth control parameter, and write the processed data into the SDM; and after the data in the SDM is demodulated and modulated by the xDSP, the data is sent to the RRU through a high-speed interface to complete antenna interface processing.

The processing equipment provided by the embodiment of the invention comprises: BLA, at least one cluster, UMTS accelerator, system bus; wherein the BLA, the at least one cluster, and the UMTS accelerator are all connected to the system bus;

the BLA is used for acquiring data to be processed from the cluster group and carrying out bit level processing on the data of a first standard or carrying out bit level processing on the data of a second standard;

the cluster group includes: xDSP, FFT accelerator; the xDSP is used for performing symbol-level processing on the first-standard data, wherein the symbol-level processing process is accelerated by the FFT accelerator when the symbol-level processing is performed;

and the UMTS accelerator is used for carrying out symbol-level processing on the data of the second system.

In the embodiment of the invention, the cluster group further comprises an SDM;

and if the data to be processed is not positioned in the SDM of the cluster, accessing the SDM crossing the cluster to acquire the data to be processed.

In this embodiment of the present invention, the processing device further includes a GDMA and an ANTP, and the cluster further includes an SDM; the GDMA and the ANTP are connected with the system bus, and the SDM is respectively connected with the xDSP and the FFT accelerator;

the GDMA is used for storing data to be sent to the SDM in the cluster;

the BLA is used for acquiring a first control parameter, performing bit-level processing on data in the SDM according to the first control parameter, and writing the processed data back to the SDM for storage;

the xDSP is used for performing symbol-level processing on the data in the SDM based on the acceleration processing of the FFT accelerator, and writing the processed data back to the SDM for storage;

and the ANTP is used for acquiring a second control parameter, demodulating and modulating the data in the SDM according to the second control parameter, and sending the processed data to the RRU to complete antenna interface processing.

the ANTP is used for acquiring a third control parameter, demodulating and modulating the received data according to the third control parameter, and writing the processed data into the SDM for storage;

the BLA is used for acquiring a fourth control parameter, performing bit-level processing on the data in the SDM according to the fourth control parameter, and writing the processed data back to the SDM for storage;

and the GDMA is used for sending data from the SDM to an external storage module for MAC-level processing.

In this embodiment of the present invention, the processing device further includes a GDMA and an ANTP, and the cluster further includes an SDM; wherein the GDMA and the ANTP are connected with the system bus;

the GDMA is configured to store data to be sent to an SDM in a cluster, where the cluster includes at least one xDSP;

the BLA is used for taking a fifth control parameter, performing bit-level processing on the data in the SDM according to the fifth control parameter, and writing the processed data back to the SDM for storage;

the UMTS accelerator is used for acquiring a sixth control parameter, performing symbol-level processing on the data in the SDM according to the sixth control parameter, and writing the processed data back to the SDM for storage;

and the ANTP is used for acquiring a seventh control parameter, demodulating and modulating the data in the SDM according to the seventh control parameter, and sending the processed data to the RRU to complete antenna interface processing.

the ANTP is used for acquiring an eighth control parameter, demodulating and modulating the received data according to the eighth control parameter, and writing the processed data into the SDM for storage;

the UMTS accelerator is used for acquiring a ninth control parameter, performing symbol-level processing on the data in the SDM according to the ninth control parameter, and writing the processed data back to the SDM for storage;

the BLA is used for acquiring a tenth control parameter, performing bit-level processing on the data in the SDM according to the tenth control parameter, and writing the processed data back to the SDM for storage;

In this embodiment of the present invention, the processing device further includes an ANTP, where the ANTP is connected to the system bus; the cluster further comprises an SDM;

the xDSP is also used for acquiring data from a high-speed interface, demodulating and modulating the data and storing the data into the SDM;

the ANTP is further configured to obtain an eleventh control parameter, perform demodulation and modulation processing on the data in the SDM according to the eleventh control parameter, and send the processed data to the RRU to complete antenna interface processing.

the ANTP is further configured to obtain a twelfth control parameter, perform demodulation and modulation processing on the received data according to the twelfth control parameter, and write the processed data into the SDM;

and the xDSP is also used for demodulating and modulating the data in the SDM and then sending the data to the RRU through a high-speed interface to complete antenna interface processing.

According to the technical scheme of the embodiment of the invention, data to be processed is obtained, and the system type of the data to be processed is determined; if the data to be processed is first standard data, performing bit-level processing on the first standard data through a bit-level processing acceleration module BLA, and performing symbol-level processing on the first standard data through an enhanced digital processor xDSP, wherein when the symbol-level processing is performed, the process of the symbol-level processing is accelerated through a Fast Fourier Transform (FFT) accelerator; and if the data to be processed is second system data, performing bit-level processing on the second system data through BLA, and performing symbol-level processing on the second system data through a UMTS accelerator. The xDSP multi-core cluster structure adopted by the embodiment of the invention is a high-integration and high-flexibility multi-mode ASIC embedded high-performance xDSP scheme, supports 5 multi-System coexisting single-chip soft baseband processing chips such as frequency Division duplex LTE (FDD-LTE), Time Division duplex LTE (TDD-LTE), Universal Mobile Telecommunications System (UMTS), Time Division Synchronous Code Division Multiple Access (TD-SCDMA), Global System for Mobile Communications (GSM), advanced enhanced Digital Signal processor (xDSP, X Digital Signal cluster) structure with acceleration function and core data storage function, and features of a multi-core baseband processing layer and integrated multi-core baseband processing unit, and is matched with a multi-core physical processing unit, the performance and the function of the product are greatly improved, and the product is used as a key supporting product of a wireless baseband product, has the characteristics of high performance and low time delay compared with the prior art, can reduce the cost, improve the system capacity, reduce the processing time delay of a base station, and better meet the requirement of matching high-end operators on the future technical evolution and upgrade.

Drawings

The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed herein.

Fig. 1 is a general structural diagram of a multi-system baseband chip according to an embodiment of the present invention;

FIG. 2 is a diagram of a multi-core cluster architecture according to an embodiment of the present invention;

fig. 3 is a flowchart of a data processing method of a multi-standard baseband chip according to an embodiment of the present invention;

fig. 4 is a flow chart of LTE downlink data processing according to an embodiment of the present invention;

fig. 5 is a flow chart of LTE uplink data processing according to an embodiment of the present invention;

FIG. 6 is a flow chart of a UMTS-WCDMA/TD-SCDMA downlink data processing method according to an embodiment of the present invention;

FIG. 7 is a flow chart of the UMTS-WCDMA/TD-SCDMA uplink data processing according to the embodiment of the present invention;

fig. 8 is a flow chart of GSM downlink data processing according to an embodiment of the present invention;

fig. 9 is a flow chart of GSM uplink data processing according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram of a data processing apparatus of a multi-standard baseband chip according to an embodiment of the present invention;

fig. 11 is a schematic structural diagram of a processing apparatus according to an embodiment of the present invention.

Detailed Description

So that the manner in which the features and aspects of the embodiments of the present invention can be understood in detail, a more particular description of the embodiments of the invention, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings.

To facilitate understanding of the technical solutions of the embodiments of the present invention, the terms or abbreviations related to the embodiments of the present invention are explained as follows:

GSM, Global System for Mobile Communications;

UMTS, Universal Mobile telecommunications System;

LTE, Long Term Evolution of wireless communication protocols;

TDD-LTE, Time Division duplex-LTE;

FDD-LTE, Frequency Division Duplexing-LTE;

TD-SCDMA, Time Division-synchronization Code Division Multiple Access;

OFDM, Orthogonal Frequency Division Multiplexing;

PRACH, Physical Random Access Channel;

RRU, Radio Remote Unit, Radio Remote Unit;

SOC, system-on-a-Chip;

AMBA, Advanced Microcontroller Bus Architecture, Advanced Bus Architecture;

xDSP, X Digital Signal Process, advanced enhanced Digital Signal processor;

COD, Cluster of DSPs, xDSP Cluster;

crossbar, interconnecting bus matrix;

CRM, Clock and Reset Module, Clock Reset Module;

GDMA, General direct memory access, General purpose direct memory access module;

PDMA, Program direct memory access module;

DDMA, Data direct memory access module;

SVS, static voltage super, static voltage adjustment management module;

SPM, Share Program Memory, shared Program Memory unit;

SDM, Share Data Memory, sharing Data Memory unit;

GDP, General Data Port, Universal Data Port;

GPP, General Program Port;

FEP, Fast Exclusive Port, Fast private data Port;

IDM, Internal Data Memory unit;

IPM, Internal Program Memory, Internal Program storage unit;

ANTP, Antenna Process, Antenna processing module;

BLA, Bit Level Accelerator, Bit Level processing Accelerator;

FFT, Fast Fourier Transform, FFT accelerator processing unit;

UMTS-DLC, UMTS-Down Link Chip, the downstream Chip level processing module of the UMTS accelerator;

UMTS-IC, UMTS-Interference Cancel, UMTS accelerator Interference offset processing module;

UMTS DD, UMTS-Data demodulation, UMTS accelerator Data demodulation unit;

UMTS-CD, UMTS-Control demodulation, UMTS accelerator up Control channel chip level processing unit;

UMTS-PD, UMTS-Preamble Detector, UMTS accelerator lead detection processing unit;

UMTS-PM, UMTS-Path Monitor, UMTS accelerator multipath search processing unit;

ICU, Interrupt Control Unit and Interrupt Control Unit.

For higher requirements of high performance and low delay of a multi-system baseband chip, the embodiment of the invention provides a data processing method and a data processing device of the multi-system baseband chip based on a multi-core cluster structure.

Fig. 1 is a general structure diagram of a multi-system baseband chip according to an embodiment of the present invention, where the multi-system baseband chip with a multi-core cluster structure according to the embodiment of the present invention is based on a system on chip SOC design technology, as shown in fig. 1, the multi-system baseband chip includes: the Crossbar is connected with the CRM, at least one COD, the baseband physical layer accelerator and each peripheral module and provides a concurrent full-interconnection data and control interaction path of a program loading path, a data access path and a configuration path. The functional modules in the chip are connected together through Crossbar, and various processing functions of the baseband physical layer are completed under the cooperation of a GDMA controller, an ICU, a general timer and the like. Each module in the multi-system baseband chip is described below:

1) the Crossbar is based on an AMBA bus protocol architecture and comprises a plurality of m multiplied by n dimensional matrix array Crossbar and different types of bus conversion bridges to realize interconnection of all interconnection equipment.

2) The CRM is responsible for managing clocks and resets required by all functions and further comprises a temperature monitoring module, an SVS management module, a bus monitoring module, a BOOT management module and the like. The system is independent from the whole chip large system and interacts with the SOC large system through a simple and reliable access interface.

The SVS management as described above refers to a static voltage adjustment means for reducing the overall power consumption of the chip. On the premise of meeting the performance, different voltages are applied to chips (fast chips, slow chips and the like) with different process distributions.

The bus monitoring is a debugging means, and captures bus information such as handshaking conditions and bandwidth statistics of an AXI bus of an endpoint or an important node of an internal AXI bus of a chip meeting a trigger condition.

The BOOT management refers to a process of configuring a processor to execute an initialization program from a position designated by a chip after a chip is powered on and reset, a clock is reset normally, and a processor is reset and released.

3) COD refers to a processor cluster system including xDSP, SPM, SDM, PDMA, DDMA, FFT accelerator, bus matrix, and AXI2AXI/AXI2APB configuration bridge.

xDSP, as mentioned above, refers to advanced and enhanced DSP core in a processor cluster, providing a generic data access interface GDP, which can access the full chip address space. A fast dedicated data access interface FEP is provided to access the shared data storage space of the SDM. A generic program access interface GPP is provided which can access the full chip address space.

The SPM as described above refers to the shared program storage module of the current processor cluster for storing xDSP core program instructions, and the SDM refers to the shared data storage module of the current processor cluster for storing xDSP core program data and core baseband data.

The PDMA as described above mainly assists the xDSP core to complete data transfer between the IPM in the internal program space of the xDSP core and the storage space of the external shared program. The DDMA is mainly used for assisting the xDSL core to complete the data transfer between the internal program space IDM of the xDSL core and the external shared program storage space.

4) The baseband physical layer accelerator is a high-performance unit supporting multi-user data service parallel processing, can be expanded in scale, and meets the requirement of higher performance, and comprises the following modules:

ANTP: the antenna interface subsystem mainly provides a data interaction function between the optical port and the internal xDSP core and between the optical port and the hardware accelerator, and receives data configuration information of an external CPU and reports the data configuration information to the CPU.

BLA: and finishing the processing function of uplink and downlink bit levels of service channels of 3 systems such as LTE/UMTS/TD-SCDMA and the like.

FFT accelerator: the FFT accelerator mainly assists the xDSP core to realize the OFDM symbol demodulation modulation processing function and the PRACH related processing function of LTE antenna data, and also supports the general FFT/IFFT conversion function.

UMTS accelerator: the system comprises UMTS-DLC submodules: the UMTS downlink chip level processing is completed. The system comprises a UMTS-IC sub-module: the interference cancellation process of UMTS is completed. The system comprises a UMTS-DD submodule: the traffic channel demodulation process of UMTS is completed. The system comprises a UMTS-CD sub-module: and finishing the chip-level demodulation processing of the UMTS uplink control channel. The system comprises UMTS-PD sub-modules: and finishing the detection processing of the UMTS uplink preamble. The system comprises a UMTS-PM submodule: and finishing the UMTS uplink multipath searching processing.

5) The chip external interface, including the DDR interface, is used by both the dedicated accelerator and the xDSP. The antenna data stream including the baseband processing is transmitted and received by an antenna interface subsystem (ANTP), and is connected to the outside through a high-speed Serdes. The SRIO/PCIe interface is mainly used for chip cascade connection and enhancing the processing capacity of the chip. The Extern CPU interface is mainly used for system configuration, and the flexibility of the chip is enhanced.

6) The GDMA replaces a processor to carry out high-speed data transmission between peripheral equipment and a memory in the whole chip system, reduces the burden of the processor, and the controller is connected to an AMBA system bus and is responsible for SOC system data handling of the AMBA framework, and is characterized in that: the method carries n independent DMA channels, supports chain transmission, supports multidimensional transmission and supports efficient read-write parallel transmission.

7) And the ICU is used for providing inter-core communication processing units among the xDSPs and between the xDSPs and an external CPU, providing 1 outbox with the depth of d1 for each xDSP core, providing a shared INBOX with the depth of d2 for each cluster, and providing 1 INBOX with the depth of d3 and 1 message incoming interrupt and 1 overflow error interrupt for the external CPU.

The embodiment of the invention provides a set of clock resetting and boot processes: the chip external input main clock comprises a differential clock and a frequency-variable single-ended clock, except a clock used for the CRM module, an input clock of the PLL and reference clocks of all serdes parts; other internal clocks are configurable to be off. The chip internally uses a plurality of PLL IPs for generating an internal high frequency clock from a reference clock.

The reset of the CRM module is controlled by a chip external reset _ n signal, and the reset of other accelerators, IP/PLL/xDSP cores and the like is controlled by a register which is configurable inside the CRM. By default, accelerators other than CRM, IP/PLL/xDSP cores, etc. are in a reset state. After the CRM is reset, software inside the CRM releases other accelerators, IP/PLL/xDSP cores and the like step by step.

After the chip is reset, the BOOT of the xDSP is carried out by CRM software, and the specific flow is as follows:

1. load xDSP program instructions into instruction space (including IDM, SDM, DDR);

2. loading xDSP program data into a data space (including IDM, SDM, DDR);

3. configuring a BOOT _ VECTOR register in a system controller corresponding to the xDSP as a program starting address expected by a user;

4. and configuring a corresponding xDSP reset register in the clock reset module, and releasing all soft resets of the xDSP at the same time.

5. And configuring a BOOT control register corresponding to the xDSP to control a BOOT signal required by starting the corresponding xDSP, and carrying out BOOT on the xDSP from a starting address expected by a user.

The processing system of the multi-core cluster structure in the embodiment of the invention is a heterogeneous cluster chain structure based on a System On Chip (SOC) design technology, and is different from the prior art in that the embodiment of the invention not only comprises a plurality of xDSPs (x digital processors) for cooperatively processing cluster data, but also comprises an FFT (fast Fourier transform) accelerator for performing a data acceleration function in cooperation with the xDSPs, and also comprises a core data sharing storage unit (SDM). Theoretically, the dimension of the matrix array can be infinitely increased, but actually, when the dimension of the matrix array is continuously increased, the efficiency of equipment in interconnection and intercommunication through the matrix is reduced, the delay of a bus path is prolonged, and the problems of bus deadlock and the like are easily caused. Generally, the dimension of each matrix array is less than or equal to e, so that the above problems can be effectively avoided. The multiple xDSPs in the multi-core cluster can process multi-cell data of the same cluster in parallel, the number y of the multi-core cluster is influenced by the usable dimensionality of the bus matrix array, and when the xDSPs need to process more cell data outside the cluster, SDM spaces of other clusters can be accessed through GDP interfaces to process cell switching, multi-antenna combination and other baseband services. The FFT accelerator mainly assists the xDSP to realize the OFDM symbol demodulation modulation processing function and the PRACH related processing function of LTE antenna data, supports the functions of general FFT and IFFT transformation, and plays an important acceleration role in the data demodulation processing of the xDSP. The SDM is used for storing core data needing low-delay processing, and xDSP can process the core data with the shortest access path and delay without passing through a bus Crossbar, so that the data transmission delay caused by passing through a bus matrix is reduced.

Fig. 2 is a diagram of a multi-core cluster structure according to an embodiment of the present invention, and as shown in fig. 2, the present invention provides a COD including xDSP, SPM, SDM, PDMA, DDMA, bus matrix and AXI2AXI/AXI2APB configuration bridge, and an FFT accelerator.

The xDSP provided by the present invention supports the following main interfaces and functions:

1. and a general data access interface GDP is provided for accessing data, and instruction data can be configured in the SDM of the cluster, or in other SDMs or DDR, so that the utilization rate of the xDSL resources in demodulating different data can be improved to the maximum extent under flexible configuration and scheduling.

2. A general program access interface GPP is provided for accessing instructions, and instruction data can be configured in the cluster SPM, or in other cluster SPMs or DDR.

3. A fast dedicated data access interface FEP is provided, which only has access to the SDM space of the cluster, for fast processing of SDM stored data, especially antenna data of the same cell, with minimum delay.

4. A PDMA is provided, which can transfer data between IPM and SPM/DDR by command through GPP interface.

5. A DDMA is provided, which can carry data in IDM and SDM/DDR through GDP/FEP interface.

6. The integrated self-developed FFT accelerator can play an important acceleration role in data demodulation processing of xDSP, particularly assist the xDSP to realize OFDM symbol demodulation modulation processing function and PRACH related processing function of LTE antenna data, support general FFT and IFFT conversion functions, and can meet the optimal delay performance of LTE data.

7. The integrated core data storage unit SDM can provide shortest path loss and time delay requirements for the demodulation processing core baseband data of the xDSP. The non-core data is stored in the external DDR, does not occupy resources in the xDSP cluster, and can tolerate certain time delay.

8. As shown in fig. 2, the third step represents the parameter configuration interfaces of the ICU, SDM, PDM, and FFT accelerator, respectively.

Fig. 3 is a flowchart of a data processing method of a multi-standard baseband chip according to an embodiment of the present invention, and as shown in fig. 3, the method includes:

step 301: acquiring data to be processed, and determining the system type of the data to be processed.

The acquiring the data to be processed comprises the following steps:

judging whether the data to be processed is located in the SDM of the cluster;

Step 302: if the data to be processed is first standard data, performing bit level processing on the first standard data through BLA, and performing symbol level processing on the first standard data through xDSP, wherein when the symbol level processing is performed, the process of the symbol level processing is accelerated through an FFT accelerator.

The first system data is: and (3) LTE standard data.

When the first system data is first system downlink data, the performing bit-level processing on the first system data by BLA and performing symbol-level processing on the first system data by xDSP includes:

and the ANTP acquires a second control parameter, demodulates and modulates the data in the SDM according to the second control parameter, and sends the processed data to the RRU to complete antenna interface processing.

When the first system data is first system uplink data, the performing bit-level processing on the first system data by BLA and performing symbol-level processing on the first system data by xDSP includes:

Step 303: and if the data to be processed is second system data, performing bit-level processing on the second system data through BLA, and performing symbol-level processing on the second system data through a UMTS accelerator.

The second system data is: UMTS-WCDMA/TD-SCDMA system data.

When the second-system data is second-system downlink data, the performing bit-level processing on the second-system data through BLA and performing symbol-level processing on the second-system data through a UMTS accelerator includes:

When the second system data is second system uplink data, the performing bit-level processing on the second system data by BLA and performing symbol-level processing on the second system data by UMTS accelerator includes:

In addition, the method of the embodiment of the invention further comprises the following steps: and if the data to be processed is the data of the third system, demodulating and modulating the data of the third system through the xDSP and an antenna processing module ANTP.

The third system data is: and GSM standard data.

When the third system data is third system downlink data, the performing demodulation and modulation processing on the third system data through xDSP and ANTP includes:

When the third system data is third system uplink data, the performing demodulation and modulation processing on the third system data through xDSP and ANTP includes:

The technical solution of the embodiments of the present invention is further described in detail below with reference to specific application scenarios.

Example one

Fig. 4 is a flow chart of LTE downlink data processing according to an embodiment of the present invention, including a processing procedure of baseband original antenna data, symbol data, and bit data on a chip. As shown in fig. 4, the method comprises the following steps:

step 401: the GDMA transfers the MAC layer processing result needing downlink transmission to the SDM from the external DDR;

step 402: the BLA acquires control parameters from the SDM or the IDM under the coordination of the xDSP, or receives the configuration of the xDSP to complete bit level downlink processing of the data, and writes the data back to the SDM for storage after the processing is finished;

step 403: the xDSP completes the symbol level downlink processing of the downlink data with the assistance of the FFT accelerator in the cluster, and writes back the processed data to the SDM for storage;

step 404: the ANTP obtains control parameters from the SDM or the IDM or receives the configuration of the xDSP under the coordination of the xDSP, takes out data from the SDM storage, and sends the data to the RRU through a CPRI interface in the ANTP after the processing is finished so as to finish the antenna interface processing.

Fig. 5 is a flow chart of LTE uplink data processing according to an embodiment of the present invention, including a processing procedure of baseband original antenna data, symbol data, and bit data on a chip. As shown in fig. 5, the method comprises the following steps:

step 501: the ANTP obtains control parameters from the SDM or the IDM under the coordination of the xDSP, or receives the configuration of the xDSP, and writes data received from a CPRI interface in the ANTP into an SDM storage after the data is processed to complete the antenna interface processing;

step 502: the xDSP completes the systematic level uplink processing of the uplink data with the aid of an FFT accelerator in the cluster, and writes back the processed data to the SDM for storage;

step 503: the BLA acquires control parameters from the SDM or the IDM under the coordination of the xDSP, or receives the configuration of the xDSP to complete bit level uplink processing of the data;

step 504: and the GDMA transfers the data which needs to be received in the uplink from the SDM to an external DDR to carry out the processing of MAC and above level.

Example two

Fig. 6 is a flowchart of processing UMTS-WCDMA/TD-SCDMA downlink data according to an embodiment of the present invention, including a processing procedure of baseband original antenna data, symbol data, and bit data in a chip. As shown in fig. 6, the method comprises the following steps:

step 601: the GDMA transfers the MAC layer processing result needing downlink transmission to the SDM from the external DDR;

step 602: the BLA acquires control parameters from the SDM or the IDM under the coordination of the xDSP, or receives the configuration of the xDSP to complete bit level downlink processing of the data, and writes the data back to the SDM for storage after the processing is finished;

step 603: the UMTS accelerator acquires control parameters from the SDM or the IDM under the coordination of the xDSP, or receives the configuration of the xDSP to complete symbol level downlink processing of the data, and writes the processed data back to the SDM for storage;

step 604: the ANTP obtains control parameters from the SDM or the IDM or receives the configuration of the xDSP under the coordination of the xDSP, takes out data from the SDM storage, and sends the data to the RRU through a CPRI interface in the ANTP after the processing is finished so as to finish the antenna interface processing.

Fig. 7 is a flowchart of processing UMTS-WCDMA/TD-SCDMA uplink data according to an embodiment of the present invention, including a processing procedure of baseband original antenna data, symbol data, and bit data in a chip. As shown in fig. 7, the method comprises the following steps:

step 701: the ANTP obtains control parameters from the SDM or the IDM under the coordination of the xDSP, or receives the configuration of the xDSP, and writes data received from a CPRI interface in the ANTP into an SDM storage after the data is processed to complete the antenna interface processing;

step 702: the UMTS accelerator acquires control parameters from the SDM or the IDM under the coordination of the xDSP, or receives the configuration of the xDSP to complete chip level and symbol level uplink processing of the data, and writes the processed data back to the SDM for storage;

step 703: the BLA acquires control parameters from the SDM or the IDM under the coordination of the xDSP, or receives the configuration of the xDSP to complete bit level uplink processing of the data;

step 704: and the GDMA transfers the data which needs to be received in the uplink from the SDM to an external DDR to carry out the processing of MAC and above level.

EXAMPLE III

Fig. 8 is a flow chart of GSM downlink data processing according to an embodiment of the present invention, including a processing procedure of baseband original antenna data, symbol data, and bit data on a chip. As shown in fig. 8, the method comprises the following steps:

step 801: the xDSP acquires data to be processed from a high-speed Serdes interface, processes the data and stores the data in the SDM;

step 802: the ANTP obtains control parameters from the SDM or the IDM or receives the configuration of the xDSP under the coordination of the xDSP, takes out data from the SDM storage, and sends the data to the RRU through a CPRI interface in the ANTP after the processing is finished so as to finish the antenna interface processing.

Fig. 9 is a flow chart of GSM uplink data processing according to an embodiment of the present invention, including a processing procedure of baseband original antenna data, symbol data, and bit data on a chip. As shown in fig. 9, the method comprises the following steps:

step 901: the ANTP obtains control parameters from the SDM or the IDM under the coordination of the xDSP, or receives the configuration of the xDSP, and writes data received from a CPRI interface in the ANTP into an SDM storage after the data is processed to complete the antenna interface processing;

step 902: the xDSP completes the processing of the data and sends the data to the RRU through a high-speed Serdes interface to complete the antenna interface processing.

In a specific application scenario, it is assumed that a baseband service scenario needs to support 8 cells, each cell supports 2 antennas, a chip system can be built and includes 4 multi-core clusters, each cluster is loaded with 2 xDSP cores, in general, 2 xdsps of a certain cluster s cooperatively process baseband data of 4 antennas of 2 cells allocated in parallel, and a loaded FFT accelerator unit provides an acceleration processing function of LTE standard data. When other antenna data of other cells need to be processed, the xDSP or DDMA accesses the cell antenna data or symbol data stored by the SDM of other clusters through the GDP data interface for processing.

The technical implementation of the present invention, including but not limited to the above summary and implementation, especially, the above implementation example is only a specific example, and the number of cells and the number of antennas supported by the multi-core cluster structure of the baseband processing chip, the number of xdsps and the heterogeneous structure formed by the FFT accelerating unit, and the system capacity of the baseband physical processing unit may vary according to different requirements. The multi-core heterogeneous cluster structure provided by the invention is an xDSP cluster structure with an acceleration function and aiming at baseband data service processing, and is not limited to the specific number of xDSPs and the number of accelerators of a cluster.

Fig. 10 is a schematic structural composition diagram of a data processing apparatus of a multi-standard baseband chip according to an embodiment of the present invention, and as shown in fig. 10, the apparatus includes:

an acquisition unit 1001 configured to acquire data to be processed;

a determining unit 1002, configured to determine a format type of the data to be processed;

a first processing unit 1003, configured to, if the data to be processed is data of a first standard, perform bit-level processing on the data of the first standard through BLA, and perform symbol-level processing on the data of the first standard through xDSP, where a process of the symbol-level processing is accelerated through a fast fourier transform FFT accelerator when performing the symbol-level processing.

The device further comprises:

a second processing unit 1004, configured to perform bit-level processing on the data of the second system by using BLA and perform symbol-level processing on the data of the second system by using a UMTS accelerator if the data to be processed is data of the second system;

a third processing unit 1005, configured to, if the data to be processed is data of a third standard, perform demodulation and modulation processing on the data of the third standard through xDSP and ANTP.

In this embodiment of the present invention, the obtaining unit 1001 is specifically configured to: judging whether the data to be processed is located in the SDM of the cluster; if the data to be processed is located in the SDM of the cluster, accessing the SDM of the cluster to obtain the data to be processed; and if the data to be processed is not located in the SDM of the cluster, accessing the SDM across the cluster to acquire the data to be processed.

In this embodiment of the present invention, the first processing unit 1003 includes:

a first downlink processing subunit 10031, configured to store, by the GDMA, data to be sent to an SDM in a cluster, where the cluster includes at least one xDSP; the BLA acquires a first control parameter, performs bit-level processing on data in the SDM according to the first control parameter, and writes the processed data back to the SDM for storage; the xDSP performs symbol-level processing on the data in the SDM based on the acceleration processing of the FFT accelerator, and writes the processed data back to the SDM for storage; and the ANTP acquires a second control parameter, demodulates and modulates the data in the SDM according to the second control parameter, and sends the processed data to the RRU to complete antenna interface processing.

a first uplink processing subunit 10032, configured to obtain a third control parameter through ANTP, perform demodulation and modulation processing on the received data according to the third control parameter, and write the processed data into the SDM for storage; the xDSP performs symbol-level processing on the data in the SDM based on the acceleration processing of the FFT accelerator, and writes the processed data back to the SDM for storage; the BLA acquires a fourth control parameter, performs bit-level processing on the data in the SDM according to the fourth control parameter, and writes the processed data back to the SDM for storage; and the general GDMA sends data from the SDM to an external storage module for MAC-level processing.

In this embodiment of the present invention, the second processing unit 1004 includes:

a second downlink processing subunit 10041, configured to store, by the GDMA, data to be sent to an SDM in a cluster, where the cluster includes at least one xDSP; the BLA acquires a fifth control parameter, performs bit-level processing on the data in the SDM according to the fifth control parameter, and writes the processed data back to the SDM for storage; the UMTS accelerator acquires a sixth control parameter, performs symbol-level processing on the data in the SDM according to the sixth control parameter, and writes the processed data back to the SDM for storage; and the ANTP acquires a seventh control parameter, demodulates and modulates the data in the SDM according to the seventh control parameter, and sends the processed data to the RRU to complete antenna interface processing.

a second uplink processing subunit 10042, configured to obtain an eighth control parameter through the ANTP, perform demodulation and modulation processing on the received data according to the eighth control parameter, and write the processed data into the SDM for storage; the UMTS accelerator acquires a ninth control parameter, performs symbol-level processing on the data in the SDM according to the ninth control parameter, and writes the processed data back to the SDM for storage; the BLA acquires a tenth control parameter, performs bit-level processing on the data in the SDM according to the tenth control parameter, and writes the processed data back to the SDM for storage; and the GDMA sends the data from the SDM to an external storage module for MAC-level processing.

In this embodiment of the present invention, the third processing unit 1005 includes:

a third downlink processing subunit 10051, configured to obtain data from the high-speed interface through xDSP, demodulate and modulate the data, and store the demodulated data in the SDM; and the ANTP acquires an eleventh control parameter, demodulates and modulates the data in the SDM according to the eleventh control parameter, and sends the processed data to the RRU to complete antenna interface processing.

a third uplink processing subunit 10052, configured to obtain a twelfth control parameter through the ANTP, perform demodulation and modulation processing on the received data according to the twelfth control parameter, and write the processed data into the SDM; and after the data in the SDM is demodulated and modulated by the xDSP, the data is sent to the RRU through a high-speed interface to complete antenna interface processing.

Those skilled in the art will appreciate that the functions performed by the various elements of the apparatus shown in fig. 10 may be understood by reference to the associated description of the method described above. The functions of the units in the apparatus shown in fig. 10 may be implemented by a program running on a processor, or may be implemented by specific logic circuits.

Fig. 11 is a schematic structural composition diagram of a processing apparatus according to an embodiment of the present invention, and as shown in fig. 11, the processing apparatus includes: a BLA 1101, at least one cluster 1102, a UMTS accelerator 1103, a system bus 1106; wherein the BLA 1101, the at least one cluster 1102, and the UMTS accelerator 1103 are all connected to the system bus 1106;

the BLA 1101 is configured to acquire data to be processed from the cluster group 1102, and perform bit-level processing on data of a first system, or perform bit-level processing on data of a second system;

the cluster group 1102 includes: xDSP11021, FFT accelerator 11022; the xDSP11021 is configured to perform symbol level processing on the data of the first standard, where, during the symbol level processing, the FFT accelerator 11022 is used to accelerate the process of the symbol level processing; the xDSP11021 is also used for demodulating and modulating the data of a third standard;

the UMTS accelerator 1103 is configured to perform symbol-level processing on the data of the second system.

In this embodiment of the present invention, the cluster group 1102 further includes an SDM 11023;

if the data to be processed is located in the SDM 11023 of the cluster 1102, accessing the SDM 11023 of the cluster 1102 to obtain the data to be processed;

if the data to be processed is not located in SDM 11023 of the present cluster 1102, then SDM 11023 across cluster 1102 is accessed to obtain the data to be processed.

In this embodiment of the present invention, the processing device further includes a GDMA 1105 and an ANTP 1104, and the cluster group 1102 further includes an SDM 11023; the GDMA 1105 and the ANTP 1104 are connected to the system bus 1106, and the SDM 11023 is connected to the xDSP11021 and the FFT accelerator 11022, respectively;

the GDMA 1105 is configured to store data to be sent into an SDM 11023 in a cluster group 1102;

the BLA 1101 is configured to acquire a first control parameter, perform bit-level processing on data in the SDM 11023 according to the first control parameter, and write the processed data back to the SDM 11023 for storage;

the xDSP11021 is configured to perform symbol-level processing on data in the SDM 11023 based on the acceleration processing of the FFT accelerator 11022, and write back the processed data to the SDM 11023 for storage;

the ANTP 1104 is configured to acquire a second control parameter, demodulate and modulate the data in the SDM 11023 according to the second control parameter, and send the processed data to the RRU to complete antenna interface processing.

In this embodiment of the present invention, the processing device further includes a GDMA 1105, and the cluster group 1102 further includes an SDM 11023 and an ANTP 1104; the GDMA 1105 and the ANTP 1104 are connected to the system bus 1106, and the SDM 11023 is connected to the xDSP11021 and the FFT accelerator 11022, respectively;

the ANTP 1104 is configured to acquire a third control parameter, perform demodulation and modulation processing on the received data according to the third control parameter, and write the processed data into the SDM 11023 for storage;

the BLA 1101 is configured to acquire a fourth control parameter, perform bit-level processing on data in the SDM 11023 according to the fourth control parameter, and write the processed data back to the SDM 11023 for storage;

the GDMA 1105 is used for sending data from the SDM 11023 to an external storage module for MAC level processing.

In this embodiment of the present invention, the processing device further includes a GDMA 1105 and an ANTP 1104, and the cluster group 1102 further includes an SDM 11023; the GDMA 1105 and the ANTP 1104 are connected to the system bus 1106;

the GDMA 1105 is configured to store data to be sent into an SDM 11023 in a cluster 1102, where the cluster 1102 includes at least one xDSP 11021;

the BLA 1101 is configured to obtain a fifth control parameter, perform bit-level processing on data in the SDM 11023 according to the fifth control parameter, and write the processed data back to the SDM 11023 for storage;

the UMTS accelerator 1103 is configured to obtain a sixth control parameter, perform symbol-level processing on the data in the SDM 11023 according to the sixth control parameter, and write the processed data back to the SDM 11023 for storage;

the ANTP 1104 is configured to obtain a seventh control parameter, demodulate and modulate the data in the SDM 11023 according to the seventh control parameter, and send the processed data to the RRU to complete antenna interface processing.

the ANTP 1104 is configured to acquire an eighth control parameter, perform demodulation and modulation processing on the received data according to the eighth control parameter, and write the processed data into the SDM 11023 for storage;

the UMTS accelerator 1103 is configured to obtain a ninth control parameter, perform symbol-level processing on the data in the SDM 11023 according to the ninth control parameter, and write the processed data back to the SDM 11023 for storage;

the BLA 1101 is configured to acquire a tenth control parameter, perform bit-level processing on data in the SDM 11023 according to the tenth control parameter, and write the processed data back to the SDM 11023 for storage;

In this embodiment of the present invention, the processing device further includes an ANTP 1104, where the ANTP is connected to the system bus 1106; the cluster group 1102 also includes SDM 11023;

the xDSP11021 is further configured to acquire data from a high-speed interface, demodulate and modulate the data, and store the demodulated and modulated data into the SDM 11023;

the ANTP 1104 is further configured to obtain an eleventh control parameter, perform demodulation and modulation processing on the data in the SDM 11023 according to the eleventh control parameter, and send the processed data to the RRU to complete antenna interface processing.

the ANTP 1104 is further configured to obtain a twelfth control parameter, perform demodulation and modulation processing on the received data according to the twelfth control parameter, and write the processed data into the SDM 11023;

the xDSP11021 is further configured to perform demodulation and modulation processing on the data in the SDM 11023, and send the data to the RRU through a high-speed interface to complete antenna interface processing.

The interaction between the above modules can be realized by a bus.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims

1. A data processing method of a multi-standard baseband chip is characterized in that the multi-standard baseband chip comprises a bit level processing acceleration module BLA, at least one cluster, a universal mobile telecommunications module UMTS accelerator and a system bus; wherein the BLA, the at least one cluster, and the UMTS accelerator are all connected to the system bus; the method comprises the following steps:

if the data to be processed is first standard data, performing bit-level processing on the first standard data through BLA, and performing symbol-level processing on the first standard data through an enhanced digital processor xDSP, wherein the symbol-level processing process is accelerated through a Fast Fourier Transform (FFT) accelerator when the symbol-level processing is performed;

2. The method of claim 1, further comprising:

and if the data to be processed is the data of the third system, demodulating and modulating the data of the third system through the xDSP and an antenna processing module ANTP.

3. The method of claim 1, wherein the obtaining data to be processed comprises:

judging whether the data to be processed is located in a shared data storage unit (SDM) of the cluster;

4. The method as claimed in claim 1, wherein in a case that the data of the first standard is downlink data of the first standard, the performing bit-level processing on the data of the first standard through BLA and performing symbol-level processing on the data of the first standard through xDSP includes:

5. The method according to claim 1 or 4, wherein in a case that the data of the first standard is uplink data of the first standard, the performing bit-level processing on the data of the first standard by BLA and performing symbol-level processing on the data of the first standard by xDSP includes:

6. The method as claimed in claim 1, wherein in a case that the data of the second system is downlink data of a second system, the performing bit-level processing on the data of the second system by BLA and performing symbol-level processing on the data of the second system by UMTS accelerator includes:

7. The method as claimed in claim 1 or 6, wherein in a case that the data of the second system is uplink data of a second system, the performing bit-level processing on the data of the second system by BLA and performing symbol-level processing on the data of the second system by UMTS accelerator includes:

8. The method according to claim 2, wherein in a case that the data of the third standard is downlink data of a third standard, the performing demodulation and modulation processing on the data of the third standard by xDSP and ANTP includes:

9. The method according to claim 2 or 8, wherein in a case that the data of the third standard is uplink data of a third standard, the performing demodulation and modulation processing on the data of the third standard by xDSP and ANTP includes:

10. A data processing device of a multi-system baseband chip comprises a BLA, at least one cluster, a UMTS accelerator and a system bus; wherein the BLA, the at least one cluster, and the UMTS accelerator are all connected to the system bus; characterized in that the device comprises:

an acquisition unit for acquiring data to be processed;

11. The apparatus of claim 10, further comprising:

12. The apparatus according to claim 10, wherein the obtaining unit is specifically configured to: judging whether the data to be processed is located in the SDM of the cluster; if the data to be processed is located in the SDM of the cluster, accessing the SDM of the cluster to obtain the data to be processed; and if the data to be processed is not located in the SDM of the cluster, accessing the SDM across the cluster to acquire the data to be processed.

13. The apparatus of claim 10, wherein the first processing unit comprises:

14. The apparatus according to claim 10 or 13, wherein the first processing unit comprises:

15. The apparatus of claim 10, wherein the second processing unit comprises:

16. The apparatus according to claim 10 or 15, wherein the second processing unit comprises:

17. The apparatus of claim 11, wherein the third processing unit comprises:

18. The apparatus according to claim 11 or 17, wherein the third processing unit comprises:

19. A processing device, characterized in that the processing device comprises: BLA, at least one cluster, UMTS accelerator, system bus; wherein the BLA, the at least one cluster, and the UMTS accelerator are all connected to the system bus;

20. The processing device of claim 19, wherein the cluster further comprises an SDM;

21. The processing device of claim 19, wherein the processing device further comprises a GDMA, an ANTP, wherein the cluster further comprises an SDM; the GDMA and the ANTP are connected with the system bus, and the SDM is respectively connected with the xDSP and the FFT accelerator;

the GDMA is used for storing data to be sent to the SDM in the cluster;

22. The processing device according to claim 19 or 21, wherein the processing device further comprises a GDMA, an ANTP, the cluster further comprises an SDM; the GDMA and the ANTP are connected with the system bus, and the SDM is respectively connected with the xDSP and the FFT accelerator;

23. The processing device of claim 19, wherein the processing device further comprises a GDMA, an ANTP, wherein the cluster further comprises an SDM; wherein the GDMA and the ANTP are connected with the system bus;

24. The processing device of claim 19 or 23, wherein the processing device further comprises a GDMA, an ANTP, wherein the cluster further comprises an SDM; wherein the GDMA and the ANTP are connected with the system bus;

25. The processing device of claim 19, further comprising an ANTP, the ANTP connected to the system bus; the cluster further comprises an SDM;

26. The processing device according to claim 19 or 25, further comprising an ANTP, the ANTP being connected to the system bus; the cluster further comprises an SDM;