CN108737065B - Novel equivalent circuit model of chaotic system - Google Patents
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Abstract
The invention discloses a novel analog circuit for realizing a novel chaotic system, which comprises an integrated operational amplifier U1, an integrated operational amplifier U2 and a multiplier U3, wherein corresponding operations in a chaotic system equation are realized by utilizing an integrated operational amplifier chip and an analog multiplier circuit, the integrated operational amplifier chip is mainly used for realizing inverse operation, proportional operation, summation operation and integral operation, the analog multiplier is used for realizing product operation, and the analog multiplier mainly comprisesxSum ofxA term generation circuit,yAnd-yA term generation circuit,zAnd-zA term generation circuit,wAn item generation circuit. The invention provides a novel equivalent circuit model of a four-dimensional chaotic system, which is used for simulating the dynamic characteristics of the chaotic system, and the generated sequence has larger key parameter space and higher safety when being used as a pseudo-random sequence II applied to a cryptosystem.
Description
Technical Field
The invention belongs to the technical field of circuit design, relates to an equivalent circuit model of a novel chaotic system, and particularly relates to a circuit model of a novel four-dimensional chaotic system with rich dynamic characteristics, which is used for generating a chaotic pseudo-random sequence with good performance.
Background
In 1963, the american meteorologist Lorenz (Lorenz) showed the charm of chaos to people through the "butterfly effect", and proposed the first mathematical and physical models of the chaotic system. In 1976, a famous insect population model is provided by American mathematics ecology physician plum (May R), then the dynamic characteristics of various chaotic systems are continuously and deeply analyzed, a plurality of new chaotic systems and models are provided, the development of chaos is promoted, a new entry point is provided for the research of chaos, and a stout research result is obtained. When the chaotic sequence is applied to the password, not only the complexity of the chaotic system but also the pseudo-randomness and the safety of the sequence generated by the chaotic system need to be considered. At present, the classical chaotic system has been widely researched, and can be deciphered by using methods such as phase space reconstruction and the like, and the security of the chaotic system faces challenges. Meanwhile, the continuous high-dimensional chaotic system is more complex in mathematical structure, has a larger secret key parameter space, and is applied to a cryptosystem as a pseudo-random sequence II, so that the security is higher.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a novel equivalent circuit model of a four-dimensional chaotic system, which is used for simulating the dynamic characteristics of the chaotic system.
The technical scheme adopted by the invention for solving the technical problem is as follows: comprises an x term and-x term generating circuit, a y term and-y term generating circuit, a z term and-z term generating circuit and a w term generating circuit. The x term generating circuit is constituted by the operational amplifier 4 in the integrated operational amplifier chip U1, the resistors R5, R6, and the capacitor C2, and specifically, the-y term and the-x term are added to the operational amplifier 4 in the integrated operational amplifier chip U1, and the output of x is realized by the inverted summation operation and the integration operation. The y term generating circuit is composed of an operational amplifier 4, multipliers U3, R15, R16 and R17 in an integrated operational amplifier chip U2 and a capacitor C4, specifically, the multiplier U3 outputs an xy term, the xy term is added to an operational amplifier 1 in the integrated operational amplifier chip U2, an output-xy term, -x term, -y term and-xy term are added to the operational amplifier 4 in the integrated operational amplifier chip U2 through an inverted summation operation, and the output of y is realized through the inverted summation operation and an integral operation. The z term generating circuit is composed of an operational amplifier 2 in an integrated operational amplifier chip U2, a multiplier U3, resistors R11, R12, R13 and R14 and a capacitor C3, wherein the multiplier U3 outputs an xy term which is added to an operational amplifier 1 in the integrated operational amplifier chip U2, an output-xy term is obtained through an inverted summation operation, the x term, -z term, w term and-xy term are added to the operational amplifier 2 in the integrated operational amplifier chip U2, and the output of z is realized through the inverted summation operation and an integration operation. The w term generating circuit is composed of the operational amplifier 3 in the integrated operational amplifier chip U2, resistors R18, R19 and a capacitor C1, and the-z term and the w term are added to the operational amplifier 3 in the integrated operational amplifier chip U2, and the output of w is realized through an inverting summation integration operation. The x term generation circuit is realized by an inverting proportional amplifier composed of the operational amplifier 3 and resistors R7 and R8 in the integrated operational amplifier chip U1. The y term generating circuit is realized by an operational amplifier 2 in an integrated operational amplifier chip U1 and an inverting proportional amplifier formed by resistors R3 and R4. The z term generating circuit is realized by an operational amplifier 1 in an integrated operational amplifier chip U1 and an inverting proportional amplifier composed of resistors R1 and R2. The xy term generating circuit is composed of an operational amplifier 1 in an integrated operational amplifier chip U2, a multiplier U3, resistors R9 and R10, and the xy term output by the multiplier U3 is output by an inverting proportional amplifier.
The integrated operational amplifier chip U1 and the integrated operational amplifier chip U2 adopt LF 347; multiplier U3 employs AD 633;
the 1 st pin of the integrated operational amplifier chip U1 is connected with one end of a second resistor R2; the 2 nd pin is connected with the other end of the second resistor R2 and one end of the first resistor R1, and the other end of the first resistor R1 is connected with the 7 th pin of the integrated operational amplifier chip U2; the 3 rd pin is grounded; the 4 th pin is connected with a positive 15V power supply; the 5 th pin is grounded; the 6 th pin is connected with one ends of a third resistor R3 and a fourth resistor R4, and the other end of the third resistor R3 is connected with the 14 th pin of the integrated operational amplifier chip U2; the 7 th pin is connected with the other end of the fourth resistor R4; the 8 th pin is connected with one end of an eighth resistor R8; the 9 th pin is connected with one end of a seventh resistor R7 and the other end of an eighth resistor R8, and the other end of the seventh resistor R7 is connected with the 14 th pin of the integrated operational amplifier chip U1; the 10 th pin is grounded; the 11 th pin is connected with a negative 15V power supply; the 12 th pin is grounded; the 13 th pin is connected with one end of a fifth resistor R5, one end of a sixth resistor R6 and one end of a second capacitor C2, the other end of the fifth resistor R5 is connected with the 7 th pin of the integrated operational amplifier U1 chip, and the other end of the sixth resistor R6 is connected with the 8 th pin of the integrated operational amplifier U1 chip; the 14 th pin is connected to the other end of the second capacitor C2.
The 1 st pin of the integrated operational amplifier chip U2 is connected with one end of a ninth resistor R9; the 2 nd pin is connected with the other end of the ninth resistor R9 and one end of the tenth resistor R10, and the other end of the tenth resistor R10 is connected with the 7 th pin of the multiplier U3; the 3 rd pin is grounded; the 4 th pin is connected with a positive 15V power supply; the 5 th pin is grounded; a 6 th pin is connected with one end of a third capacitor C3, one end of an eleventh resistor R11, one end of a twelfth resistor R12, one end of a thirteenth resistor R13 and one end of a fourteenth resistor R14, the other end of the eleventh resistor R11 is connected with a 14 th pin of an integrated operational amplifier chip U1, the other end of the twelfth resistor R12 is connected with a 1 st pin of the integrated operational amplifier chip U1, the other end of the thirteenth resistor R13 is connected with an 8 th pin of the integrated operational amplifier chip U2, and the other end of the fourteenth resistor R14 is connected with a 1 st pin of the integrated operational amplifier chip U2; the 8 th pin is connected with one end of a first capacitor C1; the 9 th pin is connected with one end of an eighteenth resistor R18, one end of a nineteenth resistor R19 and the other end of a first capacitor C1, the other end of the eighteenth resistor R18 is connected with the 1 st pin of the integrated operational amplifier chip U1, and the other end of the nineteenth resistor R19 is connected with the 8 th pin of the integrated operational amplifier chip U2; the 10 th pin is grounded; the 11 th pin is connected with a negative 15 power supply; the 12 th pin is grounded; the 13 th pin is connected with one end of a fifteenth resistor R15, one end of a sixteenth resistor R16, one end of a seventeenth resistor R17 and one end of a fourth capacitor C4, and the other end of the fifteenth resistor R15 is connected with the 1 st pin of the integrated operational amplifier chip U1; the other end of the sixteenth resistor R16 is connected with the 8 th pin of the integrated operational amplifier chip U1, and the other end of the seventeenth resistor R17 is connected with the 1 st pin of the integrated operational amplifier chip U2; the 14 th pin is connected to the other end of the fourth capacitor C4.
The 1 st pin of the multiplier U3 is connected with the 14 th pin of the integrated operational amplifier chip U1; the 2 nd pin is grounded; the 3 rd pin is connected with the 14 th pin of the integrated operational amplifier chip U2; the 4 th pin is grounded; the 5 th pin is connected with a negative 15V power supply; the 6 th pin is grounded; the 7 th pin is connected with one end of a tenth resistor R10; the 8 th pin is connected with a positive 15V power supply.
The invention designs an equivalent circuit model of a novel chaotic system with rich dynamic characteristics, which comprises 2 integrated operational amplifier chips and 1 multiplier, and has clear and simple structure and easy realization. The equivalent circuit model can be used for chaotic circuit experiments and applications, and has significant significance for the research of nonlinear circuits and other problems.
The novel chaotic system circuit model provided by the invention utilizes the circuit to simulate the relation among the differential equations of the chaotic system, and particularly realizes the mathematical relation among the differential equations of the chaotic system. The invention utilizes an integrated operational amplifier chip and an analog multiplier circuit to realize corresponding operation in a chaotic system equation, wherein the integrated operational amplifier chip is mainly used for realizing inverse operation, proportional operation, summation operation and integral operation, and the analog multiplier is used for realizing product operation.
Drawings
Fig. 1 is an equivalent circuit block diagram of the present invention.
Fig. 2 is an equivalent analog circuit diagram of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
The theoretical starting point of the invention is a novel four-dimensional chaotic system, which is shown by the following expression:
wherein x, y, z and w are dimensionless state variables of the system, a, b, c, d, e, f, g and h are coefficients,
denotes the differential of x, y, z, w.
As shown in fig. 1, the equivalent analog circuit based on the novel four-dimensional chaotic system of the present embodiment includes an integrated operational amplifier chip U1, an integrated operational amplifier chip U2 and a multiplier U3. The variables x, y and z are respectively subjected to the operational amplifier 3, the operational amplifier 2 and the operational amplifier 1 in the integrated operational amplifier chip U1 to obtain variables-x, -y and-z; the variable-y and-x are subjected to operational amplifier 4 in the integrated operational amplifier chip U1 to obtain a variable x; the variables x and y pass through a multiplier U3 to obtain xy; xy is obtained through an operational amplifier 1 in an integrated operational amplifier chip U2; -x, -z and-xy pass through an operational amplifier 4 in an integrated operational amplifier chip U2 to obtain a variable y; x, -z, w and-xy pass through an operational amplifier 2 in an integrated operational amplifier chip U2 to obtain a variable z; the variables-z and w are subjected to an operational amplifier 3 in an integrated operational amplifier chip U2 to obtain a variable w; the integrated operational amplifier U1 mainly realizes inverse proportion operation, summation operation and integral operation; the integrated operational amplifier U2 mainly realizes summation operation and integration operation; the multiplier U3 performs a multiplication operation of the two signals. LF347 is adopted for U1 and U2, AD633 is adopted for U3, and LF347 and AD633 are all in the prior art.
As shown in fig. 2, 4 operational amplifiers are integrated in the integrated operational amplifier chip U1, wherein the operational amplifiers corresponding to the 1 st, 2 nd and 3 th pins form an inverting proportional operational circuit with the first resistor R1 and the second resistor R2, and obtain-z, the input variable is input to the 2 nd pin of the integrated operational amplifier chip U1 through the first resistor R1, and the output of the pin 1 of U1 is-z:
the operational amplifiers corresponding to the 5 th, 6 th and 7 th pins of the integrated operational amplifier chip U1, the third resistor R3 and the fourth resistor R4 form an inverse proportion operational circuit, y is obtained, the input variable is y, the y is input to the 6 th pin of the integrated operational amplifier chip U1 through the third resistor R3, and the output of the pin 7 of U1 is-y:
the operational amplifier corresponding to the 8 th, 9 th and 10 th pins of the integrated operational amplifier chip U1, the seventh resistor R7 and the eighth resistor R8 form an inverse proportion operational circuit, and obtain-x, wherein an input variable is x, the x is input to the 9 th pin of the integrated operational amplifier chip U1 through the seventh resistor R7, and the output of the pin 8 of U1 is-x:
the operational amplifier corresponding to the 12 th, 13 th and 14 th pins of the integrated operational amplifier chip U1, the fifth resistor R5, the sixth resistor R6 and the second capacitor C2 form an inverting proportional-integral operational circuit, x is obtained, an input variable-y is input to the 13 th pin of the integrated operational amplifier chip U1 through the fifth resistor R5, the input variable x is input to the 13 th pin of the integrated operational amplifier chip U1 through the sixth resistor R6, and the output of the pin 14 of the U1 is x:
4 operational amplifiers are integrated in the integrated operational amplifier chip U2, wherein the operational amplifiers corresponding to the pins 1, 2 and 3 of the integrated operational amplifier chip U2, the ninth resistor R9 and the tenth resistor R10 form an inverse proportion operational circuit, so that-xy is obtained, an input variable xy is input to the pin 2 of the integrated operational amplifier chip U2 through the tenth resistor R10, and the output of the pin 1 of U2 is-xy:
the operational amplifiers corresponding to the pins 5, 6 and 7 of the integrated operational amplifier chip U2, the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13, the fourteenth resistor R14 and the third capacitor C3 form four inverse proportion summation operation and integration operation circuits to obtain z, and input variables x, -z, w and-xy are input to the pin 6 of the integrated operational amplifier chip U2 through the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13 and the fourteenth resistor R14, wherein xy is obtained by a multiplier U3, -xy is obtained by the pin 1 of the integrated operational amplifier chip U2, and the output of the pin 7 of the U2 is z:
the operational amplifiers corresponding to the 8 th, 9 th and 10 th pins of the integrated operational amplifier chip U2, the eighteenth resistor R18, the nineteenth resistor R19 and the first capacitor C1 form an inverting proportional-integral operational circuit to obtain w, an input variable-z is input to the 9 th pin of the integrated operational amplifier chip U2 through the eighteenth resistor R18, the input variable w is input to the 9 th pin of the integrated operational amplifier chip U2 through the nineteenth resistor R19, and the output of the pin 8 of the U2 is w:
the operational amplifiers corresponding to the 12, 13 and 14 pins of the integrated operational amplifier chip U2, the fifteenth resistor R15, the sixteenth resistor R16, the seventeenth resistor R17 and the fourth capacitor C4 form three inverse proportional summing and integrating operational circuits, the input variables are-xy, -x and-z, wherein the-xy term is obtained by the multiplier U3 and the operational amplifier 1 in the integrated operational amplifier U2, and is input to the 2 nd pin of the integrated operational amplifier chip U2 by the seventeenth resistor R17, the variables-x and-z are input to the 13 th pin of the integrated operational amplifier chip U2 by the sixteenth resistor R16 and the fifteenth resistor R15, respectively, and the output of the U2 pin 14 is y:
the multiplier U3 has a model number AD633, and is used to perform the multiplication of the variables x and y, i.e., the output of the seventh pin of the multiplier U3 is xy.
The 1 st pin of the integrated operational amplifier chip U1 is connected with one end of a second resistor R2 and used as an output end of a-z, the 2 nd pin is connected with one end of a first resistor R1 and the other end of a second resistor R2, the 3 rd pin is grounded, the 4 th pin is connected with a positive 15V power supply, the 5 th pin is grounded, the 6 th pin is connected with one end of a third resistor R3 and one end of a fourth resistor R4, the 7 th pin is connected with the other end of a fourth resistor R4 and used as an output end of a-y, the 8 th pin is connected with one end of a first capacitor C6 and used as an output end of a w, the 9 th pin is connected with one end of a seventh resistor R7, the 8 th pin is connected with one end of an eighth resistor R8 and used as an output end of a-x, the 10 th pin is grounded, the 11 th pin is connected with a negative 15V power supply, the 12 th pin is grounded, the 13 th pin is connected with one end of a second capacitor C2 and one end of a fifth resistor R36, the 14 th pin is connected to the other end of the second capacitor C2 and serves as an output terminal for x.
A 1 st pin of the integrated operational amplifier chip U2 is connected with one end of a ninth resistor R9 and used as an output end of-xy, a 2 nd pin is connected with the other end of the ninth resistor R9 and one end of a tenth resistor R10, a 3 rd pin is grounded, a 4 th pin is connected with a positive 15V power supply, a 5 th pin is grounded, a 6 th pin is connected with one end of an eleventh resistor R11, one end of a twelfth resistor R12, one end of a thirteenth resistor R13, one end of a fourteenth resistor R14 and one end of a third capacitor C3, a 7 th pin is connected with the other end of the third capacitor C3 and used as an output end of a variable z, and an 8 th pin is connected with one end of the first capacitor C1 and used as an output end of w; the 9 th pin is connected with one end of an eighteenth resistor R18, one end of a nineteenth resistor R19 and the other end of a first capacitor C1, the 10 th pin is grounded, the 11 th pin is connected with a negative 15V power supply, the 12 th pin is grounded, the 13 th pin is connected with one end of a fifteenth resistor R15, one end of a sixteenth resistor R16 and one end of a seventeenth resistor R17, and the 14 th pin is connected with the other end of a fourth capacitor C4 and serves as an output end of y.
The 2 nd, 4 th and 6 th pins of the multiplier U3 are grounded, the 5 th pin is connected with a negative 15V power supply, the 7 th pin is used as an xy output end, and the 8 th pin is connected with a positive 15V power supply.
It should be appreciated by those skilled in the art that the above embodiments are only used for verifying the present invention, and are not to be construed as limiting the present invention, and that the changes and modifications of the above embodiments are within the scope of the present invention.
Claims (2)
1. An equivalent circuit model of a novel chaotic system is characterized in that the model is designed based on the following mathematical relationship:
wherein x, y, z and w are dimensionless state variables of the chaotic system, a, b, c, d, e, f, g and h are coefficients, and the variables x, y and z are respectively subjected to a third operational amplifier, a second operational amplifier and a first operational amplifier in an integrated operational amplifier chip U1 to obtain variables-x, -y and-z; the variable-y and the variable-x are subjected to a fourth operational amplifier 4 in the integrated operational amplifier chip U1 to obtain a variable x; the variables x and y pass through a multiplier U3 to obtain a variable xy; the variable xy is subjected to a first operational amplifier in the integrated operational amplifier chip U2 to obtain a variable-xy; the variables-x, -z and-xy are subjected to a fourth operational amplifier in the integrated operational amplifier chip U2 to obtain a variable y; the variables x, -z, w and-xy are processed by a second operational amplifier in the integrated operational amplifier chip U2 to obtain a variable z; the variables-z and w pass through a third operational amplifier in the integrated operational amplifier chip U2 to obtain a variable w; the integrated operational amplifier U1 mainly realizes inverse proportion operation, summation operation and integral operation; the integrated operational amplifier U2 mainly realizes summation operation and integration operation;
the integrated operational amplifier U1 and the integrated operational amplifier U2 adopt LF347N, and four operational amplifiers are shared in the integrated operational amplifier U1 and the integrated operational amplifier U2; the 1 st pin of the integrated operational amplifier U1 outputs the-z term, the 7 th pin of the integrated operational amplifier U1 outputs the-y term, the 8 th pin of the integrated operational amplifier U1 outputs the-x term, and the 14 th pin of the integrated operational amplifier U1 outputs the x term; the 1 st pin of the integrated operational amplifier U2 outputs the xy term, the 7 th pin of the integrated operational amplifier U2 outputs the z term, the 8 th pin of the integrated operational amplifier U2 outputs the w term, and the 14 th pin of the integrated operational amplifier U2 outputs the y term; the 7 th pin of the multiplier U3 outputs an xy term;
the 1 st pin of the integrated operational amplifier chip U1 is connected with one end of a second resistor R2 and used as an output end of a-z, the 2 nd pin of the integrated operational amplifier chip U1 is connected with one end of a first resistor R1 and the other end of a second resistor R2, the 3 rd pin of the integrated operational amplifier chip U1 is grounded, the 4 th pin of the integrated operational amplifier chip U1 is connected with a positive 15V power supply, the 5 th pin of the integrated operational amplifier chip U1 is grounded, the 6 th pin of the integrated operational amplifier chip U1 is connected with one end of a third resistor R3 and one end of a fourth resistor R4, the 7 th pin of the integrated operational amplifier chip U1 is connected with the other end of a fourth resistor R4 and used as an output end of a-y, the 8 th pin of the integrated operational amplifier chip U1 is connected with one end of an eighth resistor R8 and used as an output end of an item-x, the 9 th pin of the integrated operational amplifier chip U1 is connected with one end of a seventh resistor R7 and used, The other end of the eighth resistor R8 is connected, the 10 th pin of the integrated operational amplifier chip U1 is grounded, the 11 th pin of the integrated operational amplifier chip U1 is connected with a negative 15V power supply, the 12 th pin of the integrated operational amplifier chip U1 is grounded, and the 13 th pin of the integrated operational amplifier chip U1 is connected with one end of the second capacitor C2, one end of the fifth resistor R5 and one end of the sixth resistor R6; the 14 th pin of the integrated operational amplifier chip U1 is connected with the other end of the second capacitor C2 and serves as an output end of the x; the 1 st pin of the integrated operational amplifier chip U2 is connected with one end of a ninth resistor R9 and used as an output end of-xy, the 2 nd pin of the integrated operational amplifier chip U2 is connected with the other end of a ninth resistor R9 and one end of a tenth resistor R10, the 3 rd pin of the integrated operational amplifier chip U2 is grounded, the 4 th pin of the integrated operational amplifier chip U2 is connected with a positive 15V power supply, the 5 th pin of the integrated operational amplifier chip U2 is grounded, the 6 th pin of the integrated operational amplifier chip U2 is connected with one end of an eleventh resistor R11, one end of a twelfth resistor R12, one end of a thirteenth resistor R13, one end of a fourteenth resistor R14 and one end of a third capacitor C3, the 7 th pin of the integrated operational amplifier chip U2 is connected with the other end of a third capacitor C3 and used as an output end of a variable z, the 8 th pin of the integrated operational amplifier chip U2 is connected with one end of a first capacitor C1, and serves as an output terminal of w; the 9 th pin of the integrated operational amplifier chip U2 is connected with one end of an eighteenth resistor R18, one end of a nineteenth resistor R19 and the other end of a first capacitor C1, the 10 th pin of the integrated operational amplifier chip U2 is grounded, the 11 th pin is connected with a negative 15V power supply, the 12 th pin of the integrated operational amplifier chip U2 is grounded, the 13 th pin of the integrated operational amplifier chip U2 is connected with one end of a fifteenth resistor R15, one end of a sixteenth resistor R16 and one end of a seventeenth resistor R17, and the 14 th pin of the integrated operational amplifier chip U2 is connected with the other end of a fourth capacitor C4 and serves as an output end of y.
2. The novel chaotic system equivalent circuit model as set forth in claim 1, wherein: the 1 st pin of the multiplier U3 is connected with the 14 th pin of the integrated operational amplifier chip U1; the 2 nd pin of the multiplier U3 is grounded; the 3 rd pin of the multiplier U3 is connected with the 14 th pin of the integrated operational amplifier chip U2; the 4 th pin of the multiplier U3 is grounded; the 5 th pin of the multiplier U3 is connected with a negative 15V power supply; the 6 th pin of the multiplier U3 is grounded; the 7 th pin of the multiplier U3 is connected with one end of a tenth resistor R10; the 8 th pin of multiplier U3 is connected to a positive 15 volt supply.
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