CN108735740A - Semiconductor devices - Google Patents
Semiconductor devices Download PDFInfo
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- CN108735740A CN108735740A CN201710243320.3A CN201710243320A CN108735740A CN 108735740 A CN108735740 A CN 108735740A CN 201710243320 A CN201710243320 A CN 201710243320A CN 108735740 A CN108735740 A CN 108735740A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
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Abstract
A kind of semiconductor devices is provided.The semiconductor devices includes：Grid structure is laminated, including upper selection gate pattern, illusory gate pattern and the unit gate pattern for being layered on substrate and extending in a first direction；Active patterns are separated from each other while across stacking grid structure；And gate dielectric pattern, it is plugged between unit gate pattern and active patterns, between upper selection gate pattern and active patterns and between illusory gate pattern and active patterns.It is separated from each other on the uppermost unit gate pattern that upper selection gate pattern is arranged in unit gate pattern and in the second direction for intersecting first direction.Illusory gate pattern is arranged between uppermost unit gate pattern and upper selection gate pattern and is separated from each other in a second direction.
Description
Technical field
A kind of method that present inventive concept is related to semiconductor devices and forms the semiconductor devices.
Background technology
With the large capacity for electronic device and system, multi-functional and/or compact increased demand, have been incorporated into
Various technologies are to be highly integrated the memory device used wherein.It is highly integrated for memory device, develop shape
At the increasingly finer pattern of device.However, in order to form fine pattern, expensive equipment is needed.In addition, although using
Expensive equipment, but often can not as expected realize finer pattern.Therefore, as overcoming the problems, such as these alternative
Case has energetically developed the highly integrated technology for semiconductor devices.
Invention content
Inventive concept provides a kind of semiconductor devices optimized in order to highly integrated.
Inventive concept also provides a kind of semiconductor devices that wherein reliability is enhanced.
According on one side, a kind of semiconductor devices is directed toward in inventive concept, which includes：Grid structure is laminated,
Including upper selection gate pattern, illusory gate pattern and the unit gate pattern for being layered on substrate and extending in a first direction；Active figure
Case is separated from each other while across stacking grid structure；And gate dielectric pattern, it is plugged on unit gate pattern and active figure
Between case, between upper selection gate pattern and active patterns and between illusory gate pattern and active patterns.In such case
Under, on the upper uppermost unit gate pattern that is arranged in unit gate pattern of selection gate pattern and intersecting the of first direction
It is separated from each other on two directions.Illusory gate pattern is arranged between uppermost unit gate pattern and upper selection gate pattern and the
It is separated from each other on two directions.
A kind of semiconductor devices is directed toward in inventive concept according to another aspect, which includes：Grid structure is laminated,
Including upper selection gate pattern, illusory gate pattern and the unit gate pattern for being layered on substrate and extending in a first direction；And it hangs down
Straight structure is separated from each other while across stacking grid structure.In this case, upper selection gate pattern is arranged in unit grid
It is separated from each other on uppermost unit gate pattern in pattern and in the second direction for intersecting first direction, illusory grid figure
Case is arranged between uppermost unit gate pattern and upper selection gate pattern and is separated from each other in a second direction.
Description of the drawings
Attached drawing is included to provide and be further understood to inventive concept, and is incorporated into this specification and constitutes this explanation
A part for book.Attached drawing shows the exemplary embodiment of inventive concept, and is used for describing inventive concept together with specification
Principle.
Fig. 1 is the plan view for the semiconductor devices for showing the embodiment according to present inventive concept.
Fig. 2A to Fig. 2 F is section for the method for showing the formation semiconductor devices according to an embodiment of inventive concept
Face figure.
Fig. 3 A to Fig. 3 E are sections for the method for showing the formation semiconductor devices according to another embodiment of inventive concept
Face figure.
Fig. 4 A and Fig. 4 B are sections for the method for showing the formation semiconductor devices according to another embodiment of inventive concept
Face figure.
Fig. 5 is the sectional view according to the semiconductor devices of another embodiment of inventive concept.
Fig. 6 is the sectional view according to the semiconductor devices of another embodiment of inventive concept.
Fig. 7 is the sectional view according to the semiconductor devices of another embodiment of inventive concept.
Fig. 8 is the sectional view according to the semiconductor devices of another embodiment of inventive concept.
Fig. 9 is the plan view for the semiconductor devices for showing the embodiment according to inventive concept.
Figure 10 and Figure 11 is the sectional view according to the semiconductor devices of another embodiment of inventive concept.
Figure 12 is the sectional view according to the semiconductor devices of another embodiment of inventive concept.
Figure 13 is the plan view for the semiconductor devices for showing the embodiment according to inventive concept.
Figure 14 is the sectional view according to the semiconductor devices of another embodiment of inventive concept.
Figure 15 be include block diagram according to the electronic system of the semiconductor devices of the embodiment of present inventive concept.
Figure 16 is to show to include the box according to the storage card of the semiconductor devices of an embodiment of present inventive concept
Figure.
Specific implementation mode
The semiconductor devices of embodiment according to inventive concept is described below with reference to accompanying drawings.However, inventive concept
Exemplary implementations can be embodied in many different forms and should not be construed as limited to embodiments set forth herein.And
Being to provide these embodiments makes the disclosure thoroughly and complete, and the range of inventive concept will be made to be fully conveyed to ability
The embodiment of field technique personnel, inventive concept will be limited only by the appended claims.
As used herein, term "and/or" is intended to include arbitrary and all group of one or more related Listed Items
It closes.It will be understood that when an element or layer are referred to as in another element or layer "upper", it can directly on another element or layer,
Either there may be elements or layer between two parties.It will be understood that clear although term first, second, third, etc. may be used herein
Various component, assembly units, regions, layers, and/or portions are described to Chu, but these component, assembly units, regions, layers, and/or portions are not answered
It is limited by these terms.It will be understood that although may be used herein, term is upper and lower etc. to be explicitly described various component, assembly units, area
Domain, layer and/or part, but these component, assembly units, regions, layers, and/or portions do not answer it is limited by these terms.In the accompanying drawings,
The thickness and relative thickness of layer and region are exaggerated to effectively description technique details.
By the descriptions of F referring to Figures 1 and 2 according to the semiconductor devices of an embodiment of present inventive concept.Fig. 1 is basis
The plan view of cellular zone in the semiconductor devices of one embodiment of present inventive concept.Fig. 2 F are the semiconductor devices along figure
The sectional view that line I-I' shown in 1 is intercepted.
F referring to Figures 1 and 2, semiconductor substrate (below, being referred to as " substrate ") 100 are provided.Substrate 100 can wrap
Include the well region doped with the first conductiving doping agent.Well region can be provided in the substrate 100 of cellular zone.
The grid structure of stacking can be arranged on the substrate 100.The grid structure of stacking can be on the substrate 100 along first
The line form that direction (such as X-direction) extends.The grid structure of stacking can be on the substrate 100 along second direction (such as Y-axis
Direction) arrangement.Second direction can intersect with first direction.
The grid structure of stacking may include unit gate pattern CG, upper selection gate pattern SSG and lower selection gate pattern GSG, grid
Electrode insulation pattern 114, bottom insulating pattern 112 and upper insulating pattern 119.Three layers of unit is illustrated by way of example in Fig. 2 F
The number of plies of gate pattern CG, unit gate pattern CG are not limited to the number of plies shown in Fig. 2 F.For example, the number of plies of unit gate pattern CG can be with
It is tens or hundreds of layers.
Insulating pattern 114 can be alternately laminated on the substrate 100 between unit gate pattern CG and grid.Unit gate pattern CG
It can be the line form extended along a first direction on the substrate 100.Unit gate pattern CG can include conductive material.Unit grid
Pattern CG can include the metallic compound of the semiconductor of doping, metal or conduction.Insulating pattern 114 can be distinguished between grid
It is arranged between unit gate pattern CG, on uppermost unit gate pattern CG and at nethermost unit gate pattern CG
Face.
Lower selection gate pattern GSG can be plugged between substrate 100 and nethermost unit gate pattern CG.Lower selection grid figure
Case GSG may include the material with the material identical of unit gate pattern CG.Bottom insulating pattern 112 can be plugged on lower selection grid figure
Between case GSG and substrate 100.In an embodiment of present inventive concept, bottom insulating pattern 112 can form relatively
It is thin.For example, bottom insulating pattern 112 can be plugged between lower selection gate pattern GSG and substrate 100 with sufficiently thin thickness, make
It obtains and generates potential between substrate 100 and lower selection gate pattern GSG during the operation of device.
Upper selection gate pattern SSG can be arranged on uppermost unit gate pattern CG.Upper insulating pattern 119 can be arranged
On upper selection gate pattern SSG.
The width for forming the insulating pattern 112,114 and 119 of a stacking grid structure can be with substrate 100 and insulating pattern
112, the distance between 114 and 119 proportionally narrow.For example, near substrate 100 bottom insulating pattern 112 have it is most wide
Width, and farthest away from the upper insulating pattern 119 of substrate 100 have most narrow width.In addition, insulating pattern 112,114 and 119
Side wall can be at an acute angle with the lower surface of insulating pattern 112,114 and 119.
Similar to insulating pattern 112,114 and 119, the width of gate pattern GSG, CG and SSG can be with substrates 100 and grid figure
The distance between case GSG, CG and SSG proportionally narrow.The side wall of gate pattern GSG, CG and SSG can be with gate pattern GSG, CG
It is at an acute angle with the lower surface of SSG.Due to the width of insulating pattern 112,114 and 119 and gate pattern GSG, CG and SSG, grid are laminated
The side wall of structure can be with the normal of the upper surface of substrate 100 at the angle more than 0 °.It is, stacking grid structure can have
Inclined side wall.For this purpose, interval between the side wall of stacking grid structure adjacent to each other can be as side wall be further from substrate 100
And it broadens.Largest interval d2 between adjacent stacking grid structure can be with the number of plies of the gate pattern and insulating pattern of stacking
Increase and increases.Structural insulation pattern 124 is filled between space between adjacent stacking grid structure can use grid.It is tied between grid
The width of structure insulating pattern 124 can reduce towards substrate 100.
One stacking grid structure may include multiple upper selection gate pattern SSG.For example, a stacking grid structure may include
Gate pattern SSG is selected in a pair being separated from each other.Pairs of upper selection gate pattern SSG can be arranged in uppermost unit grid figure
With the d1 that is spaced a predetermined interval apart from each other therebetween on case CG.Upper isolated insulation pattern 118 can be plugged on pairs of upper selection grid
Between pattern SSG.Interval d1 between pairs of upper selection gate pattern SSG can be than the maximum between adjacent stacking grid structure
It is short to be spaced d2.The opposite side wall of pairs of upper selection gate pattern SSG can correspond to the normal of the upper surface of substrate 100.It can
Selection of land, the angle between the normal of the upper surface of the opposite side wall and substrate 100 of pairs of upper selection gate pattern SGS are more than
0 °, but the angle that the normal of the upper surface of substrate 100 can be less than and be laminated between the side wall of grid structure.
Active patterns 121 can pass through a stacking grid structure.Active patterns 121 can form tool in grid structure is laminated
There is the matrix of first direction and the row and column of second direction.In grid structure is laminated, according to present inventive concept embodiment party
Formula, two active patterns 121 can be arranged in a second direction.
Active patterns 121 can be provided through in the hole 120 of stacking grid structure.Hole 120 can have to substrate 100
The inclined side wall in upper surface.The upper width in hole 120 can be more than the lower width in hole 120.Active patterns 121 fill hole 120
And it is upwardly extended along the side wall of the side wall of gate pattern GSG, CG and SSG and insulating pattern 112,114 and 119.Active patterns
121 lower surface can contact the well region of substrate 100.Optionally for semiconductor devices shown in the accompanying drawings, active patterns 121
The side wall in hole 120 is covered, but can incompletely fill hole 120.For example, active patterns 121 can be open tubular column.Active figure
The inner space of case 121 can be filled with insulating materials.
Active patterns 121 may include at least one of the semi-conducting material for including IVA races element.For example, active figure
Case 121 includes single crystal semiconductor or poly semiconductor.Active patterns 121 can include undoped semi-conducting material.It is optional
Ground, active patterns 121 can include the semi-conducting material doped with the first conductiving doping agent.
Dopant areas 122 can be arranged in the topmost portion of active patterns 121.Dopant areas 122 can be single
The drain region of member string.Dopant areas 122 can be doped with the second conductiving doping agent different from the first conductiving doping agent.
Another stacking grid structure can be adjacent to stacking grid structure setting described above on the substrate 100.This another
Grid structure is laminated can be in a second direction adjacent to the stacking grid structure.Common source region 102 can be arranged adjacent two
Between a stacking grid structure.The edge of common source region 102 extends in the substrate 100 below stacking grid structure.According to
One embodiment of present inventive concept, common source region 102 can be arranged at the both ends of stacking grid structure.Common source region
102 can be doped with the second conductiving doping agent.
Gate dielectric pattern 125 can be arranged between gate pattern GSG, CG and SSG and active patterns 121.Gate dielectric
Pattern 125 extends in the upper and lower surface of gate pattern GSG, CG and SSG.
Gate dielectric pattern 125 can further extend on the opposite side wall of pairs of upper selection gate pattern SSG.Grid
Dielectric pattern 125 can be contacted with upper isolated insulation pattern 118.In addition, gate dielectric pattern 125 extends to forming layer
On the side wall of the insulating pattern 112,114 and 119 of the side wall of stacked gate structure.
With reference to Fig. 3 E, on the contrary, gate dielectric pattern 125 can not extend to the phase of pairs of upper selection gate pattern SSGa
To side wall on.In this case, the opposite side wall of pairs of upper selection gate pattern SSGa can be with upper isolated insulation figure
Structural insulation pattern 124 contacts between case 118a and grid.The width of upper isolated insulation pattern 118a can subtract towards substrate 100
It is small.Between the normal of the upper surface of substrate 100 and the side wall of isolated insulation pattern 118a in the contact of upper selection gate pattern SSGa
Angle can be more than 0 °, while less than substrate 100 upper surface normal and be laminated grid structure side wall between angle.
Bit line 134 can be provided on active patterns 121.Bit line 134 can be electrically connected to doping by bit line contact 133
Agent region 122.Bit line contact 133 can pass through the layer insulation pattern 131 in stacking grid structure.Bit line 134 can be second
Side upwardly extends.One bit line 134 may be electrically connected to the multiple active patterns 121 arranged along second direction.
According to this embodiment of present inventive concept, it can be provided in reliability and be further improved and in order to highly collect
At and optimize semiconductor devices.Specifically, adjacent when whole active patterns in cellular zone share a stacking grid structure
Unit between interference be significantly increased so as to cause the mistake in read operation and/or write operation.However, according to present inventive concept
This embodiment, due to whole active patterns in cellular zone be not arranged in one stacking grid structure in, so by adjacent
Operating mistake caused by interference between unit can be significantly reduced.In addition, as described above, being laminated in grid structure at one
Pairs of upper selection gate pattern between interval d1 can be shorter than the interval d2 being laminated between grid structure.According to present inventive concept
This embodiment, unit adjacent to each other, which is arranged, in a second direction is laminated at one in grid structure.In addition, in second direction
Upper unit adjacent to each other is connected to the pairs of upper selection gate pattern SSG being separated from each other, to form multiple unit strings.Also
It is that unit adjacent to each other can be separated into discrete cell by the upper selection gate pattern SSG of separation in a second direction.Cause
This, can provide and be suitable for highly integrated semiconductor devices.
Now with reference to Fig. 1 and Fig. 4 B descriptions according to the semiconductor devices of another embodiment of present inventive concept.Fig. 4 B
The sectional view for the line I-I' interceptions shown in Fig. 1 that are the semiconductor devices.In the semiconductor devices shown in figure 4b, in addition to
Except the component different from the component of semiconductor devices shown in Fig. 2 F, detailed description will be omitted.
With reference to Fig. 4 B, a stacking grid structure may include the multiple lower selection grid figures being spaced from a second direction
Case GSGa.For example, a stacking grid structure may include selecting gate pattern GSGa under a pair extended in a first direction.Under every
It can be plugged on from insulating pattern 114a between pairs of lower selection gate pattern GSGa.Gate dielectric pattern 125 can be arranged
On the lower upper surface, lower surface and lateral wall for selecting gate pattern GSGa.In addition, be surrounded by lower selection gate pattern GSGa grid
Dielectric pattern 125 extends to lower selection gate pattern GSGa and is adjacent on the madial wall of active patterns 121.
It is laminated in grid structure at one, pairs of lower selection gate pattern GSGa adjacent to each other can divide in a second direction
It is not included in different unit strings.As a result, semiconductor devices can reduce by the unit that is included in adjacent cells string it
Between interference caused by read operation mistake.
Describe to be formed the semiconductor of an embodiment according to present inventive concept now with reference to Fig. 1 and Fig. 2A to Fig. 2 F
The example of the method for device.The sectional view of Fig. 2A to Fig. 2 F line I-I' interceptions shown in Fig. 1 that are the semiconductor devices.About
The component of F descriptions referring to Figures 1 and 2, will not repeat the detailed description of those components.
With reference to Fig. 2A, insulating layer 112 and 114 and sacrificial layer 113,115 and 117 be alternately formed on substrate 100.Absolutely
Edge layer 112 and 114 and sacrificial layer 113,115 and 117 can respectively include the material of the etching selectivity for having different.Example
Such as, insulating layer 112 and 114 includes the oxide of semiconductor element, and sacrificial layer 113,115 and 117 includes the nitrogen of semiconductor element
Compound.Uppermost sacrificial layer 117 and nethermost sacrificial layer 113 can be thicker than the sacrificial layer 115 of plant therebetween.It is plugged on
The thickness of sacrificial layer 115 between uppermost sacrificial layer 117 and nethermost sacrificial layer 113 can be uniform.
Uppermost sacrificial layer 117 can be separated into multiple layers by anisotropic etching.What is detached is uppermost
Space between sacrificial layer 117 can be the form of slits extended in a first direction.The uppermost sacrificial layer 117 detached
Between interval can be " d1-2a ".Here, between symbol " d1 " indicates between the upper selection gate pattern that will be described later
Every symbol " a " indicates the thickness for the gate dielectric pattern that will be described later.Upper isolated insulation pattern 118 can be formed in by
Between the uppermost sacrificial layer 117 of separation.
With reference to Fig. 2 B, upper insulating layer 119 can be formed on the sacrificial layer 117 and upper isolated insulation pattern 118 of separation.On
Insulating layer 119 can together form with upper isolated insulation pattern 118 or can be by going up isolated insulation pattern 118 with formation
The separated technique of technique is formed.Upper isolated insulation pattern 118 and upper insulating layer 119 may include the material with insulating layer 112 and 114
Expect identical material.
Optionally, upper isolated insulation pattern 118, upper insulating layer 119 and insulating layer 112 and 114 can respectively include not
Same material.
Hole 120 can be formed on the substrate 100 to pass through insulating layer 112,114 and 119 and sacrificial layer 113,115 and
117.Hole 120 can form a pair of of the column arranged along a first direction.Hole 120 can expose the upper surface of substrate 100.Hole 120
There can be the side wall limited by the side wall of insulating layer 112,114 and 119 and the side wall of sacrificial layer 113,115 and 117.
Active patterns 121 can be formed in hole 120.The lower surface of active patterns 121 can connect with the well region of substrate 100
It touches.Active patterns 121 can fill hole 120.Active patterns 121 can be across insulating layer 112,114 and 119 and sacrificial layer
113,115 and 117 cylindricality formula.Optionally, active patterns 121 can be conformally formed side wall and substrate 100 in hole 120
On upper surface.Active patterns 121 can be the form of unfilled column.The upper surface of active patterns 121 can be flattened, from
And expose the upper surface of upper insulating layer 119.
Dopant areas 122 can be formed in the topmost portion of active patterns 121.Dopant areas 122 can pass through
Ion implanting is formed.On the contrary, dopant areas 122 can also be formed by in-situ process.
Initiation layer stacked gate structure passes through via anisotropic etching patterned insulation layer 112,114 and 119 and sacrificial layer
113,115 and 117 and formed.Groove 123 is formed between initiation layer stacked gate structure to expose the upper surface of substrate 100.Groove
123 can extend along a first direction.The side wall and patterned sacrificial layer of patterned insulating layer 112,114 and 119
113,115 and 117 side wall can be exposed by groove 123.The side wall and figure of patterned insulating layer 112,114 and 119
The side wall of the sacrificial layer 113,115 and 117 of case can be the side wall of initiation layer stacked gate structure.Patterned insulating layer 112,
114 and 119 can be referred to as insulating pattern.Specifically, patterned insulating layer 112 can be referred to as bottom insulating pattern, pattern
The insulating layer 114 of change can be referred to as insulating pattern between grid, and patterned insulating layer 119 can be referred to as insulating pattern.
Patterned sacrificial layer 113,115 and 117 can be referred to as sacrificial pattern.
The side wall of initiation layer stacked gate structure can not be exactly perpendicular to the upper surface of substrate 100.For example, groove 123 is upper
Portion's width can be more than the lower width of groove 123.With insulating layer 112,114 and 119 and sacrificial layer 113,115 and 117
Total height get higher, the difference between the upper width and lower width of groove can become larger.
The maximum width " d2-2a " of groove 123 can be more than the interval " d1- between the uppermost sacrificial layer 117 of separation
2a".This is because the thickness that the self-reference substrate 100 of uppermost sacrificial layer 117 rises is than insulating layer 112,114 and 119 and sacrifice
The total height of layer 113,115 and 117 is thin.Specifically, as the thickness of layer to be etched thickens, the side wall for the layer being etched can
More to be tilted from the normal of the upper surface of substrate 100.In addition, when the layer formed by different types of material is etched, from
The degree of the normal slope of the upper surface of substrate can increase.
The substrate 100 exposed by groove 123 can be doped with dopant, and then common source region 102 can be formed
In substrate 100.Common source region 102 can utilize patterned insulating layer 112,114 and 119 and patterned sacrificial layer
113, it 115 and 117 is formed by ion implanting as mask.Common source region 102 can be formed in initiation layer stacked gate structure it
Between substrate 100 in.Common source region 102 it is a part of can by make common source region 102 dopant spread by with it is first
The stacking grid structure that begins is overlapping.
With reference to Fig. 2 C, the sacrificial layer 113,115 and 117 exposed by groove 123 is removed.Sacrificial layer 113,115 and 117
It can be removed by isotropic etching using etchant.For this purpose, empty space can be formed in insulating layer 112,114 and
Between 119.
Gate dielectric pattern 125 can be formed in groove 123 and empty space.Gate dielectric pattern 125 can be with thickness
It spends " a " and conformally covers the madial wall of groove 123 and the madial wall in the space of sky.Gate dielectric pattern 125 can also be formed
On the upper surface of active patterns 121 and the upper surface of upper insulating layer 119.Gate dielectric pattern 125 may include oxide skin(coating),
At least one of nitride layer and oxynitride layer.For example, gate dielectric pattern 125 can be by oxide skin(coating)-nitride
The multilayered structure that layer-oxynitride layer is constituted.
It can be formed as filling groove 123 and empty space with reference to Fig. 2 D, grid layer GL.Grid layer GL can include doping
Semi-conducting material and at least one of conductive material, which includes metal and metallic compound.
In order to make grid layer GL be fully filled groove 123 and empty space, groove 123, which can have, to be enough to fill grid
The width of layer GL.Therefore, in the case where forming the unit string detached by groove, due to the area of groove, realize that height collects
At device exist limitation.However, according to the embodiment of present inventive concept, the unit string of separation can be by selecting in separation
Gate pattern and formed.Therefore, the number of groove can be reduced.As a result, it is possible to achieve being conducive to highly integrated semiconductor devices.
With reference to Fig. 2 E, the upper surface of the upper surface of active patterns 121 and upper insulating layer 119 can be formed in by removal
Gate dielectric pattern 125 and grid layer GL on source pattern 121 and upper insulating layer 119 and be exposed.125 He of gate dielectric pattern
Grid layer GL can be removed by chemically mechanical polishing (CMP).
Gate pattern GSG, CG and SSG can be formed by etching the grid layer GL being formed in groove 123.In gate pattern
In GSG, CG and SSG, the gate pattern GSG near substrate 100 can be lower selection gate pattern, farthest away from the grid of substrate 100
Pattern SSG can be upper selection gate pattern.Pattern CG between lower selection gate pattern GSG and upper selection gate pattern SSG can be
Unit gate pattern CG.Gate pattern GSG, CG and SSG can be kept in the grid layer GL in empty space.It can be formed in covering
The mask of insulating layer 129 and active patterns, the grid layer GL being then formed in groove 123 can be by using the mask conduct
The anisotropic etching of etching mask is removed.After the anisotropic etch, grid layer GL can further be carried out it is each to
Isotropic etch.Isotropic etching can be for removing on the side wall for the insulating layer being retained between being formed in empty space
The technique of grid layer GL.By isotropic etching, gate pattern GSG, CG and the SSG being formed in empty space can be complete
Ground detaches.
Structural insulation pattern 124 can be formed in grid layer GL from the groove 123 that it is removed between grid.
With reference to Fig. 2 F, interlayer insulating film 131 can be formed on active patterns 121.It is exhausted that contact hole can be formed in interlayer
To expose dopant areas 122 in edge layer 131.This can be formed in and connect by being electrically connected to the bit line contact 133 of dopant areas 122
In contact hole.Bit line contact 133 can fill the contact hole.Conductive layer can be formed in interlayer insulating film 131 and bit line contact 133
On.Then, bit line 134 is formed by patterning the conductive layer.Bit line 134 can be extend in a second direction it is linear
Formula.Bit line 134 can be electrically connected to dopant areas 122 by bit line contact 133.
Describe to be formed the semiconductor of an embodiment according to present inventive concept now with reference to Fig. 1 and Fig. 3 A to Fig. 3 E
Another example of the method for device.The sectional view of Fig. 3 A to Fig. 3 E line I-I' interceptions shown in Fig. 1 that are the semiconductor devices.
In Fig. 3 A to Fig. 3 E, identical reference numeral can indicate component identical with the component in Fig. 2A to Fig. 2 F.Below, will
The method to form semiconductor devices is described based on the component and technique different from the component of Fig. 2A to Fig. 2 F and technique.
With reference to Fig. 3 A, insulating layer 112,114 and 119 and sacrificial layer 113,115 and 117 can be alternately formed at substrate
On 100.Different from the method for the formation semiconductor devices with reference to Fig. 2A descriptions, this embodiment of present inventive concept can not wrap
Include the technique carried out for detaching uppermost sacrificial layer 117.
With reference to Fig. 3 B, active patterns 121 are formed through insulating layer 112,114 and 119 and sacrificial layer 113,115 and
117.Dopant areas 122 can be formed in the topmost portion of active patterns 121.Then, initiation layer stacked gate structure can lead to
It crosses patterned insulation layer 112,114 and 119 and sacrificial layer 113,115 and 117 and is formed.Groove 123 is present in initial stacking
Between grid structure.Groove 123 can be the empty space extended in a first direction between initiation layer stacked gate structure.Common source
Polar region 102 can be formed in the substrate 100 between initiation layer stacked gate structure.
With reference to Fig. 3 C, sacrificial layer 113,115 and 117 can be removed.Gate dielectric pattern 125 and gate pattern GSG, CG
It can be formed in SSGa in the empty space provided by removing sacrificial layer 113,115 and 117.It is formed in uppermost sacrificial
Gate pattern (i.e. upper to select gate pattern SSGa) at domestic animal layer 117 can be present in single layer in single initiation layer stacked gate structure, no
It is same as Fig. 2 C.
It can be detached with reference to Fig. 3 D, upper selection gate pattern SSGa.Upper selection gate pattern SSGa can pass through anisotropy
Etching is detached.The pairs of upper gap 128 selected between gate pattern SSGa can be the slit shape that extends in a first direction
Formula.The side wall of upper selection gate pattern SSGa can tilt to be less than from substrate 100 side wall of initiation layer stacked gate structure.This is because
The thickness of upper selection gate pattern SSGa is thinner than the thickness of initiation layer stacked gate structure.As a result, for detaching selection gate pattern SSGa
Required space can be less than the space being used to form needed for initiation layer stacked gate structure.It is thereby achieved that in order to highly integrated
And optimised semiconductor devices.
It can be divided in the form of the line extended along a first direction with reference to Fig. 3 E, pairs of upper selection gate pattern SSGa
From.Upper isolated insulation pattern 118a be formed as being filled into upper selection gate pattern SSGa between gap 128.Upper isolated insulation
Pattern 118a can be contacted with the opposite side wall of pairs of upper selection gate pattern SSGa.
Bit line 134 and bit line contact 133 can be formed on active patterns 121.Active patterns 121 can be connect by bit line
It touches 133 and is connected to bit line 134.
Now with reference to Fig. 4 A and Fig. 4 B descriptions according to the formation semiconductor devices of another embodiment of present inventive concept
Method.
It is formed to be separated from each other with reference to Fig. 4 A, nethermost sacrificial layer 113a, is different from Fig. 2A.Sacrificial layer 113a can be with
It detaches in a second direction.As shown in Figure 4 A, insulating layer 112 and sacrificial layer 113a are formed on substrate, then sacrificial layer
113a can be anisotropically etched.Lower isolated insulation pattern 114a can be formed between the sacrificial layer 113a of separation.With
Afterwards, insulating layer 114 and sacrificial layer 115 and 117 can be alternately laminated on the sacrificial layer 113a of separation.Then, in Fig. 4 B
The semiconductor devices shown can be formed in a manner of similar to being described with reference to Fig. 2A to Fig. 2 F.
With reference to Fig. 5, by description according to the semiconductor devices of another embodiment of inventive concept.It is partly led shown in Fig. 5
Body device describes the different component of the component of semiconductor devices for focusing principally on from being described above by reference to Fig. 2 F.
With reference to Fig. 5, a stacking grid structure may include the illusory gate pattern DG being separated from each other.Illusory gate pattern DG can
To be arranged between uppermost unit gate pattern CG and upper selection gate pattern SSG.
For example, a stacking grid structure may include the illusory gate pattern DG of a pair extended in a first direction.Illusory grid
Pattern DG can be separated from each other in a second direction.
Upper isolated insulation pattern 118b can be plugged between selection gate pattern SSG and illusory gate pattern DG it
Between.Interval between upper selection gate pattern SSG can be identical as the interval between illusory gate pattern DG.For example, upper isolated insulation
The width of pattern 118b can be constant.Optionally, the interval between upper selection gate pattern SSG can be more than illusory gate pattern
Interval between DG.The width of upper isolated insulation pattern 118b can be gradually reduced towards substrate.Between upper selection gate pattern SSG
Interval d1 can be less than adjacent stacking grid structure between largest interval d2.
Upper selection gate pattern SSG may be coupled to selection line, and lower selection gate pattern GSG may be coupled to lower selection line,
Unit gate pattern CG may be coupled to wordline, and illusory gate pattern DG can be not connected to wordline.As it is used herein, term
" illusory " refers to such component, has with corresponding different components same or similar structure and shape, but
It is not have actual function in the semiconductor device and only pattern is used as to exist.Therefore, electric signal is not applied to " illusory "
Component, or " illusory " component do not execute electrical functions.
With reference to Fig. 6, by description according to the semiconductor devices of another embodiment.Semiconductor devices shown in Fig. 6 will be led
The component different from the component of semiconductor devices described above by reference to Fig. 2 F and Fig. 5 is focused on to describe.
It can be plugged between selection gate pattern SSG and in illusory grid figure with reference to Fig. 6, upper isolated insulation pattern 118c
Between case DG.Interval d1a between upper selection gate pattern SSG can be more than the interval d1b between illusory gate pattern DG.For example,
The upper area of upper isolated insulation pattern 118c can be more than lower region thereof.Interval d1a between upper selection gate pattern SSG can
With less than the largest interval d2 between adjacent stacking grid structure.
Fig. 7 is the sectional view according to the semiconductor devices of another embodiment of inventive concept.
With reference to Fig. 7, by description according to the semiconductor devices of another embodiment.Semiconductor devices shown in Fig. 7 will be led
The component different from the component of semiconductor devices described above by reference to Fig. 3 E is focused on to describe.
One stacking grid structure may include the illusory gate pattern DG being separated from each other.Illusory gate pattern DG can be arranged
Between uppermost unit gate pattern CG and upper selection gate pattern SSG.Illusory gate pattern DG can be not connected to wordline.
Upper isolated insulation pattern 118d can be plugged between selection gate pattern SSG and illusory gate pattern DG it
Between.The width of upper isolated insulation pattern 118d can be gradually reduced towards substrate 100.Interval between upper selection gate pattern SSG
The interval between illusory gate pattern DG can be more than.The normal of the upper surface of substrate 100 in the contact of upper selection gate pattern SSG
Angle between the side wall of isolated insulation pattern 118d can be more than 0 °.The normal of the upper surface of substrate 100 and illusory gate pattern
Angle in the contact of DG between the side wall of isolated insulation pattern 118d can be more than 0 °.
With reference to Fig. 8, by description according to the semiconductor devices of another embodiment of inventive concept.It is partly led shown in Fig. 8
Body device describes the different component of the component of semiconductor devices for focusing principally on from being described above with respect to Fig. 4 B.
With reference to Fig. 8, a stacking grid structure may include the illusory gate pattern DG being separated from each other.Illusory gate pattern DG can
To be arranged between uppermost unit gate pattern CG and upper selection gate pattern SSG.
For example, one of stacking grid structure may include the illusory gate pattern DG of a pair extended in a first direction.Illusory grid
Pattern DG can be separated from each other in a second direction.Illusory gate pattern DG can be not connected to wordline.
Upper isolated insulation pattern 118b can be plugged between selection gate pattern SSG and illusory gate pattern DG it
Between.Interval between upper selection gate pattern SSG can be equal to the interval between illusory gate pattern DG.For example, upper isolated insulation figure
The width of case 118b can be constant.Interval between upper selection gate pattern SSG can be less than adjacent stacking grid structure it
Between largest interval.
With reference to Fig. 9 to Figure 11, by description according to the semiconductor devices of another embodiment of inventive concept.Fig. 9 is to show
According to the plan view of the cellular zone of the semiconductor devices of the embodiment of inventive concept.Figure 10 is the semiconductor devices along Fig. 9
The sectional view of line I-I' interceptions, Figure 11 are the sectional views of line II-II' interception of the semiconductor devices along Fig. 9.
With reference to Fig. 9 to Figure 11, semiconductor devices may include substrate 200, and substrate 200 includes wherein to form storage unit
Cell array region CA and connection storage unit to connect up bonding pad CE.Cell array region CA and bonding pad CE can form list
First area.Fig. 9 shows a part of cell array region CA.Although Fig. 9 shows that bonding pad CE is shown as being arranged in cell array region
The side of CA, but bonding pad CE can also be provided in the both sides of cell array region CA.
Stacking grid structure can be arranged on the cell array region CA and bonding pad CE of substrate 200.Each stacking grid structure
May include upper selection gate pattern SSG, illusory gate pattern DG, unit gate pattern CG, lower selection gate pattern GSG, upper insulating pattern
219, insulating pattern 214 and bottom insulating pattern 212 between grid.Interlayer insulating film 250 can be arranged in stacking grid structure.
Insulating pattern 214 can be alternately laminated on substrate 200 between unit gate pattern CG and grid.Grid electrode insulation figure
Case 214 can be arranged between unit gate pattern CG, between uppermost unit gate pattern CG and illusory gate pattern DG, in void
If between gate pattern DG and upper selection gate pattern SSG and nethermost unit gate pattern CG and lower selection gate pattern GSG it
Between.Lower selection gate pattern GSG can be plugged between substrate 200 and nethermost unit gate pattern CG.Bottom insulating pattern 212 can
To be plugged between lower selection gate pattern GSG and substrate 200.Upper selection gate pattern SSG can be arranged on illusory gate pattern DG,
Upper insulating pattern 219 can be arranged on upper selection gate pattern SSG.
For example, stacking grid structure can extend in (such as X-direction) in a first direction, and may include being formed in connection
Step structure in area CE.Step structure can by selection gate pattern SSG on extending in different lengths in a first direction,
Illusory gate pattern DG, unit gate pattern CG and lower selection gate pattern GSG and formed.The step layer of step structure can wherein be set
Set the pad zone of contact plunger CP.
Stacking grid structure can be separated from each other in second direction (such as Y direction) by common source polar curve 280.Absolutely
Edge layer 282 can be arranged between stacking grid structure and common source polar curve 280.Second direction can be intersected with first direction
Direction.
Common source polar curve 280 can in a first direction extend in cell array region CA and bonding pad CE.Public source
Line 280 can be arranged on the common source region of substrate 200 202 and may be electrically connected to common source region 202.Common source polar curve
280 can be formed from conductive materials.For example, common source polar curve 280 may include tungsten (W).Insulating layer 282 can be by insulating materials
It is formed.For example, insulating layer 282 may include Si oxide (SiO2), silicon nitride (Si3N4), silicon nitrogen oxides (SiON) or its
Combination.
One stacking grid structure may include gate pattern SSG and the illusory grid of a pair being separated from each other in a pair being separated from each other
Pattern DG.Pairs of upper selection gate pattern SSG can be separated from each other in a second direction.Pairs of illusory gate pattern DG can be with
It is separated from each other in a second direction.Upper isolated insulation pattern 218 can be plugged between selection gate pattern SSG and in void
If between gate pattern DG.Interval between upper selection gate pattern SSG can be equal to the interval between illusory gate pattern DG.For example,
The width of upper isolated insulation pattern 218 can be constant.Interval d3 between upper selection gate pattern SSG can be less than adjacent
The interval d4 between grid structure is laminated.In one embodiment, the width of upper isolated insulation pattern 218 can be towards substrate
200 reduce.
In this example, in a manner of similar to Fig. 8, a stacking grid structure may include the lower selection grid being separated from each other
Pattern GSG, lower isolated insulation pattern can be plugged between lower selection gate pattern GSG.
In the CA of cell array region, across multiple vertical furrows of stacking grid structure on third direction (such as Z-direction)
Road structure C H can be arranged as multirow in a first direction.Multiple vertical channel structure CH can be arranged in a manner of zigzag.?
Third party, which is upward through stacking grid structure and the illusory channel structure DCH of upper isolated insulation pattern 218, can be arranged in unit battle array
It arranges in area CA.In addition, illusory channel structure DCH may be arranged to the end of the step layer of the step structure in neighbouring bonding pad CE
End.Illusory channel structure DCH can be arranged as multirow in a first direction in the CE of bonding pad.Illusory channel structure DCH can
To be not connected to bit line.
Vertical channel structure CH and illusory channel structure DCH can be with structures having the same.Each vertical channel structure CH
May include active patterns 221, drain region 222, gate dielectric pattern 225 and filling insulation with each illusory channel structure DCH
Pattern 227.Active patterns 221 can have hollow pipe shape and can be formed by semi-conducting material.The inside of active patterns 221
Space can be filled by filling insulating pattern 227.Gate dielectric pattern 225 can extend along the outer surface of active patterns 221.
Gate dielectric pattern 225 may include selected from oxide skin(coating), nitride layer and oxynitride layer it is at least one.For example,
Gate dielectric pattern 225 may include the multilayer film being made of oxidation film-nitride film-oxidation film.Drain region 222 can be with
It is formed by the semi-conducting material adulterated.
Semiconductor pattern 230 can be correspondingly arranged in below vertical channel structure CH.In addition, semiconductor pattern
230 can be arranged correspondingly below illusory channel structure DCH.Semiconductor pattern 230 can be by giving birth to from 200 extension of substrate
Long single-crystal semiconductor material is formed.Semiconductor pattern 230 can be arranged between active patterns 221 and substrate 200 will have
Source pattern 221 and substrate 200 are electrically connected to each other.Semiconductor pattern 230 can be formed by material identical with active patterns 221.
Lower selection gate dielectric pattern 235 can be arranged between semiconductor pattern 230 and lower selection gate pattern GSG.Lower selection grid electricity
Dielectric pattern 235 can be formed by aoxidizing the part of semiconductor pattern 230.
Referring to Fig.1 2, it will describe according to another exemplary semiconductor devices.Semiconductor devices shown in Figure 12 will be main
The component different from the component of semiconductor devices described above by reference to Figure 11 is focused on to describe.
Referring to Fig.1 2, upper isolated insulation pattern 218a can be plugged between selection gate pattern SSG and in illusory grid
Between pattern DG.Interval d3a between upper selection gate pattern SSG can be more than the interval d3b between illusory gate pattern DG.Example
Such as, upper isolated insulation pattern 218a can have upper area, the upper area to have than under upper isolated insulation pattern 218a
The big width of the width in portion region.In this example, the width of the upper area of upper isolated insulation pattern 218a and its underpart area
The width in domain can reduce towards substrate 200.In addition, the interval d3a between upper selection gate pattern SSG can be less than adjacent layer
Interval d4 between stacked gate structure.
It will describe according to another exemplary semiconductor devices.Figure 13 is the cellular zone according to another exemplary semiconductor devices
Plan view.The sectional view of Figure 14 line II-II' interceptions shown in Figure 13 that are the semiconductor devices.
Semiconductor devices shown in Figure 13 and Figure 14 will focus principally on and half above by reference to Figure 11 and Figure 12 descriptions
The component of conductor device different component describes.
In a manner of different from Figure 12, a stacking grid structure may include selection gate pattern SSG1 in a pair first, set
Set selected in a pair second selected on first on gate pattern SSG1 gate pattern SSG2, the first illusory gate pattern DG1 of a pair, with
And the second illusory gate pattern DG2 of a pair being arranged on the first illusory gate pattern DG1.Select gate pattern SSG1 can be on first
It is separated from each other in second direction.Select gate pattern SSG2 that can be separated from each other in a second direction on second.First is illusory
Gate pattern DG1 can be separated from each other in a second direction.Second illusory gate pattern DG2 can be spaced in a second direction
It opens.
Upper isolated insulation pattern 218' can be plugged on first select gate pattern SSG1 between, the selection grid figure on second
Between case SSG2, between the first illusory gate pattern DG1 and between the second illusory gate pattern DG2.Selection grid figure on first
Interval d3a between case SSG1 can be more than the interval d3b between the first illusory gate pattern DG1.For example, upper isolated insulation pattern
218' can have a upper area, which has big wide of the width of lower area than upper isolated insulation pattern 218'
Degree.In this example, the width of the upper area of upper isolated insulation pattern 218' and the width of lower region thereof can be towards bases
Plate 200 reduces.Select the interval d3a between gate pattern SSG2 that can be less than the interval between adjacent stacking grid structure on second
d4。
In this example, in a manner of similar to Figure 11, selection grid figure between selection gate pattern SSG1 and on second on first
Interval d3a between case SSG2 can be equal to the interval between the first illusory gate pattern DG1 between the second illusory gate pattern DG2
d3b。
In this example, in a manner of similar to Fig. 8, a stacking grid structure may include the lower selection grid being separated from each other
Pattern GSG, lower isolated insulation pattern can be plugged between lower selection gate pattern GSG.
It may be implemented in a plurality of types of semiconductor packages according to the semiconductor devices of the above embodiment.For example, root
It can be encapsulated in such a way according to the semiconductor storage unit of the embodiment of inventive concept：Laminate packaging (PoP), ball bar battle array
Arrange (BGA), wafer-level package (CSP), the plastic chip carrier (PLCC) with lead, plastics dual-inline package (PDIP),
Waffle die package, wafer type tube core, chip on board (COB), ceramic double-row straight cutting encapsulation (CERDIP), the flat envelope of plastic quad
Fill (MQFP), thin quad flat package (TQFP), small outline integrated circuit encapsulation (SOIC), the small outline packages of thin space
(SSOP), small thin outline package (TSOP), system in package (SIP), multi-chip package (MCP), wafer scale manufacture encapsulation (WFP)
Or wafer-level process stacked package (WSP).The envelope of the semiconductor storage unit of embodiment according to inventive concept is installed
Dress can also include the controller and/or logical device for controlling the semiconductor storage unit.
Figure 15 is to show to include the block diagram according to the electronic system of the semiconductor devices of the embodiment of inventive concept.
Referring to Fig.1 5, the electronic system 1100 according to the embodiment of inventive concept may include controller 1110, input/
Output device (I/O) 1120, memory device 1130, interface 1140 and bus 1150.Controller 1110, input/output device (I/
O) 1120, memory device 1130 and/or interface 1140 can be connected to each other by bus 1150.Bus 1150 corresponds to data
Transmission path.
Controller 1110 includes microprocessor, digital signal processor, microcontroller and executes similar function
At least one of logical device.Input/output device (I/O) 1120 may include keypad, keyboard or display device.It deposits
Memory device 1130 can store data and/or order etc..Memory device 1130 may include the above embodiment of inventive concept
Disclosed at least one of semiconductor storage unit.Memory device 1130 can also include that the semiconductor of other type is deposited
Memory device (such as flash memory, DRAM device and/or SRAM device).The execution of interface 1140 sends data to communication network
Or the function of data is received from communication network.Interface 1140 can be realized in the form of wirelessly or non-wirelessly.For example, interface 1140
May include antenna or Wireless/wired transceiver.Electronic system 1100 can also include that high-speed DRAM and/or high-speed SRAM are made
It is used to improve the operation of controller 1110 for run memory.
Electronic system 1100 can be applied to personal digital assistant (PDA), portable computer, web-tablet, radio telephone,
Mobile phone, digital music player, storage card or any electronics that can send and/or receive in wireless environments information
Device.
Figure 16 is to show to include the block diagram according to the storage card of the semiconductor devices of an embodiment of inventive concept.
Referring to Fig.1 6, include memory device 1210 according to the storage card 1200 of inventive concept embodiment.Storage
Device 1210 may include at least one of semiconductor storage unit disclosed in the above embodiment of present inventive concept.It deposits
Memory device 1210 can also include other type semiconductor storage unit (such as flash memory, DRAM device and/or
SRAM device).Storage card 1200 may include the memory control for controlling the data exchange between host and memory device 1210
Device 1220.
Memory Controller 1220 may include the processing unit 1222 for generally controlling storage card.Memory Controller
1220 may include the SRAM 1221 of the run memory as processing unit 1222.Memory Controller 1220 can also wrap
Include host interface 1223 and memory interface 1225.Host interface 1223 can have between storage card 1200 and host
Exchange the agreement of data.Memory Controller 1220 can be connected to memory device 1210 by memory interface 1225.Memory
Controller 1220 can also include that error correction encodes (ECC) block 1224.Error correction encoding block 1224 can be detected and be corrected
The mistake of the data read from memory device 1210.It is used for although it is not shown, storage card 1200 can also include storage
The ROM device of the code data interacted with host.Storage card 1200 may be used as portable data storage card.Optionally, it stores
Card 1200 can be implemented as solid-state disk (SSD), substitute the hard disk drive of computer system.
According to the embodiment of inventive concept, it is laminated in grid structure at one, in the first direction and a second direction each other
Adjacent active patterns can be with sharing unit gate pattern.Thus, it is possible to obtain the semiconductor devices optimized in order to highly integrated.
Above-mentioned theme will be considered illustrative rather than restrictive, and claims are intended to cover fall into invention structure
All modifications, enhancing and other embodiment in the true spirit and range of think of, the true spirit of inventive concept and range by
The most wide permissible explanation of claims and its equivalent determines, without should be constrained or limited by above detailed description
System.
Claims (16)
1. a kind of semiconductor devices, including：
Grid structure is laminated, including upper selection gate pattern, illusory gate pattern and the list for being layered on substrate and extending in a first direction
First gate pattern；
Active patterns are separated from each other while across the stacking grid structure；And
Gate dielectric pattern, be plugged between the unit gate pattern and the active patterns, the upper selection gate pattern with
Between the active patterns and between the illusory gate pattern and the active patterns,
The wherein described upper selection gate pattern is arranged on the uppermost unit gate pattern in the unit gate pattern and is handing over
It pitches and is separated from each other in the second direction of the first direction, the illusory gate pattern is arranged in the uppermost unit grid figure
It is separated from each other between case and the upper selection gate pattern and in this second direction.
2. semiconductor devices as described in claim 1, wherein the interval between the upper selection gate pattern and the illusory grid
Interval between pattern is identical.
3. semiconductor devices as described in claim 1, wherein the interval between the upper selection gate pattern is more than described illusory
Interval between gate pattern.
4. semiconductor devices as claimed in claim 3, wherein interval between the upper selection gate pattern is towards the substrate
Reduce, and the interval between the illusory gate pattern reduces towards the substrate.
5. semiconductor devices as described in claim 1, wherein the upper selection gate pattern include on first selection gate pattern and
Gate pattern is selected on second be arranged on described first on selection gate pattern, and the illusory gate pattern includes first illusory
Gate pattern and the second illusory gate pattern being arranged on the described first illusory gate pattern.
6. semiconductor devices as described in claim 1, wherein the stacking grid structure further includes in nethermost unit grid figure
The lower selection gate pattern extended in said first direction between case and the substrate, and
The lower selection gate pattern is set as being separated from each other in this second direction.
7. semiconductor devices as described in claim 1, further include on the substrate in this second direction with it is described
Grid structure another stacking grid structure spaced apart is laminated,
Interval between the wherein described upper selection gate pattern is less than between the stacking grid structure and another stacking grid structure
Interval.
8. semiconductor devices as claimed in claim 7 further includes in the stacking grid structure and another stacking grid structure
Between the substrate in common source region.
9. semiconductor devices as claimed in claim 8 further includes being arranged in the stacking grid structure and another stacking grid
The common source polar curve on the common source region between structure.
10. semiconductor devices as described in claim 1, wherein the gate dielectric pattern extends to the unit gate pattern
In upper and lower surface.
11. semiconductor devices as described in claim 1, wherein periphery of the gate dielectric pattern along the active patterns
Side surface extends.
12. semiconductor devices as described in claim 1 further includes being arranged between each active patterns and the substrate
Semiconductor pattern.
13. semiconductor devices as described in claim 1, wherein the gate dielectric pattern includes oxidation film-nitride film-
Oxidation film.
14. a kind of semiconductor devices, including：
Grid structure is laminated, including upper selection gate pattern, illusory gate pattern and the list for being layered on substrate and extending in a first direction
First gate pattern；With
Vertical structure is separated from each other while across the stacking grid structure,
The wherein described upper selection gate pattern is arranged on the uppermost unit gate pattern in the unit gate pattern and is handing over
It pitches and is separated from each other in the second direction of the first direction, the illusory gate pattern is arranged in the uppermost unit grid figure
It is separated from each other between case and the upper selection gate pattern and in this second direction.
15. semiconductor devices as claimed in claim 14, wherein the interval between the upper selection gate pattern is equal to the void
If the interval between gate pattern.
16. semiconductor devices as claimed in claim 14, wherein the interval between the upper selection gate pattern is more than the void
If the interval between gate pattern.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110012189A1 (en) * | 2009-07-20 | 2011-01-20 | Samsung Electronics Co., Ltd. | Semiconductor device and method of forming the same |
| US20120098048A1 (en) * | 2010-10-21 | 2012-04-26 | Samsung Electronics Co., Ltd. | Vertical memory devices and methods of manufacturing the same |
| CN105244351A (en) * | 2014-07-01 | 2016-01-13 | 三星电子株式会社 | Semiconductor device and method of manufacturing the semiconductor device |
| US20160163686A1 (en) * | 2014-12-08 | 2016-06-09 | Jaehan Lee | Semiconductor devices having dummy patterns and methods of fabricating the same |
| CN105789215A (en) * | 2015-01-14 | 2016-07-20 | 三星电子株式会社 | Vertical memory devices and methods of manufacturing the same |
| US20170092657A1 (en) * | 2015-03-10 | 2017-03-30 | Jung-Hwan Lee | Semiconductor devices including gate insulation layers on channel materials and methods of forming the same |
-
2017
- 2017-04-14 CN CN201710243320.3A patent/CN108735740A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110012189A1 (en) * | 2009-07-20 | 2011-01-20 | Samsung Electronics Co., Ltd. | Semiconductor device and method of forming the same |
| US20120098048A1 (en) * | 2010-10-21 | 2012-04-26 | Samsung Electronics Co., Ltd. | Vertical memory devices and methods of manufacturing the same |
| CN105244351A (en) * | 2014-07-01 | 2016-01-13 | 三星电子株式会社 | Semiconductor device and method of manufacturing the semiconductor device |
| US20160163686A1 (en) * | 2014-12-08 | 2016-06-09 | Jaehan Lee | Semiconductor devices having dummy patterns and methods of fabricating the same |
| CN105789215A (en) * | 2015-01-14 | 2016-07-20 | 三星电子株式会社 | Vertical memory devices and methods of manufacturing the same |
| US20170092657A1 (en) * | 2015-03-10 | 2017-03-30 | Jung-Hwan Lee | Semiconductor devices including gate insulation layers on channel materials and methods of forming the same |
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