CN108735173B - Gamma voltage generating device and liquid crystal display device - Google Patents

Gamma voltage generating device and liquid crystal display device Download PDF

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Publication number
CN108735173B
CN108735173B CN201810514835.7A CN201810514835A CN108735173B CN 108735173 B CN108735173 B CN 108735173B CN 201810514835 A CN201810514835 A CN 201810514835A CN 108735173 B CN108735173 B CN 108735173B
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terminal
switching element
input
voltage
logic unit
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CN108735173A (en
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魏玉娜
朱梅芬
陈万兴
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InfoVision Optoelectronics Kunshan Co Ltd
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InfoVision Optoelectronics Kunshan Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
    • G09G2320/0276—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0673—Adjustment of display parameters for control of gamma adjustment, e.g. selecting another gamma curve

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

The invention provides a gamma voltage generating device, which comprises a first group of voltage generating circuits, a second group of voltage generating circuits, a control circuit and a selection circuit. The first generating circuit is used for providing a first group of gamma voltages. The second group of voltage generating circuits is used for providing a second group of gamma voltages. The control circuit acquires a display mode of a picture to be displayed and generates a corresponding control signal according to the mode. The selection circuit is used for receiving the first group of gamma voltages and the second group of gamma voltages and outputting the first group of gamma voltages or the second group of gamma voltages to the source electrode driving circuit according to the positive sequence or the negative sequence of the control signal. The invention also provides a liquid crystal display device. The gamma voltage generating device and the liquid crystal display device can output a corresponding group of gamma voltages in a plurality of groups of gamma voltages in a positive sequence or a negative sequence according to the corresponding control signals generated by the display mode, and provide the gamma voltages to the source electrode driving circuit, thereby providing convenience for circuit layout and saving the occupied space of the layout.

Description

Gamma voltage generating device and liquid crystal display device
Technical Field
The present invention relates to the field of liquid crystal display, and more particularly, to a gamma voltage generating device and a liquid crystal display device.
Background
Liquid Crystal Display (LCD) devices have the advantages of good picture quality, small size, light weight, low driving voltage, low power consumption, no radiation, relatively low manufacturing cost, and the like, and currently dominate the flat panel Display field. It is widely used in a variety of office automation and audio-visual devices such as desktop computers, palm top computers, Personal Digital Assistants (PDAs), cellular phones, tv boxes, and the like.
At present, the demand for the picture quality of the lcd devices is increasing, and the lcd devices often need to operate in different display modes, such as wide viewing angle, narrow viewing angle, etc., and require different sets of gamma voltages in different display modes. However, when the conventional source driving circuit calls the internal gamma voltage in the switching display mode, the display quality of the liquid crystal display device may be affected by the abnormal picture, for example, the split screen of the picture.
Disclosure of Invention
In view of the above, the present invention is directed to a gamma voltage generating device, which can solve the problem of abnormal pictures when a source driving circuit calls an internal gamma voltage in a switching display mode.
Specifically, the invention provides a gamma voltage generating device which comprises a first group of voltage generating circuits, a second group of voltage generating circuits, a control circuit and a selection circuit. The first group of voltage generation circuits are used for providing a first group of gamma voltages and comprise n voltage output ends, wherein n is a positive integer. The second group of voltage generating circuits is used for providing a second group of gamma voltages and comprises n voltage output ends. The control circuit acquires a display mode of a picture to be displayed and generates a corresponding control signal according to the display mode, wherein the control signal comprises a first control signal and a second control signal. The selection circuit comprises n voltage output ends, and is used for receiving the first group of gamma voltages and the second group of gamma voltages and outputting the first group of gamma voltages or the second group of gamma voltages to the source electrode driving circuit in a positive sequence or a negative sequence at the n voltage output ends of the selection circuit according to the control signal.
Preferably, the selection circuit includes n sub-selection circuits, the sub-selection circuit includes a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, a first selection terminal, a second selection terminal and an output terminal, the first input terminal of the mth sub-selection circuit is connected to the mth voltage output terminal of the first group of voltage generation circuits, the second input terminal of the mth sub-selection circuit is connected to the n-m +1 voltage output terminal of the first group of voltage generation circuits, the third input terminal of the mth sub-selection circuit is connected to the mth voltage output terminal of the second group of voltage generation circuits, the fourth input terminal of the mth sub-selection circuit is connected to the n-m +1 voltage output terminal of the second group of voltage generation circuits, the first selection terminal of the mth sub-selection circuit receives the first control signal, the second selection terminal of the mth sub-selection circuit receives the second control signal, and the output terminal of the mth sub-selection circuit selects the voltage on one of the first input terminal to the fourth input terminal of the mth sub-selection circuit to output according to the first control signal and the second control signal; wherein m is less than or equal to n, and m is a positive integer.
Preferably, the mth sub-selection circuit includes a first switching element, a second switching element, a third switching element, a fourth switching element, a first logic unit, a second logic unit, a third logic unit, a fourth logic unit, a fifth switching element, a sixth switching element, a seventh switching element, and an eighth switching element. The first logic unit comprises a first input end, a second input end and an output end, the first input end of the first logic unit is connected with the first control end of the mth sub-selection circuit through a first resistor, and the second input end of the first logic unit is connected with the second control end of the mth sub-selection circuit through a second resistor. The first switch element comprises a first control end, a first path end and a second path end, the first control end of the first switch element is connected with the output end of the first logic unit, the first path end of the first switch element is connected with the first power supply through a third resistor, and the second path end of the first switch element is grounded. The second switch element comprises a second control end, a third path end and a fourth path end, the second control end of the second switch element is connected with the first path end of the first switch element, the third path end of the second switch element is connected with the first input end of the mth sub-selection circuit, and the fourth path end of the first switch element is connected with the output end of the mth sub-selection circuit. The second logic unit comprises a first input end, a second input end and an output end, the first input end of the second logic unit is connected with the first input end of the first logic unit, and the second input end of the second logic unit is connected with the second input end of the first logic unit. The third switch element comprises a third control end, a fifth path end and a sixth path end, the third control end of the third switch element is connected with the output end of the first logic unit, the fifth path end of the third switch element is connected with the second power supply through a fourth resistor, and the sixth path end of the third switch element is grounded. The fourth switch element comprises a fourth control end, a seventh path end and an eighth path end, the fourth control end of the fourth switch element is connected with the fifth path end of the third switch element, the seventh path end of the fourth switch element is connected with the third input end of the mth sub-selection circuit, and the eighth path end of the fourth switch element is connected with the fourth path end of the second switch element. The third logic unit comprises a first input end, a second input end and an output end, the first input end of the third logic unit is connected with the first input end of the first logic unit, and the second input end of the third logic unit is connected with the second input end of the first logic unit. The fourth logic unit comprises a first input end, a second input end and an output end, the first input end of the fourth logic unit is connected with the first path end of the first switch element, and the second input end of the fourth logic unit is connected with the output end of the third logic unit. The fifth logic unit comprises a first input end, a second input end and an output end, the first input end of the fifth logic unit is connected with the fourth control end of the fourth switching element, and the second input end of the fifth logic unit is connected with the output end of the third logic unit. The fifth switching element comprises a fifth control end, a ninth path end and a tenth path end, the fifth control end of the fifth switching element is connected with the output end of the fourth logic unit through a fifth resistor, the ninth path end of the fifth switching element is connected with a third power supply through a sixth resistor, and the tenth path end of the fifth switching element is grounded. The sixth switching element comprises a sixth control end, an eleventh path end and a tenth path end, the sixth control end of the sixth switching element is connected with the ninth path end of the fifth switching element, the eleventh path end of the sixth switching element is connected with the second input end of the mth sub-selection circuit, and the tenth path end of the sixth switching element is connected with the fourth path end of the second switching element. The seventh switching element comprises a seventh control end, a tenth path end and a tenth path end, the seventh control end of the seventh switching element is connected with the output end of the fifth logic unit through a seventh resistor, the thirteenth path end of the seventh switching element is connected with the fourth power supply through an eighth resistor, and the tenth path end of the seventh switching element is grounded. The eighth switching element comprises an eighth control end, a fifteenth end and a sixteenth end, the eighth control end of the eighth switching element is connected with the tenth end of the seventh switching element, the fifteenth end of the eighth switching element is connected with the fourth input end of the mth sub-selection circuit, and the sixteenth end of the eighth switching element is connected with the fourth end of the second switching element.
Preferably, the first switching element, the third switching element, the fifth switching element and the seventh switching element are NPN-type triodes, and the second switching element, the fourth switching element, the sixth switching element and the eighth switching element are P-channel junction field effect transistors.
Preferably, when the first input terminal and the second input terminal of the first logic unit receive high level signals at the same time, the output terminal of the first logic unit outputs high level signals, and when the first input terminal and the second input terminal of the first logic unit do not receive high level signals at the same time, the output terminal of the first logic unit outputs low level signals. When the first input end of the second logic unit receives a low level signal and the second input end receives a high level signal at the same time, the output end of the second logic unit outputs a high level signal, and when the first input end of the second logic unit does not receive the low level signal or the second input end does not receive the high level signal, the output end of the second logic unit outputs the low level signal. When the first input end and the second input end of the third logic unit receive high level signals or low level signals at the same time, the output end of the third logic unit outputs high level signals, and when the first input end and the second input end of the third logic unit do not receive high level signals or receive low level signals at the same time, the output end of the third logic unit outputs low level signals. When the first input end and the second input end of the fourth logic unit receive high level signals or receive low level signals at the same time, the output end of the fourth logic unit outputs high level signals, and when the first input end and the second input end of the fourth logic unit do not receive high level signals or receive low level signals at the same time, the output end of the fourth logic unit outputs low level signals. When the first input end and the second input end of the fifth logic unit receive high level signals or receive low level signals at the same time, the output end of the fifth logic unit outputs low level signals, and when the first input end and the second input end of the fifth logic unit do not receive high level signals or receive low level signals at the same time, the output end of the fifth logic unit outputs high level signals.
Preferably, the first group of voltage generation circuits includes a first resistor string, the first resistor string includes n +1 first voltage-dividing resistors, a first end of the first resistor string receives the first dc voltage, a second end of the first resistor string is grounded, and a common end of every two first voltage-dividing resistors is connected to n voltage output ends of the first group of voltage generation circuits.
Preferably, the second group of voltage generating circuits includes a second resistor string, the second resistor string includes n +1 second voltage dividing resistors, a first end of the second resistor string receives the second dc voltage, a second end of the second resistor string is grounded, and a common end of every two second voltage dividing resistors is connected to n voltage output ends of the second group of voltage generating circuits.
Preferably, the control signal comprises a third control signal, the second group of voltage generating circuits comprises a programmable gamma voltage buffer circuit, the programmable gamma voltage buffer circuit comprises n voltage output terminals which are the n voltage output terminals of the second group of voltage generating circuits, and the programmable gamma voltage buffer circuit is used for buffering at least one group of gamma voltages and outputting a corresponding group of gamma voltages in the at least one group of gamma voltages according to the third control signal.
The invention also provides a liquid crystal display device which comprises the gamma voltage generating device.
Preferably, when the liquid crystal display device is in the wide viewing angle display mode, if the first control signal is at a high level and the second control signal is at a high level, the gamma voltage generating device outputs the first set of gamma voltages in a positive sequence, or if the first control signal is at a low level and the second control signal is at a low level, the gamma voltage generating device outputs the first set of gamma voltages in a negative sequence;
when the liquid crystal display device is in a narrow viewing angle display mode, if the first control signal is at a low level and the second control signal is at a high level, the gamma voltage generation device outputs the second group of gamma voltages in a positive sequence, or if the first control signal is at a high level and the second control signal is at a low level, the gamma voltage generation device outputs the second group of gamma voltages in a negative sequence.
The gamma voltage generating device and the liquid crystal display device can output a corresponding group of gamma voltages in a plurality of groups of gamma voltages in a positive sequence or a negative sequence according to the corresponding control signals generated by the display mode, and provide the gamma voltages to the source electrode driving circuit, thereby providing convenience for circuit layout and saving the occupied space of the layout.
In order to make the aforementioned and other objects, features and advantages of the invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a circuit connection diagram of a gamma voltage generating device according to a first embodiment.
Fig. 2 is a circuit connection diagram of a sub-selection circuit provided in the first embodiment.
FIG. 3 is a circuit diagram of a gamma voltage generating device according to a second embodiment.
Fig. 4 is a circuit connection diagram of a gamma voltage generating device according to a third embodiment.
Detailed Description
To further illustrate the technical means and effects of the present invention for achieving the intended purpose, the following detailed description will be given of specific embodiments, methods, steps, structures, features and effects of the gamma voltage generating device and the liquid crystal display device according to the present invention with reference to the accompanying drawings and preferred embodiments.
The foregoing and other aspects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments, as illustrated in the accompanying drawings. While the invention has been described in connection with specific embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the invention.
First embodiment
Fig. 1 is a circuit connection diagram of a gamma voltage generating device according to a first embodiment. Referring to fig. 1, the gamma voltage generating apparatus of the first embodiment includes a first group of voltage generating circuits 100, a second group of voltage generating circuits 200, a control circuit 300 and a selection circuit 400. The first group of voltage generating circuits 100 is used for providing a first group of gamma voltages, and the first group of voltage generating circuits 100 includes n voltage output terminals (101, 102.. 10n in the figure), where n is a positive integer. The second group voltage generating circuit 200 is used for providing a second group gamma voltage, and the second group voltage generating circuit 200 includes n voltage output terminals (201, 202.. 20n in the figure). The control circuit 300 obtains a display mode of a picture to be displayed and generates a corresponding control signal according to the display mode, wherein the control signal comprises a first control signal and a second control signal. The selection circuit 400 includes n voltage output terminals (401, 402.. 40n in the figure), and the selection circuit 400 is configured to receive the first and second sets of gamma voltages and output the first and second sets of gamma voltages to the source driving circuit 500 in a positive or negative sequence at the n voltage output terminals according to the control signal.
Specifically, the first group of voltage generating circuits 100 is connected to the selection circuit 400 for providing the first group of gamma voltages to the selection circuit 400, and specifically, n gamma voltages are output to the selection circuit 400 through n voltage output terminals of the first group of voltage generating circuits 100, for example, the 1 st voltage output terminal 101 of the first group of voltage generating circuits 100 outputs the gamma voltage V1A, the 2 nd voltage output terminal 102 outputs the gamma voltage V2A, and sequentially, the n th voltage output terminal 10n outputs the gamma voltage VnA. The second group of voltage generating circuits 200 is connected to the selecting circuit 400, and is configured to provide the second group of gamma voltages to the selecting circuit 400, specifically, n gamma voltages are output to the selecting circuit 400 through n voltage output terminals of the second group of voltage generating circuits 200, for example, the 1 st voltage output terminal 201 of the second group of voltage generating circuits 200 outputs the gamma voltage V1B, the 2 nd voltage output terminal 202 outputs the gamma voltage V2B, and the n th voltage output terminal 20n outputs the gamma voltage VnB sequentially. Accordingly, the selection circuit 400 may receive n gamma voltages of the first group of gamma voltages and n gamma voltages of the second group of gamma voltages. The selection circuit 400 is connected to the control circuit 300, and receives the display mode of the picture to be displayed acquired by the control circuit 300 and generates a corresponding control signal according to the display mode, wherein the control signal comprises a first control signal and a second control signal.
The selection circuit 400 may output the first group of gamma voltages or the second group of gamma voltages to the source driving circuit 500 in a positive sequence or a negative sequence at the n voltage output terminals of the selection circuit 400 according to the control signal. Specifically, the selection circuit 400 may, but is not limited to, output the first group of gamma voltages in a positive sequence when the first control signal received the control signal is high and the second control signal of the control signal is high, that is, the 1 st voltage output terminal 401 of the selection circuit 400 outputs the gamma voltage V1A of the first group of gamma voltages, the 2 nd voltage output terminal 402 outputs the gamma voltage V2A of the first group of gamma voltages, and the n-th voltage output terminal 40n outputs the gamma voltage VnA of the first group of gamma voltages in a sequential sequence. The selection circuit 400 can, but is not limited to, output the first set of gamma voltages in a reverse order when the first control signal of the received control signal is low and the second control signal of the control signal is low, that is, the 1 st voltage output terminal 401 of the selection circuit 400 outputs the gamma voltage VnA of the first set of gamma voltages, the 2 nd voltage output terminal 402 outputs the gamma voltage Vn-1A of the first set of gamma voltages, and the nth voltage output terminal 40n outputs the gamma voltage V1A of the first set of gamma voltages in a sequential order. The selection circuit 400 may, but is not limited to, output the second set of gamma voltages in a positive sequence when the first control signal of the received control signal is low and the second control signal of the control signal is high, that is, the 1 st voltage output terminal 401 of the selection circuit 400 outputs the gamma voltage V1B of the first set of gamma voltages, the 2 nd voltage output terminal 402 outputs the gamma voltage V2B of the second set of gamma voltages, and the nth voltage output terminal 40n outputs the gamma voltage VnB of the second set of gamma voltages in a sequential sequence. The selection circuit 400 may, but is not limited to, output the second set of gamma voltages in a reverse order when the first control signal of the received control signal is high and the second control signal of the control signal is low, for example, the 1 st voltage output terminal 401 of the selection circuit 400 outputs the gamma voltage VnB of the second set of gamma voltages, the 2 nd voltage output terminal 402 outputs the gamma voltage Vn-1B of the second set of gamma voltages, and the nth voltage output terminal 40n outputs the gamma voltage V1B of the second set of gamma voltages in a sequential order.
In one embodiment, the control circuit 300 may be, but is not limited to, a single chip Microcomputer (MCU).
In one embodiment, the selection circuit 400 includes n sub-selection circuits 410, and the sub-selection circuits 410 include a first input terminal 411, a second input terminal 412, a third input terminal 413, a fourth input terminal 414, a first control terminal 415, a second control terminal 416, and an output terminal 417. The first input terminal 411 of the mth sub-selection circuit 410 is connected to the mth voltage output terminal of the first group of voltage generation circuits 100, the second input terminal 412 of the mth sub-selection circuit 410 is connected to the (n-m + 1) th voltage output terminal of the first group of voltage generation circuits 100, the third input terminal 413 of the mth sub-selection circuit 410 is connected to the mth voltage output terminal of the second group of voltage generation circuits 200, the fourth input terminal 414 of the mth sub-selection circuit 410 is connected to the (n-m + 1) th voltage output terminal of the second group of voltage generation circuits 200, the first selection terminal 415 of the mth sub-selection circuit 410 receives the first control signal, the second selection terminal 416 of the mth sub-selection circuit 410 receives the second control signal, the output terminal 417 of the mth sub-selection circuit 410 selects the voltage on one of the first to fourth input terminals 411 to 414 of the mth sub-selection circuit 410 to output according to the first and second control signals; wherein m is less than or equal to n, and m is a positive integer.
In an embodiment, the sub-selection circuit 410 includes a first switch element T1, a second switch element T2, a third switch element T3, a fourth switch element T4, a first logic unit C1, a second logic unit C2, a third logic unit C3, a fourth logic unit C4, a fifth logic unit C5, a fifth switch element T5, a sixth switch element T6, a seventh switch element T7, and an eighth switch element T8.
Fig. 2 is a circuit connection diagram of a sub-selection circuit 410 according to a first embodiment. In this embodiment, taking the mth sub-selection circuit 410 of the selection circuit 400 as an example, m is a positive integer. The first logic unit C1 includes a first input terminal, a second input terminal, and an output terminal, the first input terminal of the first logic unit C1 is connected to the first selection terminal 415 of the mth sub-selection circuit 410 through a first resistor R1, and the second input terminal of the first logic unit C1 is connected to the second selection terminal 416 of the mth sub-selection circuit 410 through a second resistor R2. The first switch element T1 includes a first control terminal, a first pass terminal and a second pass terminal, the first control terminal of the first switch element T1 is connected to the output terminal of the first logic unit C1, the first pass terminal of the first switch element T1 is connected to the first power supply V through a third resistor R3DD1And the second path terminal of the first switching element T1 is grounded. The second switching element T2 includes a second control terminal, a third path terminal and a fourth path terminal, the second control terminal of the second switching element T2 is connected to the first path terminal of the first switching element T1, the third path terminal of the second switching element T2 is connected to the first input terminal 411 of the mth sub-selection circuit 410, and the fourth path terminal of the first switching element T1 is connected to the output terminal 417 of the mth sub-selection circuit 410. The second logic cell C2 includes a first input terminal, a second input terminal, and an output terminal, the first input terminal of the second logic cell C2 is coupled to the first input terminal of the first logic cell C1, and the second input terminal of the second logic cell C2 is coupled to the second input terminal of the first logic cell C1. The third switching element T3 includes a third control terminal, a fifth path terminal and a sixth path terminal, the third control terminal of the third switching element T3 is connected to the output terminal of the first logic unit C1, the fifth path terminal of the third switching element T3 is connected to the second power source V through a fourth resistor R4DD2And the sixth path terminal of the third switching element T3 is grounded. The fourth switching element T4 includes a fourth control terminal, a seventh path terminal and an eighth path terminal, the fourth control terminal of the fourth switching element T4 is connected to the fifth path terminal of the third switching element T3, the seventh path terminal of the fourth switching element T4 is connected to the third input terminal 413 of the mth sub-selection circuit 410, and the eighth path terminal of the fourth switching element T4 is connected to the fourth path terminal of the second switching element T2。
The third logic cell C3 includes a first input terminal, a second input terminal, and an output terminal, the first input terminal of the third logic cell C3 is coupled to the first input terminal of the first logic cell C1, and the second input terminal of the third logic cell C3 is coupled to the second input terminal of the first logic cell C1. The fourth logic unit C4 includes a first input terminal, a second input terminal, and an output terminal, the first input terminal of the fourth logic unit C4 is connected to the first path terminal of the first switching element T1, and the second input terminal of the fourth logic unit C4 is connected to the output terminal of the third logic unit C3. The fifth logic unit C5 includes a first input terminal, a second input terminal, and an output terminal, the first input terminal of the fifth logic unit C5 is connected to the fourth control terminal of the fourth switching element T4, and the second input terminal of the fifth logic unit C5 is connected to the output terminal of the third logic unit C3. The fifth switching element T5 includes a fifth control terminal, a ninth path terminal and a tenth path terminal, the fifth control terminal of the fifth switching element T5 is connected to the output terminal of the fourth logic unit C4 through a fifth resistor R5, and the ninth path terminal of the fifth switching element T5 is connected to the third power source V6 through a sixth resistor R6DD3And the tenth path terminal of the fifth switching element T5 is grounded. The sixth switching element T6 includes a sixth control terminal, an eleventh path terminal and a tenth path terminal, the sixth control terminal of the sixth switching element T6 is connected to the ninth path terminal of the fifth switching element T5, the eleventh path terminal of the sixth switching element T6 is connected to the second input terminal 412 of the mth sub-selection circuit 410, and the tenth path terminal of the sixth switching element T6 is connected to the fourth path terminal of the second switching element T2. The seventh switching element T7 includes a seventh control terminal, a tenth path terminal and a tenth path terminal, the seventh control terminal of the seventh switching element T7 is connected to the output terminal of the fifth logic unit C5 through a seventh resistor R7, and the thirteenth path terminal of the seventh switching element T7 is connected to the fourth power source V8 through an eighth resistor R8DD4And the tenth path terminal of the seventh switching element T7 is grounded. The eighth switching element T8 includes an eighth control terminal, a fifteenth path terminal and a sixteenth path terminal, the eighth control terminal of the eighth switching element T8 is connected to the tenth path terminal of the seventh switching element T7, the fifteenth path terminal of the eighth switching element T8 is connected to the mth sub-selection circuit410 is connected to the fourth input terminal 414, and a sixteenth path terminal of the eighth switching element T8 is connected to the fourth path terminal of the second switching element T2.
In this embodiment, the first power supply VDD1To a fourth power supply VDD4A reference high level may be provided, but is not limited to.
Specifically, the sub-selection circuit 410 of the present embodiment receives the first control signal and the second control signal through the first selection terminal 415 and the second selection terminal 416, respectively, so as to control the switches of the first switching element T1 to the eighth switching element T8, and only one of the second switching element T2, the fourth switching element T4, the sixth switching element T6 and the eighth switching element T8 of the sub-selection circuit 410 is turned on, so that the output terminal 417 of the sub-selection circuit 410 only outputs the voltage at a corresponding one of the first input terminal 411 to the fourth input terminal 414, that is, the voltage at the corresponding voltage output terminal of the connected first group voltage generation circuit 100 or the connected second group voltage generation circuit 200. The selection circuit 400 includes a plurality of sub-selection circuits 410, after all the sub-selection circuits 410 of the selection circuit 400 respectively receive the first control signal and the second control signal through the first selection terminal 415 and the second selection terminal 416, the output terminals 417 of all the sub-selection circuits 410 only output the voltages on the corresponding one of the first input terminal 411 to the fourth input terminal 414, and when the output terminals 417 of the 1 st sub-selection circuit 410 to the output terminals 417 of the n-th sub-selection circuit 410 only output the voltages on the first input terminal 411, the 1 st voltage output terminal 401 of the selection circuit 400 correspondingly outputs the gamma voltage V1A in the first set of gamma voltages provided by the first set of voltage generation circuit 100, the 2 nd voltage output terminal 402 correspondingly outputs the gamma voltage V2A in the first set of gamma voltages provided by the first set of voltage generation circuit 100, and the n-th voltage output terminal 40n correspondingly outputs the gamma voltage VnA in the first set of gamma voltages provided by the first set of voltage generation circuit 100, the selection circuit 400 outputs the first set of gamma voltages provided by the first generation circuit to the source driving circuit 500 in a positive sequence. Similarly, when the output terminal 417 of the 1 st sub-selection circuit 410 to the output terminal 417 of the nth sub-selection circuit 410 output only the voltage at the second input terminal 412, the selection circuit 400 outputs the first set of gamma voltages provided by the first generation circuit to the source driving circuit 500 in a reverse order; when the output terminal 417 of the 1 st sub-selection circuit 410 to the output terminal 417 of the nth sub-selection circuit 410 all output only the voltage on the third input terminal 413, the selection circuit 400 outputs the second group of gamma voltages provided by the second group of voltage generation circuits 200 to the source driving circuit 500 in a positive sequence; when the output terminal 417 of the 1 st sub-selection circuit 410 to the output terminal 417 of the nth sub-selection circuit 410 all output only the voltage at the fourth input terminal 414, the selection circuit 400 outputs the second set of gamma voltages provided by the second set of voltage generation circuits 200 to the source driving circuit 500 in a reverse order.
In an embodiment, the first switching element T1, the third switching element T3, the fifth switching element T5 and the seventh switching element T7 may be, but not limited to, NPN transistors, NMOS transistors, etc., and the second switching element T2, the fourth switching element T4, the sixth switching element T6 and the eighth switching element T8 may be, but not limited to, P-channel junction field effect transistors, PNP transistors, PMOS transistors, etc.
In one embodiment, the first logic unit C1 may include, but is not limited to, the output terminal of the first logic unit C1 outputting a high signal when the first input terminal and the second input terminal of the first logic unit C1 simultaneously receive a high signal, and the output terminal of the first logic unit C1 outputting a low signal when the first input terminal and the second input terminal of the first logic unit C1 do not simultaneously receive a high signal. The second logic unit C2 may be, but not limited to, a combination of the first logic unit C1 and an inverter for level polarity inversion disposed in front of the first input terminal of the first logic unit C1, where the output terminal of the second logic unit C2 outputs a high level signal when the first input terminal of the second logic unit C2 receives no low level signal or the second input terminal receives no high level signal, the output terminal of the second logic unit C2 outputs a low level signal, and the second logic unit C2 may also be a combination of the first logic unit C1 and the inverter for level polarity inversion disposed in front of the first input terminal of the first logic unit C1. The third logic unit C3 may be, but not limited to, a third logic unit C3 that outputs a high signal when the first input terminal and the second input terminal of the third logic unit C3 simultaneously receive a high signal or simultaneously receive a low signal, and a third logic unit C3 that outputs a low signal when the first input terminal and the second input terminal of the third logic unit C3 do not simultaneously receive a high signal or simultaneously receive a low signal. The fourth logic unit C4 may be, but is not limited to, a fourth logic unit C4 that outputs a high signal when the first input terminal and the second input terminal of the fourth logic unit C4 simultaneously receive a high signal or simultaneously receive a low signal, and a fourth logic unit C4 that outputs a low signal when the first input terminal and the second input terminal of the fourth logic unit C4 do not simultaneously receive a high signal or simultaneously receive a low signal. The fifth logic unit C5 may be, but is not limited to, a combination of a first input terminal and a second input terminal of the fifth logic unit C5 receiving a high level signal simultaneously or receiving a low level signal simultaneously, an output terminal of the fifth logic unit C5 outputting a low level signal, an output terminal of the fifth logic unit C5 receiving a high level signal simultaneously or receiving a low level signal simultaneously when the first input terminal and the second input terminal of the fifth logic unit C5 receiving a high level signal simultaneously or receiving a low level signal simultaneously, the fifth logic unit C5 may be a third logic unit C3 and an inverter for level polarity inversion provided at an output terminal of the third logic unit C3, and the like.
Specifically, when the sub-selection circuit 410 receives the first control signal at the first selection terminal 415 at a high level and the second control signal at the second selection terminal 416 at a high level, the first input terminal of the first logic unit C1 receives the first control signal at the high level through the first resistor R1, the second input terminal of the first logic unit C1 receives the second control signal at the high level through the second resistor R2, so that the output terminal of the first logic unit C1 outputs the high level, and the first control terminal of the first switch element T1 receives the high level through the connected output terminal of the first logic unit C1, the first switch element T1 is turned on, so that the first pass terminal of the first switch element T1 is grounded at the low level through the turned-on first switch element T1, so that the third control terminal of the second switch element T2 receives the low level through the connected first pass terminal of the first switch element T1, the second switching element T2 is turned on so that the third path terminal and the fourth path terminal of the second switching element T2 are connected.
At the same time, of a second logic unit C2The first input terminal receives the first control signal as high level through the first resistor R1, the second input terminal of the second logic unit C2 receives the second control signal as high level through the second resistor R2, so that the output terminal of the second logic unit C2 outputs low level, and the third control terminal of the third switching element T3 receives low level through the connected output terminal of the second logic unit C2, then the third switching element T3 is turned off, so that the fifth via terminal of the third switching element T3 receives the second power supply V4 through the fourth resistor R4DD2And thus the fourth control terminal of the fourth switching element T4 receives a high level through the fifth path terminal of the connected third switching element T3, the fourth switching element T4 is turned off, i.e., the seventh path terminal and the eighth path terminal of the fourth switching element T4 are not conductive.
Meanwhile, the first input terminal of the third logic unit C3 receives the first control signal as high level through the first resistor R1, and the second input terminal of the third logic unit C3 receives the second control signal as high level through the second resistor R2, so that the output terminal of the third logic unit C3 outputs high level. A first input terminal of the fourth logic cell C4 receives a low level through the connected first path terminal of the first switching element T1, and a second input terminal of the fourth logic cell C4 receives a high level through the connected output terminal of the third logic cell C3, so that the output terminal of the fourth logic cell C4 outputs a low level. The fifth control terminal of the fifth switching element T5 receives the low level at the output terminal of the fourth logic unit C4 through the fifth resistor R5, so that the fifth switching element T5 is turned off, and the ninth path terminal of the fifth switching element T5 receives the third power source V through the sixth resistor R6DD3The sixth control terminal of the sixth switching element T6 receives a high level through the ninth path terminal of the connected fifth switching element T5, so that the sixth switching element T6 is turned off, i.e., the eleventh path terminal and the twelfth path terminal of the sixth switching element T6 are not conducted. A first input terminal of the fourth logic cell C4 receives a low level through the connected first path terminal of the first switching element T1, and a second input terminal of the fourth logic cell C4 receives a high level through the connected output terminal of the third logic cell C3, so that the output terminal of the fourth logic cell C4 outputs a low level. A fifth control terminal of the fifth switching element T5The fifth resistor R5 receives a low level at the output terminal of the fourth logic unit C4, so that the fifth switching element T5 is turned off, and the ninth path terminal of the fifth switching element T5 receives the third power source V through the sixth resistor R6DD3The sixth control terminal of the sixth switching element T6 receives a high level through the ninth path terminal of the connected fifth switching element T5, so that the sixth switching element T6 is turned off, i.e., the eleventh path terminal and the twelfth path terminal of the sixth switching element T6 are not conducted.
Meanwhile, the first input terminal of the fifth logic unit C5 receives a high level through the connected fifth path terminal of the third switching element T3, and the tenth input terminal of the fifth logic unit C5 receives a high level through the connected output terminal of the third logic unit C3, so that the output terminal of the fifth logic unit C5 outputs a low level. The seventh control terminal of the seventh switching element T7 receives the low level at the output terminal of the fifth logic unit C5 through the seventh resistor R7, so that the seventh switching element T7 is turned off, and the thirteenth path terminal of the seventh switching element T7 receives the fourth power V through the eighth resistor R8DD4The eighth control terminal of the eighth switching element T8 receives a high level through the tenth path terminal of the seventh switching element T7 connected thereto, so that the eighth switching element T8 is turned off, i.e., the fifteenth path terminal of the eighth switching element T8 and the sixteenth path terminal are not conducted.
Therefore, when the first control signal received by the first selection terminal 415 is at a high level and the second control signal received by the second selection terminal 416 is at a high level, only the second switch element T2 of the second switch element T2, the fourth switch element T4, the sixth switch element T6 and the eighth switch element T8 connected to the output terminal 417 of the sub-selection circuit 410 is turned on, so that the fourth switch terminal of the second switch element T2 receives the voltage at the first input terminal 411 of the sub-selection circuit 410 at the third switch terminal through the turned-on second switch element T2, and the fourth switch terminal of the second switch element T2 is connected to the output terminal 417 of the sub-selection circuit 410, so that the output terminal 417 of the sub-selection circuit 410 outputs the voltage at the first input terminal 411 of the sub-selection circuit 410. The first input terminal 411 of the mth sub-selection circuit 410 is connected to the mth voltage output terminal of the first group of voltage generation circuits 100, the 1 st voltage output terminal 401 of the selection circuit 400 correspondingly outputs the gamma voltage V1A of the first group of gamma voltages provided by the first group of voltage generation circuits 100, the 2 nd voltage output terminal 402 correspondingly outputs the gamma voltage V2A of the first group of gamma voltages provided by the first group of voltage generation circuits 100, and the nth voltage output terminal 40n correspondingly outputs the gamma voltage VnA of the first group of gamma voltages provided by the first group of voltage generation circuits 100 in sequence, so that the selection circuit 400 outputs the first group of gamma voltages provided by the first group of voltage generation circuits 100 to the source driving circuit 500 in a positive sequence.
Referring to the above description, it can be derived that the operation states of the first logic unit C1 to the fifth logic unit C5 and the first switch element T1 to the eighth switch when the corresponding high and low levels of the first control signal received by the first selection terminal 415 and the second control signal received by the second selection terminal 416 are applied to the sub-selection circuit 410, and the detailed operation process thereof is not repeated herein. The operation states of the first through fifth logic cells C1 through C5 are shown in the following table, wherein L represents a low level and H represents a high level.
Figure BDA0001673744820000161
Figure BDA0001673744820000171
In the above table, when the output terminal of the first logic unit C1 outputs a high level, the first switch element T1 is turned on, so that the second switch element T2 is turned on because the second control terminal thereof receives a low level; when the output terminal of the second logic unit C2 outputs a high level, the third switching element T3 is turned on, so that the fourth switching element T4 is turned on because the fourth control terminal thereof receives a low level; when the output terminal of the fourth logic unit C4 outputs a high level, the fifth switching element T5 is turned on, so that the sixth switching element T6 is turned on because the sixth control terminal thereof receives a low level; when the output terminal of the fifth logic unit C5 outputs a high level, the seventh switching element T7 is turned on, so that the eighth switching element T8 is turned on because the eighth control terminal thereof receives a low level. In the above table, the output terminals of the first logic unit C1, the second logic unit C2, the fourth logic unit C4 and the fifth logic unit C5 output high levels, which exactly correspond to the four cases of the high and low levels of the first control signal and the second control signal. Therefore, according to the high and low levels of the first control signal and the second control signal, the sub-selection circuit 410 only makes only one of the second switch element T2, the fourth switch element T4, the sixth switch element T6 and the eighth switch element T8 be turned on, and the output terminal 417 of the sub-selection circuit 410 only outputs the voltage at the corresponding one of the first input terminal 411 to the fourth input terminal 414, that is, the voltage at the corresponding voltage output terminal of the connected first group voltage generation circuit 100 or the second group voltage generation circuit 200. The selection circuit 400 includes a plurality of sub-selection circuits 410, and after all the sub-selection circuits 410 of the selection circuit 400 receive the first control signal and the second control signal through the first selection terminal 415 and the second selection terminal 416, respectively, the output terminals 417 of all the sub-selection circuits 410 only output the voltage at a corresponding one of the first input terminal 411 to the fourth input terminal 414. Therefore, when the first control signal is at a high level and the second control signal is at a high level, the gamma voltage generating device outputs the first set of gamma voltages provided by the first voltage generating circuit in a positive sequence; when the first control signal is at low level and the second control signal is at low level, the gamma voltage generating device outputs the first group of gamma voltages provided by the first voltage generating circuit in reverse order; when the first control signal is at low level and the second control signal is at high level, the gamma voltage generating device outputs a second group of gamma voltages provided by the second voltage generating circuit in a positive sequence; when the first control signal is at high level and the second control signal is at low level, the gamma voltage generating device outputs the second group of gamma voltages provided by the second voltage generating circuit in reverse order.
The gamma voltage generating device of this embodiment can output a corresponding set of gamma voltages in the plurality of sets of gamma voltages according to the positive sequence or the negative sequence of the corresponding control signal generated by the display mode, and output the gamma voltages to the source driving circuit 500, thereby providing convenience for circuit layout and saving layout space.
Second embodiment
FIG. 3 is a circuit diagram of a gamma voltage generating device according to a second embodiment. This embodiment is substantially the same as the first embodiment, except that the first group voltage generating circuit 100 includes a first resistor string, the first resistor string includes n +1 first voltage dividing resistors 110, a first end of the first resistor string receives the first dc voltage 120, a second end of the first resistor string is grounded, and a common end of every two first voltage dividing resistors 110 is connected to n voltage output ends of the first group voltage generating circuit 100.
In an embodiment, the second group voltage generating circuit 200 includes a second resistor string, the second resistor string includes n +1 second voltage-dividing resistors 210, a first end of the second resistor string receives the second dc voltage 220, a second end of the second resistor string is grounded, and a common end of every two second voltage-dividing resistors 210 is connected to n voltage output ends of the second group voltage generating circuit 200.
The gamma voltage generating device of this embodiment generates a set of gamma voltages by dividing the voltage through the resistor string, and the gamma voltage generating device can output a corresponding set of gamma voltages in the plurality of sets of gamma voltages according to the positive sequence or the negative sequence of the corresponding control signal generated by the display mode, and output the gamma voltages to the source driving circuit 500, thereby providing convenience for the circuit layout and saving the layout occupation space.
Third embodiment
Fig. 4 is a circuit connection diagram of a gamma voltage generating device according to a third embodiment. This embodiment is substantially the same as the second embodiment except that the second group voltage generating circuit 200 includes a programmable Gamma voltage buffer circuit (P-Gamma IC) including n voltage output terminals which are n voltage output terminals of the second group voltage generating circuit 200.
In one embodiment, the control signal comprises a third control signal, and the programmable gamma voltage buffer circuit is configured to buffer at least one set of gamma voltages and output a corresponding set of gamma voltages of the at least one set of gamma voltages according to the third control signal.
The gamma voltage generating device of this embodiment generates a corresponding set of gamma voltages through the programmable gamma voltage buffer circuit, and the gamma voltage generating device outputs a corresponding set of gamma voltages among the plurality of sets of gamma voltages according to the positive sequence or the negative sequence of the corresponding control signal generated by the display mode, and outputs the gamma voltages to the source driving circuit 500, thereby providing convenience for the circuit layout and saving the layout occupation space.
Fourth embodiment
The embodiment also provides a liquid crystal display device, which comprises the gamma voltage generating device.
In one embodiment, when the liquid crystal display device is in the wide viewing angle display mode, the first control signal is at a high level and the second control signal is at a high level, the gamma voltage generating device outputs the first set of gamma voltages in a positive sequence, or the first control signal is at a low level and the second control signal is at a low level, the gamma voltage generating device outputs the first set of gamma voltages in a negative sequence. When the liquid crystal display device is in the narrow viewing angle display mode, the first control signal is at a low level and the second control signal is at a high level, the gamma voltage generating device outputs the second group of gamma voltages in a positive sequence, or the first control signal is at a high level and the second control signal is at a low level, the gamma voltage generating device outputs the second group of gamma voltages in a negative sequence.
The gamma voltage generating device and the liquid crystal display device of the embodiment can output a corresponding set of gamma voltages in a plurality of sets of gamma voltages in a positive sequence or a negative sequence according to the corresponding control signals generated by the display mode, and output the gamma voltages to the source driving circuit 500, thereby providing convenience for circuit layout and saving layout occupation space.
Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. A gamma voltage generating apparatus, comprising:
a first set of voltage generation circuits (100), the first set of voltage generation circuits (100) for providing a first set of gamma voltages, the first set of voltage generation circuits (100) comprising n voltage output terminals, wherein n is a positive integer;
a second set of voltage generating circuits (200), the second set of voltage generating circuits (200) for providing a second set of gamma voltages, the second set of voltage generating circuits (200) comprising n voltage outputs;
the display control circuit comprises a control circuit (300), wherein the control circuit (300) acquires a display mode of a picture to be displayed and generates a corresponding control signal according to the display mode, and the control signal comprises a first control signal and a second control signal;
a selection circuit (400), wherein the selection circuit (400) comprises n voltage output terminals, and the selection circuit (400) is used for receiving the first group of gamma voltages and the second group of gamma voltages and outputting the first group of gamma voltages or the second group of gamma voltages to the source driving circuit (500) in a positive sequence or a negative sequence at the n voltage output terminals of the selection circuit (400) according to the control signal.
2. The gamma voltage generating apparatus of claim 1, wherein the selection circuit (400) includes n sub-selection circuits (410), the sub-selection circuits (410) including a first input terminal (411), a second input terminal (412), a third input terminal (413), a fourth input terminal (414), a first selection terminal (415), a second selection terminal (416), and an output terminal (417), a first input terminal (411) of an m-th sub-selection circuit (410) being connected to an m-th voltage output terminal of the first group of voltage generating circuits (100), a second input terminal (412) of the m-th sub-selection circuit (410) being connected to an n-m + 1-th voltage output terminal of the first group of voltage generating circuits (100), a third input terminal (413) of the m-th sub-selection circuit (410) being connected to an m-th voltage output terminal of the second group of voltage generating circuits (200), a fourth input terminal (414) of the mth sub-selection circuit (410) is connected to an n-m +1 th voltage output terminal of the second group of voltage generation circuits (200), a first selection terminal (415) of the mth sub-selection circuit (410) receives the first control signal, a second selection terminal (416) of the mth sub-selection circuit (410) receives the second control signal, and an output terminal (417) of the mth sub-selection circuit (410) selects a voltage on one of the first input terminal (411) to the fourth input terminal (414) of the mth sub-selection circuit (410) to output according to the first control signal and the second control signal;
wherein m is less than or equal to n, and m is a positive integer.
3. The gamma voltage generating apparatus of claim 2, wherein the mth sub-selection circuit (410) comprises
A first logic cell (C1), the first logic cell (C1) comprising a first input terminal, a second input terminal and an output terminal, the first input terminal of the first logic cell (C1) being connected to the first selection terminal (415) of the mth sub-selection circuit (410) through a first resistor (R1), the second input terminal of the first logic cell (C1) being connected to the second selection terminal (416) of the mth sub-selection circuit (410) through a second resistor (R2);
a first switch element (T1), the first switch element (T1) including a first control terminal, a first pass terminal and a second pass terminal, the first control terminal of the first switch element (T1) being connected to the output terminal of the first logic unit (C1), the first pass terminal of the first switch element (T1) being connected to a first power supply (V) via a third resistor (R3)DD1) The second path end of the first switching element (T1) is grounded;
a second switching element (T2), the second switching element (T2) including a second control terminal, a third pass terminal and a fourth pass terminal, the second control terminal of the second switching element (T2) being connected to the first pass terminal of the first switching element (T1), the third pass terminal of the second switching element (T2) being connected to the first input terminal (411) of the mth sub-selection circuit (410), the fourth pass terminal of the first switching element (T1) being connected to the output terminal of the mth sub-selection circuit (410);
a second logic cell (C2), the second logic cell (C2) comprising a first input, a second input, and an output, the first input of the second logic cell (C2) being coupled to the first input of the first logic cell (C1), the second input of the second logic cell (C2) being coupled to the second input of the first logic cell (C1);
a third switching element (T3), the third switching element (T3) including a third control terminal, a fifth path terminal and a sixth path terminal, the third control terminal of the third switching element (T3) being connected to the output terminal of the second logic unit (C2), the fifth path terminal of the third switching element (T3) being connected to the second power supply (V) via a fourth resistor (R4)DD2) Connected, the sixth path terminal of the third switching element (T3) is grounded;
a fourth switching element (T4), the fourth switching element (T4) including a fourth control terminal, a seventh path terminal and an eighth path terminal, the fourth control terminal of the fourth switching element (T4) being connected to the fifth path terminal of the third switching element (T3), the seventh path terminal of the fourth switching element (T4) being connected to the third input terminal (413) of the mth sub-selection circuit (410), the eighth path terminal of the fourth switching element (T4) being connected to the fourth path terminal of the second switching element (T2);
a third logic cell (C3), the third logic cell (C3) comprising a first input, a second input, and an output, the first input of the third logic cell (C3) being coupled to the first input of the first logic cell (C1), the second input of the third logic cell (C3) being coupled to the second input of the first logic cell (C1);
a fourth logic cell (C4), the fourth logic cell (C4) including a first input terminal, a second input terminal and an output terminal, the first input terminal of the fourth logic cell (C4) being connected to the first pass terminal of the first switching element (T1), the second input terminal of the fourth logic cell (C4) being connected to the output terminal of the third logic cell (C3);
a fifth logic cell (C5), the fifth logic cell (C5) comprising a first input terminal, a second input terminal and an output terminal, the first input terminal of the fifth logic cell (C5) being connected to the fourth control terminal of the fourth switching element (T4), the second input terminal of the fifth logic cell (C5) being connected to the output terminal of the third logic cell (C3);
a fifth switching element (T5), the fifth switching element (T5) comprising a fifth control terminal, a ninth path terminal and a tenth path terminal, the fifth control terminal of the fifth switching element (T5) being connected to the output terminal of the fourth logic unit (C4) through a fifth resistor (R5), the ninth path terminal of the fifth switching element (T5) being connected to a third power supply (V) through a sixth resistor (R6)DD3) The tenth path end of the fifth switching element (T5) is grounded;
a sixth switching element (T6), the sixth switching element (T6) including a sixth control terminal, an eleventh path terminal, and a tenth path terminal, the sixth control terminal of the sixth switching element (T6) being connected to the ninth path terminal of the fifth switching element (T5), the eleventh path terminal of the sixth switching element (T6) being connected to the second input terminal (412) of the mth sub-selection circuit (410), the tenth path terminal of the sixth switching element (T6) being connected to the fourth path terminal of the second switching element (T2);
a seventh switching element (T7), the seventh switching element (T7) comprising a seventh control terminal, a tenth path terminal and a tenth path terminal, the seventh control terminal of the seventh switching element (T7) being connected to the output terminal of the fifth logic unit (C5) through a seventh resistor (R7), the thirteenth path terminal of the seventh switching element (T7) being connected to a fourth power supply (V8) through an eighth resistor (R8)DD4) The tenth four-way end of the seventh switching element (T7) is grounded;
an eighth switching element (T8), the eighth switching element (T8) including an eighth control terminal, a fifteenth path terminal and a sixteenth path terminal, the eighth control terminal of the eighth switching element (T8) being connected to the tenth path terminal of the seventh switching element (T7), the fifteenth path terminal of the eighth switching element (T8) being connected to the fourth input terminal (414) of the mth sub-selection circuit (410), the sixteenth path terminal of the eighth switching element (T8) being connected to the fourth path terminal of the second switching element (T2).
4. The gamma voltage generating apparatus of claim 3, wherein the first switching element (T1), the third switching element (T3), the fifth switching element (T5) and the seventh switching element (T7) are NPN type transistors, and the second switching element (T2), the fourth switching element (T4), the sixth switching element (T6) and the eighth switching element (T8) are P channel junction field effect transistors.
5. The gamma voltage generating apparatus of claim 3, wherein the output terminal of the first logic unit (C1) outputs a high level signal when the first input terminal and the second input terminal of the first logic unit (C1) simultaneously receive a high level signal, and the output terminal of the first logic unit (C1) outputs a low level signal when the first input terminal and the second input terminal of the first logic unit (C1) simultaneously receive a high level signal;
when the first input end of the second logic unit (C2) receives a low level signal and the second input end receives a high level signal at the same time, the output end of the second logic unit (C2) outputs a high level signal, and when the first input end of the second logic unit (C2) does not receive a low level signal or the second input end does not receive a high level signal, the output end of the second logic unit (C2) outputs a low level signal;
when the first input end and the second input end of the third logic unit (C3) receive high level signals simultaneously or receive low level signals simultaneously, the output end of the third logic unit (C3) outputs high level signals, and when the first input end and the second input end of the third logic unit (C3) do not receive high level signals simultaneously or receive low level signals simultaneously, the output end of the third logic unit (C3) outputs low level signals;
when the first input end and the second input end of the fourth logic unit (C4) receive high level signals simultaneously or receive low level signals simultaneously, the output end of the fourth logic unit (C4) outputs high level signals, and when the first input end and the second input end of the fourth logic unit (C4) do not receive high level signals simultaneously or receive low level signals simultaneously, the output end of the fourth logic unit (C4) outputs low level signals;
when the first input end and the second input end of the fifth logic unit (C5) receive high level signals simultaneously or receive low level signals simultaneously, the output end of the fifth logic unit (C5) outputs low level signals, and when the first input end and the second input end of the fifth logic unit (C5) do not receive high level signals simultaneously or receive low level signals simultaneously, the output end of the fifth logic unit (C5) outputs high level signals.
6. The gamma voltage generating apparatus according to claim 2, wherein the first group of voltage generating circuits (100) comprises a first resistor string, the first resistor string comprises n +1 first voltage dividing resistors (110), a first end of the first resistor string receives the first dc voltage (120), a second end of the first resistor string is grounded, and a common end of every two first voltage dividing resistors (110) is connected to the n voltage output ends of the first group of voltage generating circuits (100).
7. The gamma voltage generating apparatus according to claim 6, wherein the second group of voltage generating circuits (200) comprises a second resistor string, the second resistor string comprises n +1 second voltage dividing resistors (210), a first end of the second resistor string receives the second DC voltage (220), a second end of the second resistor string is grounded, and a common end of every two second voltage dividing resistors (210) is connected to the n voltage output ends of the second group of voltage generating circuits (200).
8. The gamma voltage generating apparatus of claim 6, wherein the control signal comprises a third control signal, the second set of voltage generating circuits (200) comprises a programmable gamma voltage buffer circuit, the programmable gamma voltage buffer circuit comprises n voltage output terminals being the n voltage output terminals of the second set of voltage generating circuits (200), the programmable gamma voltage buffer circuit is configured to buffer at least one set of gamma voltages and output a corresponding one of the at least one set of gamma voltages according to the third control signal.
9. A liquid crystal display device including a gate driver circuit, characterized in that the liquid crystal display device includes the gamma voltage generating device according to any one of claims 1 to 8.
10. The liquid crystal display device as claimed in claim 9, wherein when the liquid crystal display device is in the wide viewing angle display mode, the gamma voltage generating device outputs the first set of gamma voltages in a positive order if the first control signal is high and the second control signal is high, or outputs the first set of gamma voltages in a negative order if the first control signal is low and the second control signal is low;
when the liquid crystal display device is in a narrow viewing angle display mode, if the first control signal is at a low level and the second control signal is at a high level, the gamma voltage generation device outputs the second group of gamma voltages in a positive sequence, or if the first control signal is at a high level and the second control signal is at a low level, the gamma voltage generation device outputs the second group of gamma voltages in a negative sequence.
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