CN108733956B - Method for optimizing impedance discontinuity at high-speed link capacitor - Google Patents
Method for optimizing impedance discontinuity at high-speed link capacitor Download PDFInfo
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- CN108733956B CN108733956B CN201810542387.1A CN201810542387A CN108733956B CN 108733956 B CN108733956 B CN 108733956B CN 201810542387 A CN201810542387 A CN 201810542387A CN 108733956 B CN108733956 B CN 108733956B
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- 239000003990 capacitor Substances 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 title claims abstract description 20
- 230000007704 transition Effects 0.000 claims abstract description 21
- 238000004088 simulation Methods 0.000 claims abstract description 14
- 238000013461 design Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 4
- 230000008054 signal transmission Effects 0.000 description 4
- 238000002847 impedance measurement Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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Abstract
The invention discloses a method for optimizing impedance discontinuity at a high-speed link capacitor, wherein the high-speed link comprises a mainboard, and the mainboard comprises a transmitting end, a capacitor and a receiving end; the transmitting end is connected with the capacitor through an outgoing line L1 and a main board main line L2, and the capacitor is connected with the receiving end through a connecting line L3; the method comprises the following steps: adding a transition zone trace a1 between L2 and the capacitor and adding a transition zone trace a2 between the capacitor and L3; adjusting the impedance of A1 and A2, and performing time domain reflectometer simulation aiming at different impedances of A1 and A2; comparing the impedance continuity condition of the high-speed link when the impedance A1 and the impedance A2 are different according to the simulation result; according to the comparison result, the optimal impedance values of A1 and A2 are determined. According to the method disclosed by the invention, the transition area wiring is added in front of and behind the capacitor, and the optimal value of the wiring impedance of the transition area is obtained by simulating the influence of the transition area wiring on the overall characteristics of the link under different impedance conditions.
Description
Technical Field
The invention relates to the technical field of servers, in particular to a method for optimizing impedance discontinuity at a high-speed link capacitor.
Background
In conventional digital system designs, high speed interconnect phenomena are often negligible because they have a weak impact on the performance of the system. However, with the continuous development of computer technology, the phenomenon of high-speed interconnection is dominant among many factors determining the performance of the system, often resulting in some unpredictable problems, and greatly increasing the complexity of system design. Therefore, in the high-speed link design, each module is optimized as much as possible, the design feasibility and risk points are evaluated in advance by means of a simulation tool, the design is optimized according to the simulation result, the success rate of the system design is improved, and the research and development period is shortened.
In the process of designing a high-speed signal link of a server system, the optimization design of the link impedance is particularly important, and if the continuity of the link impedance is poor, signal reflection and link loss are caused, so that the signal transmission quality is influenced, and even the design is failed.
In the prior art, in the design of a high-speed link, most engineers may start from the characteristics of a capacitor by digging out a reference plane of a capacitor pad to reduce the capacitance of the capacitor, so as to improve the impedance and reduce the impedance discontinuity. Although the above design concept can effectively improve the impedance at the capacitor and reduce the impedance discontinuity, the hollowed-out capacitor pad reference layer can reduce the integrity of the reference plane, influence the current flow distribution, and possibly cause the power integrity problem. In addition, if there are other high-speed lines under the capacitor, the reference planes of the other high-speed lines are not complete, which affects the signal transmission quality.
Disclosure of Invention
Based on the technical problems in the background art, the invention provides a method for optimizing impedance discontinuity at a high-speed link capacitor, transition region wiring is added in front of and behind the capacitor, and the optimal value of the impedance of the transition region wiring is obtained by simulating the influence of the transition region wiring on the overall characteristics of the link under different impedance conditions, so that the impedance change at the capacitor is minimized, and the signal transmission quality is effectively improved.
The invention provides a method for optimizing impedance discontinuity at a high-speed link capacitor, wherein the high-speed link comprises a mainboard, and the mainboard comprises a transmitting end, a capacitor and a receiving end; the transmitting end is connected with the capacitor through an outgoing line L1 and a main board main line L2, and the capacitor is connected with the receiving end through a connecting line L3;
the method comprises the following steps:
adding a transition zone trace a1 between L2 and the capacitor and adding a transition zone trace a2 between the capacitor and L3;
adjusting the impedance of A1 and A2, and performing time domain reflectometer simulation aiming at different impedances of A1 and A2;
comparing the impedance continuity condition of the high-speed link when the impedance A1 and the impedance A2 are different according to the simulation result;
according to the comparison result, the optimal impedance values of A1 and A2 are determined.
Preferably, the sum of the lengths of L2 and a1 remains constant.
Preferably, the sum of the lengths of L3 and a2 remains constant.
Preferably, the high-speed link is a PCIE link.
According to the method for optimizing the impedance discontinuity at the high-speed link capacitor, the routing of the transition region is added in front of and behind the capacitor, and the optimal value of the routing impedance of the transition region is obtained by simulating the influence of the routing of the transition region on the overall characteristics of the link under different impedance conditions, so that the impedance change at the capacitor is minimized, and the signal transmission quality is effectively improved.
Drawings
FIG. 1 is a flow chart of a method for optimizing impedance discontinuity at a high speed link capacitor in accordance with the present invention;
FIG. 2 is a diagram of the length of each segment of the high-speed link;
FIG. 3 is a graph of a link time domain reflectometer simulation with a transition region A1 of 80 ohms and A2 of 83 ohms;
FIG. 4 is a simulation diagram of a link time domain reflectometer with transition region A1 of 87 ohms, A2 of 90 ohms, A1 of 93 ohms, and A2 of 95 ohms;
FIG. 5 is a partial magnified view of a high speed link time domain reflectometer and impedance measurements.
Detailed Description
1-5, FIG. 1 is a flow chart of a method for optimizing impedance discontinuity at a high speed link capacitor according to the present invention; FIG. 2 is a diagram of the length of each segment of the high-speed link; FIG. 3 is a graph of a link time domain reflectometer simulation with a transition region A1 of 80 ohms and A2 of 83 ohms; FIG. 4 is a simulation diagram of a link time domain reflectometer with transition region A1 of 87 ohms, A2 of 90 ohms, A1 of 93 ohms, and A2 of 95 ohms; FIG. 5 is a partial magnified view of a high speed link time domain reflectometer and impedance measurements.
The invention is described in detail below with reference to the figures and examples.
A method of optimizing impedance discontinuity at a high speed link capacitor, comprising the steps of:
s1: the method comprises the following steps of dividing the routing in the PCIE high-speed link into a transmitting end outgoing line L1, a main board main routing L2, a main board main routing L2 and a transition area routing A1 between capacitors, a connecting line L3 between the capacitors and a receiving end and a transition area routing A2 between the capacitors and L3;
s2: adjusting the impedance of A1 and A2, and performing time domain reflectometry simulation aiming at different impedances of A1 and A2, wherein the sum of the lengths of L2 and A1 keeps a constant value, and the sum of the lengths of L3 and A2 keeps a constant value;
s3: comparing the impedance continuity condition of the high-speed link when the impedance A1 and the impedance A2 are different according to the simulation result;
s4: according to the comparison result, the optimal impedance values of A1 and A2 are determined.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and the technical solutions and the inventive concepts thereof according to the present invention should be equivalent or changed within the scope of the present invention.
Claims (4)
1. A method for optimizing impedance discontinuity at a high-speed link capacitor, wherein the high-speed link comprises a main board, the main board comprises a transmitting end, a capacitor and a receiving end; the transmitting end is connected with the capacitor through an outgoing line L1 and a main board main line L2, and the capacitor is connected with the receiving end through a connecting line L3;
the method comprises the following steps:
adding a transition zone trace a1 between L2 and the capacitor and adding a transition zone trace a2 between the capacitor and L3;
adjusting the impedance of A1 and A2, and performing time domain reflectometer simulation aiming at different impedances of A1 and A2;
comparing the impedance continuity condition of the high-speed link when the impedance A1 and the impedance A2 are different according to the simulation result;
according to the comparison result, the optimal impedance values of A1 and A2 are determined.
2. The method for optimizing impedance discontinuity according to claim 1, wherein the sum of the lengths of L2 and a1 is kept constant.
3. The method for optimizing impedance discontinuity according to claim 1, wherein the sum of the lengths of L3 and a2 is kept constant.
4. The method of optimizing impedance discontinuity at high speed link capacitance of claim 1 wherein said high speed link is a PCIE link.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810542387.1A CN108733956B (en) | 2018-05-30 | 2018-05-30 | Method for optimizing impedance discontinuity at high-speed link capacitor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810542387.1A CN108733956B (en) | 2018-05-30 | 2018-05-30 | Method for optimizing impedance discontinuity at high-speed link capacitor |
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| CN108733956A CN108733956A (en) | 2018-11-02 |
| CN108733956B true CN108733956B (en) | 2021-11-02 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN203206579U (en) * | 2013-04-15 | 2013-09-18 | 杭州华三通信技术有限公司 | Device for improving impedance continuity of signal line |
| CN104125177A (en) * | 2014-07-17 | 2014-10-29 | 浪潮电子信息产业股份有限公司 | Design method of differential line winding compensation |
| CN105792516A (en) * | 2016-02-25 | 2016-07-20 | 广东欧珀移动通信有限公司 | Flexible-rigid circuit board and mobile terminal |
| CN105975703A (en) * | 2016-05-11 | 2016-09-28 | 浪潮电子信息产业股份有限公司 | To-be-laid route forming method, device and PCB |
| CN107995774A (en) * | 2017-11-28 | 2018-05-04 | 无锡市同步电子科技有限公司 | A kind of cabling optimization method of Surface Mount radio-frequency maser |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090058425A1 (en) * | 2007-08-31 | 2009-03-05 | International Business Machines Corporation | Method and apparatus to test electrical continuity and reduce loading parasitics on high-speed signals |
| US10276519B2 (en) * | 2015-06-02 | 2019-04-30 | Sarcina Technology LLC | Package substrate differential impedance optimization for 25 to 60 Gbps and beyond |
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2018
- 2018-05-30 CN CN201810542387.1A patent/CN108733956B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN203206579U (en) * | 2013-04-15 | 2013-09-18 | 杭州华三通信技术有限公司 | Device for improving impedance continuity of signal line |
| CN104125177A (en) * | 2014-07-17 | 2014-10-29 | 浪潮电子信息产业股份有限公司 | Design method of differential line winding compensation |
| CN105792516A (en) * | 2016-02-25 | 2016-07-20 | 广东欧珀移动通信有限公司 | Flexible-rigid circuit board and mobile terminal |
| CN105975703A (en) * | 2016-05-11 | 2016-09-28 | 浪潮电子信息产业股份有限公司 | To-be-laid route forming method, device and PCB |
| CN107995774A (en) * | 2017-11-28 | 2018-05-04 | 无锡市同步电子科技有限公司 | A kind of cabling optimization method of Surface Mount radio-frequency maser |
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| CN108733956A (en) | 2018-11-02 |
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