CN108733305A - Memory device, system and its operating method - Google Patents
Memory device, system and its operating method Download PDFInfo
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- CN108733305A CN108733305A CN201710243291.0A CN201710243291A CN108733305A CN 108733305 A CN108733305 A CN 108733305A CN 201710243291 A CN201710243291 A CN 201710243291A CN 108733305 A CN108733305 A CN 108733305A
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- memory
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- memory cell
- electrical parameter
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0617—Improving the reliability of storage systems in relation to availability
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0625—Power saving in storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
- G06F3/0634—Configuration or reconfiguration of storage systems by changing the state or mode of one or more devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0658—Controller construction arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
Abstract
The invention discloses a kind of memory device, system and its operating methods.Wherein, which includes memory cell and selector.Memory cell is storing data.Selector coupled memory cells, selector have the adjustable electrical parameter that can be configured to varying level；Wherein when the adjustable electrical parameter of selector is configured to the first level, selector is opened in response to the operation signal of enable, to allow the data in memory cell to be accessed；When the adjustable electrical parameter of selector is configured to second electrical level, selector is remained off when receiving the operation signal of enable, to forbid the data in memory cell to be accessed.
Description
Technical field
The invention relates to a kind of memory device, system and its operating methods.
Background technology
Resistive memory, such as resistive random access memory storare device (Resistive Random Access Memory,
ReRAM), it has been widely used in various electronic product.Resistive memory includes multiple storage units, each storage unit
With specific resistance value to indicate the data value of storage, such as 0 or 1.In general, to the storage unit of resistive memory
It is programmed operation, can be completed by changing the resistance value of storage unit.
However, can not often be set via programming operation to scheduled in the presence of a small number of storage units in resistive memory
Resistance value so that there are error bit (failure bit) in memory.Since these error bits typically occur and are difficult at random
How prediction, effectively inhibit the influence of these error bits, becomes the key for improving storage device reliability.
Invention content
The invention relates to a kind of memory device, storage system and its operating methods.Memory device includes depositing
Storage unit and selector.Selector has the adjustable electrical parameter that can be configured to varying level.When selector can
Mode electrical parameter is set at the first level, and selector is operated in an enabled status.In the case, when memory cell quilt
It chooses, selector will be opened so that memory cell can be programmed or read.On the other hand, when selector it is adjustable electrically
Parameter is set at second electrical level, and selector will be operated in a disabled state.In the case, when memory cell is selected
It takes, selector will remain off so that memory cell can not be accessed.Using above-mentioned characteristic, control circuit can be first from storage
Pick out in device array can not successful program memory cell, then by couple these can not successful program memory cell
Selector is set to disabled state, to avoid error bit to the adverse effect of storage device.In addition, once selector is in
Disabled state, memory device will operate condition in extremely low leakage current, therefore can effectively avoid latent channel current (sneak
Path current) influence, and improve power consumption.
An embodiment according to the present invention, proposes a kind of memory device.Memory device include memory cell and
Selector.Memory cell is storing data.Selector coupled memory cells, selector have can be configured to different electricity
Flat adjustable electrical parameter；Wherein when the adjustable electrical parameter of selector is configured to the first level, selector response causes
Can (enabled) operation signal and open, to allow the data in memory cell to be accessed；When the adjustable electric of selector
Property parameter be configured to second electrical level, selector is remained off when receiving the operation signal of enable, to forbid memory cell
In data be accessed.
An embodiment according to the present invention, proposes a kind of storage system.Storage system include memory array and
Control circuit.Memory array includes multiple memory devices, and each memory device includes memory cell and selector.Choosing
It selects device and is coupled to memory cell, selector has the adjustable electrical parameter that can be configured to varying level.Control circuit coupling
Memory array is connect, to access these memory cells, and sets the adjustable electrical parameter of these selectors.Wherein when this
The adjustable electrical parameter of a specific selector in a little selectors is set at the first level, and specific selector responds enable
(enabled) operation signal and open, to allow to couple the specific memory list of specific selector in these memory cells
The data of member are accessed；When the adjustable electrical parameter of specific selector is set at second electrical level, specific selector is receiving
It is remained off when the operation signal of enable, to forbid the data in particular memory cell to be accessed.
An embodiment according to the present invention proposes a kind of operating method of storage system.Storage system includes storage
Device array, memory array include multiple memory devices, and each memory device includes memory cell and selector, selection
Device coupled memory cells, and with the adjustable electrical parameter that can be configured to varying level.The operating method includes：
These memory cells are read, to judge whether these memory cells pass through programming operation；When judging these memory lists
After a particular memory cell in member is by programming operation, the specific choosing of particular memory cell will be coupled in these selectors
The adjustable electrical parameter setting of device is selected in the first level, to control specific selector in the operation for receiving enable (enabled)
Signal is opened, to allow the data in particular memory cell to be accessed；When judging that particular memory cell do not pass through volume
Journey operates, and by the adjustable electrical parameter setting of specific selector in second electrical level, enable is being received to control specific selector
Operation signal when remain off, to forbid the data in particular memory cell to be accessed.
In order to which the above-mentioned and other aspect to the present invention has a better understanding, special embodiment below, and coordinate appended attached
Detailed description are as follows for figure：
Description of the drawings
Fig. 1 is painted the schematic diagram of the memory device according to one embodiment of the invention.
Fig. 2A is painted the I-E characteristic figure of the adjustable electrical parameter of the selector according to one embodiment of the invention.
Fig. 2 B are painted the I-E characteristic of the adjustable electrical parameter of the selector according to another embodiment of the present invention
Figure.
Fig. 3 A are painted the schematic diagram of the storage system according to one embodiment of the invention.
Fig. 3 B are painted an example circuit diagram of memory device.
Fig. 4 is painted the flow chart of the operating method of the storage system according to one embodiment of the invention.
Fig. 5 is painted the flow chart of the operating method of the storage system according to one embodiment of the invention.
Fig. 6 A-6C are painted the operation waveform diagram of the storage system according to one embodiment of the invention.
Fig. 7 is painted the schematic diagram of the data mode of the memory cell according to one embodiment of the invention.
【Symbol description】
100：Memory device
102：Memory cell
104：Selector
Vth1,R1,Vth1′：First level of adjustable electrical parameter
Vth2,R2,Vth2′：The second electrical level of adjustable electrical parameter
Vop：The voltage level of the operation signal of enable
302：Memory array
304：Control circuit
306：Memory device
308-1~308-m, 308：Wordline
310-1~310-n, 310：Bit line
312：Memory cell
314：Selector
316：Bias generator
M1：Transistor
Vg,Vs,Vb：Voltage
402,404,406,502,504,506,508,510,512：Step
T1：First period
T2：The second phase
T3：During third
T4：Between the fourth phase
S1,S2：Data mode
S0：Disabled state
Specific implementation mode
It is to propose that embodiment is described in detail below, embodiment can't limit this hair only to illustrate as example
The bright range to be protected.In addition, the attached drawing in embodiment is to omit unnecessary element, the technology to clearly show that the present invention is special
Point.
Fig. 1 is painted the schematic diagram of the memory device 100 according to one embodiment of the invention.Memory device 100 can be used as
A storage unit in memory.Memory device 100 includes memory cell 102 and selector 104.Memory cell
102 storing data (such as user data).104 coupled memory cells 102 of selector.As shown in Figure 1, selector 104
It is concatenated with memory cell 102, with the cellular construction of formation " 1S1R ".Selector 104 can be opened or closed.Work as selector
104 are opened, and memory cell 102 will access for external circuit；When selector 104 is closed, memory cell 102 will not
Permission is accessed by external circuit.
It may be noted that although selector 104 is rendered as the cellular construction of " 1S1R " with memory cell 102 in Fig. 1, originally
Invention is not limited thereto.Memory device 100 may include one or more selectors 104 and one or more memory cells
102, to form different cellular constructions, such as " 2S1R " cellular construction.
Memory cell 102 can be various suitable memory elements.By taking resistance-type memory as an example, memory cell
102 can be programmed to specific resistance states (such as high resistance state or low resistance state) to indicate a specific data value
(such as 1 or 0).In the case, indicate that the resistance states of data value can be considered a data mode of memory cell 102.
According to the embodiment of the present invention, selector 104 has the adjustable electrical parameter that can be configured to varying level.When
The adjustable electrical parameter of selector 104 is configured to the first level, and selector 104 is enabled status, and selector 104 will respond
The operation signal of enable and open, to allow the data in memory cell 102 to be accessed.When the adjustable electric of selector 104
Property parameter be configured to second electrical level, selector 104 is disabled state, and selector 104 is when receiving the operation signal of enable
It still remains off, to forbid the data in memory cell 102 to be accessed.
In some embodiments, operation signal refers to the signal for choosing the particular memory cell to be accessed, as
It is the online voltage of character.When the operation signal that selector 104 receives is enable, the memory of expression coupling selector 104
Unit 102 is read or is programmed by selection；Conversely, when the operation signal that selector 104 receives is disabled, coupling selection is indicated
The 102 not selected reading of memory cell or programming of device 104.
The adjustable electrical parameter of selector 104 can be the threshold voltage (threshold of selector 104
Voltage), opening resistor value (turn-on resistance) or other electrical parameters appropriate, reality of the end regarding selector 104
Depending on existing mode.
In some embodiments, selector 104 can be by transistor, the semiconductor of diode or other changeable conducting states
Structure is realized.For example, selector 104 can be by with floating gate (floating gate) or charge-trapping (charge
Trapping) transistor of structure is realized.By changing the quantity of electric charge on floating gate or charge trapping structure, selection can adjust
Threshold voltage (adjustable electrical parameter) level of device 104.
Fig. 2A is painted the I-E characteristic of the adjustable electrical parameter of the selector 104 according to one embodiment of the invention
Figure.In the example of Fig. 2A, the adjustable electrical parameter of selector 104 is threshold voltage.The threshold voltage of selector 104 can quilt
It is set in the first level Vth1 or higher second electrical level Vth2.
The voltage level of the operation signal of enable is Vop.Due to Vop > Vth1, therefore when the threshold voltage quilt of selector 104
It is set in the first level Vthl, selector 104 will be opened in response to the operation signal of enable.On the other hand, due to Vop <
Vth2, therefore when the threshold voltage of selector 104 is set at second electrical level Vth2, whether the operation signal no matter received is cause
Can, selector 104 can all maintain in off position.
The current-voltage that Fig. 2 B are painted the adjustable electrical parameter of the selector 104 according to another embodiment of the present invention is special
Property figure.In the example of Fig. 2 B, the adjustable electrical parameter of selector 104 is opening resistor value.The opening resistor of selector 104
Value can be set at the first level R1 or higher second electrical level R2.
The voltage level of the operation signal of enable is Vop.When the opening resistor value of selector 104 is set at the first level
R1, selector 104 will be opened in response to the operation signal of enable.Conversely, when the opening resistor value of selector 104 is set at the
Two level R2, no matter whether operation signal is enable, and selector 104 is all to close.
In more general terms, when the adjustable electrical parameter of selector 104 is set at the first level, selector 104 will be located
In enabled status.When the adjustable electrical parameter of selector 104 is set at second electrical level, selector 104 will be in disabled
State.Under enabled status, selector 104 can switch its conducting state in response to the variation of operation signal.Therefore, selector
104, which can be used as address device (addressing device), to be opened when memory cell 102 is selected, for memory
Unit 102 is accessed.Under disabled state, selector 104 can remain off always, and the operation signal that will not be received
It opens.Therefore, selector 104 will forbid external control circuit electrically to operate memory cell 102, such as read and write
Enter.
Fig. 3 A are painted the schematic diagram of the storage system 300 according to one embodiment of the invention.Storage system 300 includes depositing
Memory array 302 and control circuit 304.
Memory array 302 includes multiple memory devices 306.Each memory device 306 includes an at least memory
Unit 312 and at least a selector 314.In a memory device 306, memory cell 312 selects to store data
Device 314 is coupled to memory cell 312, and with the adjustable electrical parameter that can be configured to varying level.
304 couples memory array 302 of control circuit.Control circuit 304 can access the memory list of memory device 306
Member 312, and set the adjustable electrical parameter of each selector 314.Control circuit 304 can be microcontroller, microprocessor,
Application-specific integrated circuit (Application-Specific Integrated Circuit, ASIC) or other are suitable hard
Part circuit.
As shown in Figure 3A, control circuit 304 connects via a plurality of wordline 308-1~308-m and bit line 310-1~310-n
It is connected to memory array 302.304 decodable code of control circuit, one access requirement, and to wordline 308-1~308-m and bit line
310-1~310-n applies bias appropriate and is chosen, with the specific memory list to specific position in memory array 302
Member 312 such as is read out, (programming) be written at electrical operate.
Control circuit 304 also can severally set the adjustable electrical parameter of different selectors 314.Therefore, no
Same selector 314 may be set at enabled status or disabled state.For example, control circuit 304 can first read and deposit
Memory cell 312 in memory array 302 is the error bit that can not be successfully programmed to recognize which memory cell 312,
Which is the healthy position (healthy bit) that can be successfully programmed.
Disabled state will be set in by control circuit 304 by coupling the selector 314 of the memory cell 312 of error bit
(that is, adjustable electrical parameter is set at second electrical level), is accessed to avoid error bit, and is leaked caused by lowering error bit
Electric current.
On the other hand, cause will be set in by control circuit 304 by coupling the selector 314 of the memory cell 312 of healthy position
Energy state (that is, adjustable electrical parameter is set at the first level) allows the memory cell 312 of healthy position can be normal electrical
Under the conditions of be accessed.
Fig. 3 B are painted an example circuit diagram of a certain memory device 306 in Fig. 3 A.As shown in Figure 3B, memory device 306
Including memory cell 312 and selector 314.Memory cell 312 is coupled in a specific bit line 310 (such as Fig. 3 A bit lines
A certain bit line in 310-1~310-n) between selector 314.
Selector 314 includes a transistor M1.Transistor M1 have one wordline 308 of coupling (such as Fig. 3 A wordline 308-1~
A certain wordline in 308-m) control terminal (such as grid), 312 first end of coupled memory cells (as drain) and coupling
The second end (such as source electrode) of one bias generator 316.Wordline 308 is transmitting operation signal.When the operation news being applied in wordline 308
Number be enable (such as with high potential), indicate couple this wordline 308 memory device 306 by control circuit 304 select make
Further electrically operation；Conversely, when the operation signal being applied in wordline 308 is disabled (such as with low potential), indicate
Couple 306 not controlled circuit 304 of the memory device selection of this wordline 308.
When selector 314 is in disabled state, the threshold voltage of transistor M1 is set at second electrical level so that crystal
Pipe M1 is always to close, and do not opened by operation signal.In the case, when memory cell 312 is selected by control circuit 304
It selects, control circuit 304 can only detect faint electric current (or high resistance), this faint electric current and corresponding data shape
The sensing electric current of state is compared, about low 4 orders of magnitude.Therefore, it is because of non-cause that control circuit 304, which can pick out faint electric current,
Energy state causes, and unrelated with the data mode of memory cell 312.
When selector 314 is in enabled status, the threshold voltage of transistor M1 will be configured to the first level.In this situation
Under, transistor M1 can be opened in response to the operation signal of enable, and be closed in response to the operation signal of disabled.As transistor M1
It is opened, memory cell 312 will allow to be accessed.
In one embodiment, control circuit 304 can execute transistor M1 one hot carrier injection (hot carrier
Injection) or a Fu Le-Nuo Deng penetrate (Fowler-Nordheim tunneling) operation, by the threshold value of transistor M1
Voltage is adjusted from the first level to second electrical level.The second electrical level is for example higher than the first level.
It is noted that although memory device 306 is realized with the circuit framework of Fig. 3 B in above-mentioned example, this hair
It is bright to be not limited thereto.Memory device described in various embodiments of the present invention is all suitable as the storage of storage system 300
Device device 306.
Fig. 4 is painted the flow chart of the operating method of the storage system 300 according to one embodiment of the invention.
In step 402, control circuit 304 reads multiple memory cells 312 in memory array 302, to judge this
Whether a little memory cells 312 pass through a programming operation.
Programming operation may include one or more programming steps, setting memory cell 312 to scheduled data shape
State.When a memory cell 312 is by programming operation, indicate that the memory cell 312 after being handled by programming operation, has become
Work(it is programmed to scheduled data mode.It is considered as healthy position by the memory cell 312 of programming operation.Conversely, when one
Memory cell 312 indicates the memory cell 312 after being handled by programming operation not by programming operation, and can not be by
It is programmed to scheduled data mode.It can not be considered as error bit by the memory cell 312 of programming operation.
In step 404, for one or more (health of memory cell 312 by programming operation in memory array 302
Position), control circuit 304 will couple this one or more by the adjustable of the selector 314 of the memory cell 312 of programming operation
Electrical parameter is set in the first level.
It is (wrong for one or more memory cells 312 not by programming operation in memory array 302 in step 406
Accidentally position), control circuit 304 by couple this one or more not by the selector 314 of the memory cell of programming operation 312 can
Mode electrical parameter is set in second electrical level.
Described in brought forward, when the adjustable electrical parameter of selector 314 is set at the first level, selector 314 will operate
In enabled status, selector 314 will switch its conducting state in response to the variation of operation signal at this time；When selector 314 can
Mode electrical parameter is set at second electrical level, and selector 314 will be operated in disabled state, and selector 104 maintains always
Closed state, and the operation signal that will not be received is opened.
By the above-mentioned means, the memory cell 306 (error bit) that can not be successfully programmed in memory array 302 by because
For selector 314 is configured to disabled state and can not be accessed.Therefore, it can avoid unfavorable shadow of the error bit to storage device
It rings.In addition, once selector 314 is configured to disabled state, selector 314 is equivalent to open circuit, therefore can effectively solve to leak electricity
The problem of stream.
In one embodiment, the flow such as Fig. 4 can be executed in the manufacturing process of memory, in advance by memory array
In error bit set at disabled state.In another embodiment, control circuit 304 can be held periodically or in response to trigger event
The flow of row such as Fig. 4.
To help to understand, the more details of an illustration and non-limiting examples are described below in conjunction with Fig. 5 and Fig. 6 A-6C.
Fig. 5 is painted the flow chart of the operating method of the storage system 300 according to one embodiment of the invention.Fig. 6 A-6C are painted
Show the operation waveform diagram of the storage system 300 according to one embodiment of the invention.In this example, memory device 306 be with
Circuit structure shown in Fig. 3 B realizes that wherein transistor M1 is, for example, a floating gate transistors, and memory cell 312 is an electricity
The memory element of resistive memory.
As shown in figure 5, in step 502, it is alternatively that the floating gate transistors of device 314 manufacture under normal operation, make each
Selector 314 is initially operated in enabled status.In the case, adjustable electrical parameter (the threshold value electricity of each selector 314
Pressure) it is set at the first level, for example, about 0.6 volt.
In step 504, control circuit 304 executes programming operation to memory cell 312.Programming operation will be for example including that will deposit
Storage unit 312 is programmed to the operation of " setting (SET) " state and/or memory cell 312 is programmed to " resetting
(RESET) " operation of state.
B and Fig. 6 A are please referred to Fig.3, if programming operation is the programming for belonging to SET state, in first period T1, control circuit
The voltage Vg of bit line 308 is set in the level higher than the first level, such as 1.2 volts by 304, and by the voltage of bias generator 316
Vs is set in 1.5 volts or higher.Under this bias condition, selector 314 is opened, and memory cell 312 is programmed to
SET state.
B and Fig. 6 B are please referred to Fig.3, if programming operation is the programming for belonging to RESET state, in first period T1, control electricity
Voltage Vg is set in the level higher than the first level Vth1 ', such as 1.2 volts by road 304, and 310 voltage Vb of bit line is set
In 1.5 volts or higher.Under this bias condition, selector 314 is opened, and memory cell 312 is programmed to RESET shapes
State.
In step 506, control circuit 304 is read after executing programming to memory cell 312.Then in step 508, control
Circuit 304 judges whether to successfully pass programming operation for other memory cell 312.
Referring again to Fig. 3 B and Fig. 6 A, if the programming operation performed by step 504 is the programming for belonging to SET state,
In second phase T2, voltage Vg is set in higher than the first level Vth1 ' level, such as 1.2 volts by control circuit 304, and will
Voltage Vb is set in low level, such as 0.1,0.3 or 0.5 volt.Under this bias condition, selector 314 is opened, and is stored
Device unit 312 is read.Whether control circuit 304 can judge memory cell 312 in correspondence according to the size of sensing electric current
The low-resistance value of SET state, such as 30K ohm.For example, once control circuit 304 detects the size of sensing electric current about
For 20~50 microamperes (μ A), then judge that memory cell 312 is successfully programmed to SET state.Conversely, then judging memory cell
312 do not pass through programming operation.
Referring again to Fig. 3 B and Fig. 6 B, if the programming operation performed by step 504 is the volume for belonging to RESET state
Journey, in second phase T2, voltage Vg is set in the level higher than the first level Vth1 ' by control circuit 304, such as 1.2 volts,
And voltage Vb is set in low level, such as 0.1,0.3 or 0.5 volt.Under this bias condition, selector 314 is opened, and
Memory cell 312 is read.Control circuit 304 can judge whether memory cell 312 is according to the size of sensing electric current
The high resistance of corresponding RESET state, such as 100K ohm.For example, once control circuit 304 detects sensing electric current
Size is about 1~5 microampere, then judges that memory cell 312 is successfully programmed to RESET state.Conversely, then judging memory list
Member 312 does not pass through programming operation.
In step 510, after judging memory cell 312 by programming operation, control circuit 304 will maintain to select
The threshold voltage of device 314 is in the first level Vth1 '.That is, when memory cell 312 is considered as healthy position, couples this and deposit
The selector 314 of storage unit 312 will be set at enabled status.
In step 512, after judging memory cell 312 not by programming operation, control circuit 304 is by selector
314 threshold voltage switches to second electrical level.That is, when memory cell 312 is considered as error bit, the memory is coupled
The selector 314 of unit 312 will be set at disabled state.
In one embodiment, control circuit 304 can execute hot carrier injection behaviour in the second end (source terminal) of transistor M1
Make, the threshold voltage of selector 314 is made to be promoted to second electrical level, such as 1.8 volts.
Fig. 6 C are please referred to, after entering disabled state, threshold voltage will be set at higher than wordline electricity selector 314
Press a second electrical level Vth2 ' of Vg.Even if therefore voltage Vg T3 (during programming operation) T4 between the fourth phase during third (are read
During operation) it is enable (such as 1.2 volts), transistor M1 is all remained off so that control circuit 304 can only detect very
Low sensing electric current, approximate number Naan (nA) to pico-ampere (pA).
Fig. 7 is painted the schematic diagram of the data mode of the memory cell 312 according to one embodiment of the invention.
Described in brought forward, control circuit 304 can judge the data mode of memory cell 312 according to sensing electric current.In this example
In, tool is there are two possible data mode S1 and S2 in the operation of memory cell 312, respectively a specific data value is presented
(such as 0 or 1).Once the selector 314 for coupling this memory cell 312 is closed, control circuit 304 is read with normal electrically condition
Take this memory cell 312 that can will only detect the sensing electric current of atomic weak (compared to the sensing electric current of corresponding data state),
And then pick out a disabled state S0.This disabled state S0 can't be considered as indicating the number of a particular data value
According to state.In other words, when a memory cell 312 is selected, the selector 314 for coupling this memory cell 312 can be by changing
Become its adjustable electrical parameter, to introduce the disabled state S0 of a unrelated storage data.At disabled state S0, memory
Unit 312 will be unable to access with normal electrically condition.
It is noted that although memory cell 312 only has two data modes S1 and S2 in Fig. 7, the present invention is simultaneously
It is not limited.In some embodiments, memory cell 312 may include more than two data mode, such as four possibility
Data mode.
In conclusion the memory device of present invention proposition includes memory cell and selector.Selector has can
It is configured to the adjustable electrical parameter of varying level.When the adjustable electrical parameter of selector is set at the first level, choosing
Device operation is selected in an enabled status.In the case, when memory cell is selected, selector will be opened so that memory list
Member can be programmed or read.On the other hand, when the adjustable electrical parameter of selector is set at second electrical level, selector will be grasped
Make in a disabled state.In the case, when memory cell is selected, selector will remain off so that memory list
Member can not be accessed.Using above-mentioned characteristic, control circuit can first be picked out from memory array can not successful program storage
Device unit, then will couple these can not the selector of memory cell of successful program be set to disabled state, to avoid mistake
Accidentally adverse effect of the position to storage device.In addition, once selector is in disabled state, memory device will be operated in pole
The condition of low-leakage current, therefore the influence of latent channel current (sneak path current) is can effectively avoid, and improve power and disappear
Consumption.
Although the present invention is disclosed as above with embodiment, however, it is not to limit the invention.Those skilled in the art exist
Do not depart from the spirit and scope of the present invention, when can various modifications may be made with addition.Therefore, protection scope of the present invention is when regarding accompanying
Subject to claims are defined.
Claims (10)
1. a kind of memory device, which is characterized in that including：
One memory cell, to store a data；And
One selector, couples the memory cell, and the selection utensil has can be configured to varying level one adjustable electrical ginseng
Number；
Wherein when the adjustable electrical parameter of the selection device is configured to one first level, the selection device responds a behaviour of enable
Make signal and open, to allow the data in the memory cell to be accessed；When the adjustable electrical parameter of the selection device
It is configured to a second electrical level, the selection device is remained off when receiving the operation signal of enable, to forbid the memory list
The data in member are accessed.
2. memory device according to claim 1, which is characterized in that the selection device includes a transistor, this is adjustable
Electrical parameter is a threshold voltage of the transistor, which has a control terminal of one wordline of coupling, couples the memory
One first end of unit and the second end for coupling a bias generator, the wordline is transmitting the operation signal；
Wherein when the threshold voltage of the transistor is configured to the second electrical level, which is closed, and not by the operation
Signal is opened；
When the threshold voltage of the transistor is configured to first level, which opens in response to the operation signal of enable
It opens, and is closed in response to the operation signal of disabled, which is above first level.
3. memory device according to claim 2, which is characterized in that the transistor is performed a hot carrier injection or not
Le-Nuo Deng penetrate operation so that the threshold voltage of the transistor is adjusted from first level to the second electrical level.
4. memory device according to claim 1, which is characterized in that when the memory cell is not grasped by a programming
Make, the adjustable electrical parameter of the selection device is set at the second electrical level.
5. a kind of storage system, which is characterized in that including：
One memory array, including multiple memory devices, respectively the memory device include：
One memory cell；And
One selector, is coupled to the memory cell, the selection utensil have can be configured to varying level one it is adjustable electrically
Parameter；And
One control circuit couples the memory array, to access these memory cells, and set these selectors these
Adjustable electrical parameter；
Wherein when the adjustable electrical parameter of the specific selector in these selectors is set at one first level, the spy
Determine selector to open in response to an operation signal of enable, to allow to couple the one of the specific selector in these memory cells
The data of particular memory cell are accessed；When the adjustable electrical parameter of the specific selector is set at one second electricity
Flat, which remains off when receiving the operation signal of enable, to forbid being somebody's turn to do in the particular memory cell
Data are accessed.
6. storage system according to claim 5, which is characterized in that the specific selector includes a transistor, this can
Mode electrical parameter is a threshold voltage of the transistor, which has a control terminal of one wordline of coupling, couples the spy
Determine one first end of memory cell and couple a second end of a bias generator, the wordline is transmitting the operation signal；
Wherein when the threshold voltage of the transistor is configured to the second electrical level, which is closed, and not by the operation
Signal is opened；
When the threshold voltage of the transistor is configured to first level, which opens in response to the operation signal of enable
It opens, and is closed in response to the operation signal of disabled, which is above first level.
7. storage system according to claim 6, which is characterized in that the control circuit is more to transistor execution
One hot carrier injection or a Fu Le-Nuo Deng penetrate operation, by the threshold voltage of the transistor from first level adjust to
The second electrical level.
8. storage system according to claim 5, which is characterized in that the control circuit more to：
These memory cells are read, to judge these memory cells whether by a programming operation；And
For, not by a first memory unit of the programming operation, being coupled in these selectors in these memory cells
The adjustable electrical parameter setting of one first selector of the first memory unit is in the second electrical level.
9. storage system according to claim 8, which is characterized in that the control circuit more to：
It, should by coupling in these selectors for the second memory unit by the programming operation in these memory cells
The adjustable electrical parameter setting of one second selector of second memory unit is in first level.
10. a kind of operating method of storage system, which is characterized in that the storage system includes a memory array, this is deposited
Memory array includes multiple memory devices, and respectively the memory device includes a memory cell and a selector, the selection
Device couples the memory cell, and has the adjustable electrical parameter that can be configured to varying level, which includes：
These memory cells are read, to judge these memory cells whether by a programming operation；
When judging the particular memory cell in these memory cells by the programming operation, by coupling in these selectors
The adjustable electrical parameter setting of a specific selector of the particular memory cell is connect in one first level, to control the spy
Determine selector to be opened when receiving an operation signal of enable, to allow the data in the particular memory cell to be deposited
It takes；And
When judging the particular memory cell not by the programming operation, by the adjustable electrical parameter of the specific selector
It is set in a second electrical level, is remained off with controlling the specific selector when receiving the operation signal of enable, to forbid this
The data in particular memory cell are accessed.
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