CN108733123B

CN108733123B - Power management unit for preventing overshoot in power-on process

Info

Publication number: CN108733123B
Application number: CN201810514726.5A
Authority: CN
Inventors: 杨运福
Original assignee: Huada Semiconductor Co Ltd
Current assignee: Xiaohua Semiconductor Co ltd
Priority date: 2018-05-25
Filing date: 2018-05-25
Publication date: 2020-03-31
Anticipated expiration: 2038-05-25
Also published as: CN108733123A

Abstract

The invention discloses a power management unit, comprising: a reference source that generates a reference voltage based on a system voltage; a delay unit that delays the reference voltage and generates a delayed reference voltage; and a low dropout regulator receiving the delayed reference voltage and generating an internal voltage VDD based on the delayed reference voltage, wherein the delayed reference voltage does not sample an initial overshoot portion of the reference voltage.

Description

Power management unit for preventing overshoot in power-on process

Technical Field

The invention relates to the technical field of power management, in particular to a power management unit for preventing overshoot in a power-on process.

Background

A Micro Control Unit (MCU), also called a single-chip microcomputer or a single-chip microcomputer, is a computer with a chip level formed by properly reducing the frequency and specification of a central processing Unit and integrating peripheral interfaces such as a memory, a counter and the like, even a power supply Unit, on a single chip, and is used for different combined control in different application occasions.

For a micro control Unit (mcu) chip, a power management Unit (PowerManagement Unit) is a basic component to meet the requirements of low power consumption system design and reliability design.

A typical power management unit includes a reference voltage source followed by a linear regulator. The linear voltage stabilizer increases the reference voltage VREF output by the reference voltage source by a certain multiple to generate a stable voltage VDD to supply power for the digital logic circuit. Meanwhile, the power management unit can monitor the power supply voltage (including the system voltage AVCC and the adjusted internal voltage VDD) and timely and correctly generate a reset signal to ensure the reliable and stable work of the MCU system.

However, the conventional power management unit cannot monitor the overshoot of the reference voltage during the power-on start-up process. During power-up start-up, when the reference voltage exceeds a desired stable value due to a start-up circuit or the like. This reference voltage is also followed by the next linear regulator to amplify, which may generate a voltage VDD exceeding the specification for supplying the digital logic. Since the VDD voltage exceeds the specification definition of the digital logic circuit, the characteristics of the digital logic circuit, such as the timing sequence, cannot be guaranteed, and thus the MCU cannot be guaranteed to be in a stable and reliable operating state. Even when the overshoot amplitude is large, the generated VDD voltage is higher than the breakdown voltage of the digital logic device, and a part of the digital logic circuit is directly broken down, so that the chip fails.

Therefore, there is a need in the art for a power management unit that prevents overshoot during power up.

Disclosure of Invention

The invention ensures that the generated VDD voltage does not have an overshoot process by carrying out time delay sampling on the reference voltage, and ensures that the digital logic circuit reliably and stably works.

According to an aspect of the present invention, there is provided a power management unit comprising:

a reference source that generates a reference voltage based on a system voltage;

a delay unit that delays the reference voltage and generates a delayed reference voltage; and

a low dropout linear regulator that receives the delayed reference voltage, generates an internal voltage VDD based on the delayed reference voltage,

wherein the delayed reference voltage does not sample an initial overshoot portion of the reference voltage.

In one embodiment of the invention, the delay unit comprises a switch, and the switch is used for conducting the reference source and the low dropout linear regulator; and after the initial overshoot part of the reference voltage is finished, the switch conducts the reference source and the low dropout linear regulator.

In an embodiment of the present invention, the delay unit implements the delay in an analog manner.

In one embodiment of the present invention, the delay unit includes:

a current source that generates a reference current based on a system voltage AVCC;

a capacitor in series with the current source;

a buffer, an input terminal of the buffer being connected to a connection node of the current source and the capacitor; and

the switch is connected between the reference source and the low dropout regulator in series, the switch is also provided with a control end for controlling the on and off of the switch, and the control end is connected with the output end of the buffer.

In one embodiment of the invention, the switch is a MOS transistor or a triode.

In an embodiment of the present invention, the power management unit further includes a system voltage power-on reset module, and the system voltage power-on reset module generates a system voltage power-on reset signal based on the system voltage AVCC.

In one embodiment of the present invention, the delay unit implements the delay digitally.

In one embodiment of the present invention, the delay unit includes:

the oscillator delays the system voltage power-on reset signal output by the system voltage power-on reset module to form a delayed power-on reset signal PORH _ P; and

the switch is connected between the reference source and the low dropout regulator in series, and the switch also has a control end for controlling the on and off of the switch, and the control end receives a delayed power-on reset signal PORH _ P.

In one embodiment of the invention, the switch is a MOS transistor or a triode.

In one embodiment of the present invention, the power management unit further includes an internal voltage power-on reset module that generates an internal voltage power-on reset signal based on the internal voltage VDD.

Compared with the prior art, the method and the device ensure that the generated VDD voltage does not have an overshoot process by carrying out time delay sampling on the reference voltage, and ensure that the digital logic circuit works reliably and stably.

Drawings

To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.

Fig. 1 shows a schematic diagram of a power management unit 100.

Fig. 2 illustrates a timing diagram 200 of the power management unit 100 shown in fig. 1.

Fig. 3 illustrates a power management unit 300 according to an embodiment of the invention.

Fig. 4 illustrates a timing diagram 400 of the power management unit 300 shown in fig. 3.

Fig. 5 shows a circuit schematic of a delay cell 500 according to an embodiment of the invention.

Fig. 6 shows a timing diagram of the devices in the delay cell 500 shown in fig. 5.

Fig. 7 shows a circuit schematic of a delay cell 700 according to another embodiment of the invention.

Fig. 8 illustrates a timing diagram of the devices in the delay cell 700 shown in fig. 7.

Detailed Description

In the following description, the invention is described with reference to various embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention may be practiced without specific details. Further, it should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

Reference in the specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

Fig. 1 shows a schematic diagram of a power management unit 100. As shown in fig. 1, the power management unit 100 includes a low power consumption reference source LPBGR 110 and a low dropout regulator LDO 120. LPBGR 110 generates reference voltage VREF based on system voltage AVCC. LDO 120 receives reference voltage VREF output by LPBGR 110, and increases reference voltage VREF by a certain multiple to generate a stable voltage VDD to power the digital logic circuit.

The power management unit 100 may further include a system voltage power-on reset module PORH 130 and an internal voltage power-on reset module PORL 140. PORH 130 generates a system voltage power-on reset signal based on system voltage AVCC. The internal voltage power-on reset block PORL 140 generates an internal voltage power-on reset signal based on the internal voltage VDD.

Fig. 2 illustrates a timing diagram 200 of the power management unit 100 shown in fig. 1. During power-up start-up of reference source LPBGR 110, reference voltage VREF overshoots due to a start-up circuit or the like, exceeds a desired stable value, and then falls back to a final stable value. The overshoot of the reference voltage VREF is also followed and amplified by the next LDO 120, which may generate a voltage VDD exceeding the specification to power the digital logic. Since the VDD voltage exceeds the specification definition of the digital logic circuit, the characteristics of the digital logic circuit, such as the timing sequence, cannot be guaranteed, and thus the MCU cannot be guaranteed to be in a stable and reliable operating state.

In order to solve the overshoot problem, the invention provides a power management unit, which ensures that a low dropout linear regulator (LDO) module cannot immediately follow a generated reference voltage VREF in the power-on process, and starts the low dropout linear regulator (LDO) after the reference voltage VREF falls back to a stable expected voltage, so that the generated VDD voltage does not have an overshoot process, and the reliable and stable work of a digital logic circuit is ensured.

Fig. 3 illustrates a power management unit 300 according to an embodiment of the invention. As shown in fig. 3, the power management unit 300 includes a reference source 310, a delay unit 320, and a low dropout regulator LDO 330. Reference source 310 generates a reference voltage VREF based on system voltage AVCC. The delay unit 320 delays the reference voltage VREF and generates a delayed reference voltage VREFD. The LDO 330 receives the delayed reference voltage VREFD, increases the delayed reference voltage VREFD by a certain multiple, and generates a stable voltage VDD to power the digital logic circuit.

The power management unit 300 may further include a system voltage power-on reset module PORH 340 and an internal voltage power-on reset module PORL 350. PORH 340 generates a system voltage power-on reset signal based on system voltage AVCC. The internal voltage power-on reset block PORL 350 generates an internal voltage power-on reset signal based on the internal voltage VDD.

In order to solve the problem of VDD overshoot caused by VREF overshoot during MCU startup, delay sampling is performed on VREF through the delay unit 320, so that VREFD is guaranteed not to sample the overshoot voltage of VREF, and VREFD completely samples the value of VREF until VREF is stable.

Fig. 4 illustrates a timing diagram 400 of the power management unit 300 shown in fig. 3. As can be seen from fig. 4, VREFD does not sample the overshoot voltage of VREF, and therefore, the internal voltage VDD does not overshoot and is always within the specification range of the digital logic circuit.

Fig. 5 shows a circuit schematic of a delay cell 500 according to an embodiment of the invention. The delay unit 500 shown in fig. 5 implements the delay in an analog manner. As shown in fig. 5, the delay unit 500 includes a current source 510, a capacitor 520 connected in series with the current source, a buffer 530, and a switch 540. An input terminal of the buffer 530 is connected to a connection node a of the current source 510 and the capacitor 520. The output of the buffer 530 is connected to the control terminal of the switch 540. The switch 540 is connected between the reference source and the LDO for turning on the reference source and the LDO. The switch 540 may be a MOS transistor having a gate as a control terminal connected to the output terminal of the buffer 530, and a source and a drain connected to the reference voltage VREF and the delayed reference voltage VREFD, respectively. Alternatively, the switch 540 may be a transistor, the base of which is the control terminal and is connected to the output terminal of the buffer 530, and the collector and the emitter of which are respectively connected to the reference voltage VREF and the delayed reference voltage VREFD. It should be understood by those skilled in the art that the above only provides a few examples of the switch 540, and not a limitation of the switch 540, and any switching device capable of controlled on and off should fall within the scope of the present invention.

Delay unit 500 uses current source 510 to charge capacitor 520 to achieve the delay. The current source 510 generates a reference current based on the system voltage AVCC, and when the AVCC is not powered on, the current source has no current, i.e. its current magnitude is 0; when the AVCC starts to power up, when the potential of the connection node a is lower than a certain threshold voltage, the output BA through the buffer 530 is low, the switch 540 is in an off (non-conductive) state, at this time, the reference voltage VREF is in an overshoot state, and slowly falls back, the current source 510 starts to slowly stabilize to its final value, the potential of the connection node a gradually rises, when the potential of the connection node a is charged to be higher than a certain threshold voltage, the output BA through the buffer 530 is high, and the switch 540 becomes a closed state. The charging time of the capacitor 520 is sufficient to take into account the process of the entire current source 510 from scratch, and by properly setting the values of the current source 510 and the capacitor 520, sufficient redundancy can be reserved for the system to ensure that the switch does not turn on before the overshoot ends. Therefore, by properly setting the values of the current source 510 and the capacitor 520, it is ensured that the time for the potential of the connection node a to rise to a certain threshold value is equal to or longer than the time required for VREF to fall back to a stable value, and when the switch 540 is turned to a closed state, VREF has fallen back to a stable value, and VREFD follows VREF, avoiding the overshoot process of VREF. Based on the above description, a person skilled in the art can set the parameter values of the current source 510 and the capacitor 520 to ensure that the overshoot process of VREF is avoided, and the selection of the specific parameter values of the current source 510 and the capacitor 520 is not described in detail.

Fig. 6 shows a timing diagram of the devices in the delay cell 500 shown in fig. 5. As can be seen from fig. 6, during the overshoot of VREF, the output BA of the buffer 530 is low, and VREFD does not sample the overshoot voltage of VREF, so the internal voltage VDD does not overshoot and is always within the specification range of the digital logic circuit.

Fig. 7 shows a circuit schematic of a delay cell 700 according to another embodiment of the invention. The delay unit 700 shown in fig. 7 implements the delay digitally. As shown in fig. 7, the delay unit 700 includes an oscillator OSC 710, a switch 730, and a count delay 740. The count delay 740 counts the rising edge of the oscillator signal output from the oscillator OSC 710, and when the count delay 740 reaches a predetermined value, the system voltage power-on reset signal output from the system voltage power-on reset module PORH 340 is allowed to pass through, forming a delayed power-on reset signal PORH _ P. The control terminal of the switch 730 is connected to the delayed power-on reset signal. The switch 730 is connected between the reference source and the low dropout regulator for switching on the reference source and the low dropout regulator.

The switch 730 may be a MOS transistor having a gate as a control terminal and controlled by the delayed power-on reset signal PORH _ P, and a source and a drain connected to the reference voltage VREF and the delayed reference voltage VREFD, respectively. Alternatively, the switch 730 may be a transistor, the base of which is the control terminal and is controlled by the delayed power-on reset signal PORH _ P, and the collector and the emitter of which are respectively connected to the reference voltage VREF and the delayed reference voltage VREFD. It should be understood by those skilled in the art that the above examples of only switch 730 are given and not limiting to switch 540, and any switching device capable of controlled turn-on and turn-off should fall within the scope of the present invention.

An internal independent dedicated oscillator OSC 710 and a count delay 740 are used to implement a delay of the reset signal PORH of the high voltage AVCC for a period of time. When the AVCC is stabilized, the system can generate a PORH signal, but VREF is still in an overshoot process and is not stabilized; the PORH is delayed for a period of time by using the independent oscillator OSC 710 and the counting delay 740, the delay time of the counting delay 740 can be controlled by setting the period of the oscillation signal output by the oscillator OSC 710 and the counting value of the counting delay 740, so that the delay time is more than or equal to the time required by VREF to fall back to a stable value, when the PORH _ P signal is at a high level, VREF is in a stable state, the switch 730 is switched on, and VREFD follows VREF. According to the above description, a person skilled in the art can set the period of the oscillation signal output by the oscillator OSC 710 and the count value of the count delay 740 to ensure that the overshoot process of the VREF is avoided, and the setting of the period of the oscillation signal output by the oscillator OSC 710 and the count value of the count delay 740 is not described in detail.

Fig. 8 illustrates a timing diagram of the devices in the delay cell 700 shown in fig. 7. As can be seen from fig. 8, during the overshoot of VREF, the delayed power-on reset signal PORH _ P is low, the switch 730 is turned off, VREFD does not sample the overshoot voltage of VREF, and therefore, the internal voltage VDD does not overshoot and is always within the specification range of the digital logic circuit.

While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various combinations, modifications, and changes can be made thereto without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A power management unit to prevent overshoot during power up, comprising:

wherein the delayed reference voltage does not sample an initial overshoot portion of the reference voltage,

the delay unit includes: a current source that generates a reference current based on a system voltage AVCC; a capacitor in series with the current source; a buffer, an input terminal of the buffer being connected to a connection node of the current source and the capacitor; and the switch is connected in series between the reference source and the low dropout regulator, and is also provided with a control end for controlling the on and off of the switch, and the control end is connected with the output end of the buffer.

2. The power management unit for preventing overshoot during power up of claim 1, wherein the delay unit comprises a switch for turning on the reference source and the low dropout linear regulator; and after the initial overshoot part of the reference voltage is finished, the switch conducts the reference source and the low dropout linear regulator.

3. The power management unit for preventing overshoot during power up as in claim 1, wherein the delay unit implements delay in an analog manner.

4. The power management unit for preventing overshoot during power up of claim 1, wherein the switch is a MOS transistor or a triode.

5. The power management unit for preventing overshoot during power-on of claim 1, further comprising a system voltage power-on reset module that generates a system voltage power-on reset signal based on a system voltage AVCC.

6. A power management unit to prevent overshoot during power up, comprising:

wherein the delay unit includes: the oscillator delays the system voltage power-on reset signal output by the system voltage power-on reset module to form a delayed power-on reset signal PORH _ P; and the switch is connected between the reference source and the low dropout regulator in series, and is also provided with a control end for controlling the on and off of the switch, and the control end receives a delayed power-on reset signal PORH _ P.

7. The power management unit for preventing overshoot during power up as in claim 6, wherein the delay unit implements the delay digitally.

8. The power management unit for preventing overshoot during power up of claim 6, wherein the switch is a MOS transistor or a triode.

9. The power management unit for preventing overshoot during power-on as claimed in claim 6, further comprising an internal voltage power-on reset module that generates an internal voltage power-on reset signal based on an internal voltage VDD.