CN108717947A - Transistor structure of semiconductor memory and manufacturing method - Google Patents
Transistor structure of semiconductor memory and manufacturing method Download PDFInfo
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- CN108717947A CN108717947A CN201810895215.2A CN201810895215A CN108717947A CN 108717947 A CN108717947 A CN 108717947A CN 201810895215 A CN201810895215 A CN 201810895215A CN 108717947 A CN108717947 A CN 108717947A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
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- 239000000758 substrate Substances 0.000 claims abstract description 42
- 230000002262 irrigation Effects 0.000 claims description 136
- 238000003973 irrigation Methods 0.000 claims description 136
- 238000005452 bending Methods 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 12
- 230000004888 barrier function Effects 0.000 claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 238000005253 cladding Methods 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 5
- 230000005540 biological transmission Effects 0.000 abstract description 6
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 230000005669 field effect Effects 0.000 description 8
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- 238000005516 engineering process Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a transistor structure of a semiconductor memory and a manufacturing method thereof, wherein the structure comprises: the semiconductor substrate is provided with an active area and a channel insulation structure, the active area is provided with a first contact area and a second contact area, the semiconductor substrate is provided with a groove penetrating through the active area and the channel insulation structure in the preset column direction, the groove is provided with a first depth in the active area section and a second depth in the channel insulation structure section, and the first depth is different from the second depth and does not exceed the depth of the channel insulation structure; the trench conducting wire is embedded in the trench, the trench comprises a micro trench structure located at the bottom of the active area section, the micro trench structure comprises a trench which is recessed relative to the bottom of the active area section, the cross section of the re-recessed trench parallel to the length extension direction of the trench is bent and extended, the trench conducting wire is filled into the re-recessed trench to form a micro fin portion grid electrode structure, and the micro fin portion grid electrode structure is integrally connected with the main body of the trench conducting wire. The invention can increase the width of the transmission channel and improve the performance of the device.
Description
Technical field
The present invention relates to technical field of integrated circuits, more particularly to the transistor arrangement and system of a kind of semiconductor memory
Make method.
Background technology
With the continuous diminution of device feature size, the problems such as short-channel effect, subthreshold current are big and grid leak is electric, makes biography
The plane type field effect transistor structure of system has been difficult to meet the needs of to device performance.Multi-panel gate semiconductor device is as normal
The replacement of rule planar device is widely used.
Fin formula field effect transistor (Fin FET) is a kind of typical multi-panel gate semiconductor device, is generally included three-dimensionally
The one or more fins being set on substrate are equipped with isolation structure between each fin, and gate structure is across on fin, cover
The top surface of one section of fin and side wall, source electrode and drain electrode are located in the fin that gate structure both sides are not covered by gate structure,
The one section of fin covered by gate structure is channel region.This three-dimensional transistor arrangement increases gate structure and ditch
The contact area in road region, the top surface and side wall that gate structure is in contact with fin all become raceway groove, this, which is conducive to increase, drives
Streaming current improves device performance.
Patent publication No. is that a patent document of CN104733312A discloses a kind of shape of fin formula field effect transistor
At method, the forming method includes：Semiconductor substrate is provided, the semiconductor substrate has NMOS area and PMOS area,
It is formed with the first fin in PMOS area, the second fin is formed in NMOS area；First medium is formed on a semiconductor substrate
Layer, the surface of the first medium layer are less than the top surface of the first fin and the second fin；It is formed in first medium layer surface
Across the gate structure of first fin and the second fin；Removal is located at the first fin of gate structure both sides, in the areas PMOS
The first groove is formed on domain；The first semiconductor layer is deposited in first groove, makes the surface of the first semiconductor layer higher than the
One dielectric layer surface；Second dielectric layer is formed on the first medium layer using mobility chemical vapor deposition method；Removal
Part second dielectric layer at the top of second fin, exposes the surface of the second fin；The second half are formed in the second fin portion surface to lead
Body layer.
However, further reducing with device size, the device performance of existing fin formula field effect transistor is difficult to meet
How higher requirement improves transistor arrangement and further increases the technical barrier that device performance is still urgently to be resolved hurrily at present.
Invention content
In view of prior art described above, the purpose of the present invention is to provide a kind of transistor arrangements of semiconductor memory
And production method, the device performance for improving field-effect transistor in memory.
In order to achieve the above objects and other related objects, the present invention provides a kind of transistor arrangement of semiconductor memory,
Including：
Semiconductor substrate, the trench insulation structure with a plurality of active areas and the isolation active area, each active area
With the first contact zone (being specially located at the bit line contact area among the active area) and the on the semiconductor substrate
Two contact zones (the capacitance contact contact zone for being specially located at the active area both ends), the semiconductor substrate is in predetermined column direction
The active area being applied on predetermined column direction equipped with a plurality of grooves and the trench insulation structure, to have described in separation
First contact zone of source region and second contact zone, wherein the groove is deep with first in the section of the active area
Degree, the groove in the section of the trench insulation structure there is the second depth, first depth to differ in described second
Depth and the third depth for being no more than the trench insulation structure；And
A plurality of slot wires (being specially wordline), are embedded in the groove, wherein the groove further includes being located at institute
State micro- trench architectures of the section bottom of active area, micro- trench architectures include relative to the active area section bottom again
Recessed irrigation canals and ditches recessed again, the irrigation canals and ditches recessed again are that bending extends in the section for being parallel to the trench length extending direction,
The slot wire more inserts the irrigation canals and ditches recessed again of micro- trench architectures, to be formed towards inside the semiconductor substrate
Micro- fin gate structure, and micro- fin gate structure is integrated with the main body of the slot wire and connect.
Optionally, micro- trench architectures include a plurality of side by side recessed again for being parallel to the trench length extending direction
Enter irrigation canals and ditches, and the direction of the irrigation canals and ditches recessed again is identical.
Optionally, the irrigation canals and ditches recessed again are in the case where the cross sectional shape for being parallel to the trench length extending direction includes centre
Recessed arc-shaped bend.
Optionally, the irrigation canals and ditches recessed again include that V-arrangement is curved in the cross sectional shape for being parallel to the trench length extending direction
It is bent.
Optionally, the irrigation canals and ditches recessed again include inverted V-shaped being parallel to the cross sectional shape of the trench length extending direction
Bending.
Optionally, the depth capacity of the irrigation canals and ditches recessed again is not more than the depth of second depth and first depth
The ratio of difference, the width of the maximum widths of the irrigation canals and ditches recessed again relative to the groove is not less than 0.1.
Optionally, the depth capacity of the irrigation canals and ditches recessed again is between 2nm~20nm, the maximum of the irrigation canals and ditches recessed again
Width is between 1nm~10nm.
Optionally, the section bottom of the active area is etching rough surface relative to the side wall of the groove.
Optionally, the slot wire surface is covered with insulating layer, the slot wire and micro- fin gate structure
Gate electrode layer including gate dielectric layer and on the gate dielectric layer, the irrigation canals and ditches recessed again of micro- trench architectures are most
Big depth and maximum width are all more than the cladding thickness for forming thickness and being less than the insulating layer of the gate dielectric layer.
Optionally, second depth is more than first depth, exhausted in the irrigation canals and ditches for increasing the slot wire
Structural strength in edge structure.
In order to achieve the above objects and other related objects, the present invention also provides a kind of transistor arrangements of semiconductor memory
Production method, include the following steps：
Semi-conductive substrate is provided, and forms a plurality of active areas in the semiconductor substrate surface and is isolated described active
The trench insulation structure in area, each active area have the first contact zone and the second contact zone on the semiconductor substrate；
A plurality of grooves are formed in predetermined column direction on the semiconductor substrate, are applied in described on predetermined column direction
Active area and the trench insulation structure, with first contact zone for detaching the active area and second contact zone,
Described in groove there is the first depth in the section of the active area, the groove has in the section of the trench insulation structure
Second depth, first depth differ in second depth and are no more than the third depth of the trench insulation structure,
And include during forming the groove：The recessed groove again, it further includes being located at the active area to make the groove
Section bottom micro- trench architectures, micro- trench architectures include relative to the active area section bottom again it is recessed again
Recessed irrigation canals and ditches, the irrigation canals and ditches recessed again are that bending extends in the section for being parallel to the trench length extending direction；And
A plurality of slot wires are formed, are embedded in the groove, the slot wire more inserts micro- trench architectures
The irrigation canals and ditches recessed again, to be formed towards micro- fin gate structure inside the semiconductor substrate, and micro- fin
Gate structure is integrated with the main body of the slot wire and connect.
Optionally, micro- trench architectures include a plurality of side by side recessed again for being parallel to the trench length extending direction
Enter irrigation canals and ditches, and the direction of the irrigation canals and ditches recessed again is identical.
Optionally, the irrigation canals and ditches recessed again are in the case where the cross sectional shape for being parallel to the trench length extending direction includes centre
Recessed arc-shaped bend.
Optionally, the irrigation canals and ditches recessed again include that V-arrangement is curved in the cross sectional shape for being parallel to the trench length extending direction
It is bent.
Optionally, the irrigation canals and ditches recessed again include inverted V-shaped being parallel to the cross sectional shape of the trench length extending direction
Bending.
Optionally, the depth capacity of the irrigation canals and ditches recessed again is not more than the depth of second depth and first depth
The ratio of difference, the width of the maximum widths of the irrigation canals and ditches recessed again relative to the groove is not less than 0.1.
Optionally, the depth capacity of the irrigation canals and ditches recessed again is between 2nm~20nm, the maximum of the irrigation canals and ditches recessed again
Width is between 1nm~10nm.
Optionally, the section bottom of the active area is etching rough surface relative to the side wall of the groove.
Optionally, hard mask layer is formed on the active area, and graphical photoresist is then formed on the hard mask layer
Layer is to define the groove in the section position of the active area, and etching is described to be formed downwards along the graphical photoresist layer
Section of the groove in the active area.
Optionally, micro- irrigation canals and ditches knot is formed in the section bottom of the active area using dry etching or wet etching
Structure.
Optionally, first retain the trench insulation structure, after forming micro- trench architectures, then remove the groove in institute
The section of trench insulation structure is stated to form the complete groove.
Optionally, formed micro- trench architectures when, first etch the groove the section of the active area side wall,
Etching barrier layer is formed in the trench insulation structure of the side wall and the adjacent side wall again, exposes the groove in institute
The bottom of the section of active area is stated, then bottom described in etching processing, forms micro- trench architectures, then remove the etching
Barrier layer.
Optionally, the groove is first removed in the section of the trench insulation structure, re-forms micro- trench architectures.
Optionally, insulating layer is formed on the slot wire surface, and is forming the slot wire and micro- fin
When gate structure, be initially formed gate dielectric layer, then gate electrode layer is formed on the gate dielectric layer, micro- trench architectures it is described
The depth capacity of recessed irrigation canals and ditches and maximum width are all more than forming thickness and being less than the insulating layer for the gate dielectric layer again
Cladding thickness.
Optionally, second depth is more than first depth, exhausted in the irrigation canals and ditches for increasing the slot wire
Structural strength in edge structure.
As described above, the transistor arrangement and production method of the semiconductor memory of the present invention, have the advantages that：
The transistor arrangement and production method of the semiconductor memory of the present invention, by making special micro- ditch in active area
Canal structure makes channel area be increased on the basis of keeping original device size, can further increase the width of transmission channel
Degree, to be greatly improved the device performance of field-effect transistor.
Description of the drawings
Fig. 1 a-1c are shown as a kind of transistor arrangement schematic diagram of semiconductor memory provided by the invention, wherein Fig. 1 a
For schematic top plan view, Fig. 1 b and Fig. 1 c are respectively the schematic cross-section of cross-wise direction A and cross-wise direction B shown on Fig. 1 a.
The production method that Fig. 2 a-2m are shown as the transistor arrangement of the semiconductor memory of the offer of the embodiment of the present invention one is shown
It is intended to.
The production method that Fig. 3 a-3d are shown as the transistor arrangement of semiconductor memory provided by Embodiment 2 of the present invention is shown
It is intended to.
The production method that Fig. 4 a-4d are shown as the transistor arrangement of the semiconductor memory of the offer of the embodiment of the present invention three is shown
It is intended to.
The production method that Fig. 5 a-5d are shown as the transistor arrangement of the semiconductor memory of the offer of the embodiment of the present invention four is shown
It is intended to.
The production method that Fig. 6 a-6d are shown as the transistor arrangement of the semiconductor memory of the offer of the embodiment of the present invention five is shown
It is intended to.
The production method that Fig. 7 a-7d are shown as the transistor arrangement of the semiconductor memory of the offer of the embodiment of the present invention six is shown
It is intended to.
The production method that Fig. 8 a-8d are shown as the transistor arrangement of the semiconductor memory of the offer of the embodiment of the present invention seven is shown
It is intended to.
Component label instructions
100 active areas
101 first contact zones
102 second contact zones
200 trench insulation structures
300 grooves
301 micro- trench architectures
3011 recessed irrigation canals and ditches again
401 hard mask layers
402 graphical photoresist layers
501 etching barrier layers
600 micro- fin gate structures
601 gate dielectric layers
602 gate electrode layers
603 insulating layers
Specific implementation mode
Illustrate that embodiments of the present invention, those skilled in the art can be by this specification below by way of specific specific example
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.It should be noted that in the absence of conflict, following embodiment and implementation
Feature in example can be combined with each other.
It should be noted that the diagram provided in following embodiment only illustrates the basic structure of the present invention in a schematic way
Think, component count, shape and size when only display is with related component in the present invention rather than according to actual implementation in schema then
Draw, when actual implementation kenel, quantity and the ratio of each component can be a kind of random change, and its assembly layout kenel
It is likely more complexity.
In order to improve the device performance of field-effect transistor, the present invention provides a kind of transistor junction of semiconductor memory
Structure please refers to Fig.1 a-1c, wherein Fig. 1 a be schematic top plan view, Fig. 1 b and Fig. 1 c be respectively cross-wise direction A shown on Fig. 1 a and
The schematic cross-section of cross-wise direction B, the device architecture include：Semiconductor substrate has described in a plurality of active areas 100 and isolation
The trench insulation structure 200 of active area, each active area 100 have 101 (tool of the first contact zone on the semiconductor substrate
Body is the bit line contact area among the active area 100) (specially it is located at the active area 100 with the second contact zone 102
The capacitance contact contact zone at both ends), the semiconductor substrate forms a plurality of grooves 300 in predetermined column direction, is applied in predetermined
The active area 100 on column direction and the trench insulation structure 200, connect with detach the active area 100 described first
Area 101 and second contact zone 102 are touched, wherein the groove 300 has the first depth in the section of the active area 100
D1, the groove 300 in the section of the trench insulation structure 200 there is the second depth d2, the first depth d1 to differ
In the second depth d2 and no more than the third depth d3 of the trench insulation structure 200；And a plurality of slot wires are (specifically
For wordline), it is embedded in the groove 300, wherein the groove 300 further includes positioned at the section bottom of the active area 100
Micro- trench architectures 301, micro- trench architectures 301 include relative to the active area section bottom it is recessed recessed again again
Irrigation canals and ditches 3011, the recessed irrigation canals and ditches 3011 again are that bending extends in the section for being parallel to the trench length extending direction, described
Slot wire more inserts the recessed irrigation canals and ditches 3011 again of micro- trench architectures 301, to be formed towards the semiconductor substrate
Internal micro- fin gate structure 600, and micro- fin gate structure 600 and the main body of the slot wire are integrated company
It connects.It should be noted that signified predetermined column direction is cross-wise direction B shown in Fig. 1 a herein.It is especially noted that institute
It is cross-wise direction B shown in Fig. 1 a, the follow-up groove width extending direction to state trench length extending direction in the present embodiment
It is cross-wise direction A shown in Fig. 1 a in the present embodiment.
As illustrated in figure 1 c, in some embodiments of the invention, the recessed irrigation canals and ditches 3011 again are being parallel to the groove
The cross sectional shape of length extending direction includes intermediate recessed arc-shaped bend, v-shaped bending or inverted V-shaped bending, increases electricity to realize
The channel area of sub- transmission channel width and the transistor arrangement.As shown in Figure 1 b, in some embodiments of the invention, institute
A plurality of again recessed irrigation canals and ditches 3011 side by side of the micro- trench architectures 301 including being parallel to the trench length extending direction are stated, and
The recessed irrigation canals and ditches 3011 again are towards identical, to further increase the raceway groove face of electron propagation ducts width and the transistor
Product.In some embodiments of the invention, the section bottom of the active area is that etching is coarse relative to the side wall of the groove
Face.Wherein, the groove 300 has in the section of the active area 100 the first depth d1, the groove 300 are in the ditch
The third depth d3 of the second depth d2 and the trench insulation structure 200 that the section of canal insulation system 200 has such as scheme
Shown in 1b.It should be noted that Fig. 1 b, Fig. 1 c depict only in the embodiment of the present invention a kind of possible situation to schematically illustrate.
In some embodiments of the invention, the second depth d2 is more than the first depth d1, for increasing the slot wire
Structural strength in the trench insulation structure.In other embodiments of the present invention, the first depth d1 is more than institute
The second depth d2 is stated, for increasing main body and the micro- fin gate structure of the active area along the crosscutting slot wire
Channel length.In some embodiments of the invention, the depth capacity of the recessed irrigation canals and ditches 3011 again is not more than described second
The depth difference of depth d2 and the first depth d1, and the maximum width of the recessed irrigation canals and ditches 3011 again is relative to the groove
The ratio of 300 width is not less than 0.1；Preferably, the depth capacity of the recessed irrigation canals and ditches 3011 again is less than second depth
The depth difference of d2 and the first depth d1.In other embodiments of the present invention, the maximum of the recessed irrigation canals and ditches 3011 again
Depth is not more than the depth difference of the first depth d1 and the second depth d2, and the maximum of the recessed irrigation canals and ditches 3011 again is wide
The ratio for spending the width relative to the groove 300 is not less than 0.1；Preferably, the depth capacity of the recessed irrigation canals and ditches 3011 again
Less than the depth difference of the first depth d1 and the second depth d2.By considering the recessed irrigation canals and ditches 3011 again most
Big depth and maximum width so that the depth of the recessed irrigation canals and ditches 3011 again is neither too deep only shallow, the irrigation canals and ditches recessed again
3011 width is neither wide only narrow；Not only avoid again that recessed irrigation canals and ditches are excessively shallow, wide can not be effectively increased channel area
The problem of, while it is too deep, narrow so that the slot wire being subsequently formed can not be filled up completely to also avoid again recessed irrigation canals and ditches
The bottom of the irrigation canals and ditches recessed again so that the problem of bottom of the irrigation canals and ditches recessed again gap occurs, influences device performance.Wherein
Between 2nm~20nm, the maximum width of the recessed irrigation canals and ditches 3031 again is situated between the depth capacity of the recessed irrigation canals and ditches 3011 again
Between 1nm~10nm.
Specifically, the semiconductor substrate, usually Si sills.The ditch being arranged between multiple active areas 100
Canal insulation system can be fleet plough groove isolation structure (STI).
Specifically, the slot wire includes the grid contacted with the active area 100 with micro- fin gate structure 600
Dielectric layer 601 and the gate electrode layer 602 on the gate dielectric layer 601.It can be covered on 602 surface of the gate electrode layer
Insulating layer 603.The depth capacity and maximum width of the irrigation canals and ditches recessed again of micro- trench architectures 301 are all more than the grid and are situated between
Matter layer 601 forms thickness and the cladding thickness less than the insulating layer 603, for avoiding the gap of micro- trench architectures complete
It is filled up entirely by the gate dielectric layer, while current characteristics is adjusted.The media material such as silica may be used in gate dielectric layer 601
The insulating materials such as silicon nitride may be used in material, insulating layer 603, and gate electrode layer 602 can be metal or other suitable electrode materials
Material.
In addition, source electrode and drain electrode can be arranged in semiconductor active region 100.About fin FET device
Structure, material, manufacture craft, the principle of the parts such as source electrode, drain electrode, drift region have been that those skilled in the art are known, therefore herein
It does not repeat, any suitable structure, material may be used in the part such as source electrode, drain electrode, drift region in device architecture of the present invention
And manufacture craft, the invention is not limited in this regard.
Illustrate the production method of the transistor arrangement of semiconductor memory provided by the invention in detail further below.
This method comprises the following steps：
Semi-conductive substrate is provided, and is formed described in a plurality of active areas 100 and isolation in the semiconductor substrate surface
The trench insulation structure 200 of active area 100, each active area 100 have the first contact zone 101 on the semiconductor substrate
With the second contact zone 102；
A plurality of grooves 300 are formed in predetermined column direction on the semiconductor substrate, are applied on predetermined column direction
The active area 100 and the trench insulation structure 200, to detach first contact zone 101 and the institute of the active area 100
The second contact zone 102 is stated, wherein the groove 300 has the first depth d1, the groove in the section of the active area 100
300 in the section of the trench insulation structure 200, that there is the second depth d2, the first depth d1 to differ is deep in described second
D2 and the third depth d3 no more than the trench insulation structure 200 are spent, and is wrapped during forming groove 300
It includes：The recessed groove 300 again, it further includes micro- trench architectures positioned at the section bottom of the active area to make the groove 300
301, micro- trench architectures 301 include the section bottom recessed irrigation canals and ditches 3011 recessed again again relative to the active area, institute
It is that bending extends that recessed irrigation canals and ditches 3011, which are stated again, in the section for being parallel to the trench length extending direction；And
A plurality of slot wires are formed, are embedded in the groove 300, the slot wire more inserts micro- irrigation canals and ditches knot
The recessed irrigation canals and ditches 3011 again of structure 301, to be formed towards micro- fin gate structure 600 inside the semiconductor substrate, and
And micro- fin gate structure 600 is integrated with the main body of the slot wire and connect.
Wherein, the recessed irrigation canals and ditches 3011 again include centre in the cross sectional shape for being parallel to the trench length extending direction
Recessed arc-shaped bend, v-shaped bending or inverted V-shaped bending, increases electron propagation ducts width and the transistor arrangement to realize
Channel area.In some embodiments of the invention, micro- trench architectures 301 further include being parallel to the trench length to prolong
A plurality of irrigation canals and ditches 3011 recessed again side by side in direction are stretched, and the recessed irrigation canals and ditches 3011 again are towards identical, to further increase
The channel area of electron propagation ducts width and the transistor.The section bottom of the active area 100 is relative to the groove
300 side wall is etching rough surface.
In some embodiments of the invention, the second depth d2 is more than the first depth d1, described for increasing
Structural strength of the slot wire in the trench insulation structure.In other embodiments of the present invention, first depth
D1 is more than the second depth d2, for increasing main body and the micro- fin of the active area along the crosscutting slot wire
The channel length of gate structure.
In some embodiments of the invention, the depth capacity of the recessed irrigation canals and ditches 3011 again is not more than second depth
The depth difference of d2 and the first depth d1, and the maximum width of the recessed irrigation canals and ditches 3011 again is relative to the groove 300
The ratio of width is not less than 0.1；Preferably, the depth capacity of the recessed irrigation canals and ditches 3011 again is less than the second depth d2 and institute
State the depth difference of the first depth d1.In other embodiments of the present invention, the depth capacity of the recessed irrigation canals and ditches 3011 again is not
More than the depth difference of the first depth d1 and the second depth d2, and the maximum width of the recessed irrigation canals and ditches 3011 again is opposite
It is not less than 0.1 in the ratio of the width of the groove 300；Preferably, the depth capacity of the recessed irrigation canals and ditches 3011 again is less than institute
State the depth difference of the first depth d1 and the second depth d2.By the depth capacity for considering the recessed irrigation canals and ditches 3011 again
And maximum width so that the depth of the recessed irrigation canals and ditches 3011 again is neither too deep only shallow, the recessed irrigation canals and ditches 3011 again
Width is neither wide only narrow；Not only avoid again that recessed irrigation canals and ditches are excessively shallow, wide the problem of can not being effectively increased channel area,
It is too deep, narrow so that the slot wire being subsequently formed can not be filled up completely the irrigation canals and ditches to also avoid again recessed irrigation canals and ditches simultaneously
Bottom so that the problem of there is gap, influences device performance in the bottom of the irrigation canals and ditches recessed again.The wherein described irrigation canals and ditches recessed again
3011 depth capacity between 2nm~20nm, the maximum widths of the recessed irrigation canals and ditches 3011 again between 1nm~10nm it
Between.
Specifically, hard mask layer 401 can be formed on the active area 100, then the shape on the hard mask layer 401
At graphical photoresist layer 402 with define the groove 300 the active area 100 section position, and along the graphical light
Resistance layer 402 downwards etching with formed the groove 300 the active area 100 section.In order to form special bottom structure,
I.e. micro- trench architectures 301, may be used dry etching or wet etching, by controlling the means such as etch period, etching condition, shape
At micro- trench architectures 301.
It should be noted that the present invention does not limit the design parameter range of dry etching and wet etching and implements item
Part etches the groove 300 described in the section of the active area 100, processing bottom, formation according to the needs of practical application
Micro- trench architectures 301 may be used dry etching, wet etching or other suitable methods, and condition and parameter is embodied can be with
It is selected and is adjusted according to actual conditions.
Specifically, the trench insulation knot of the groove 300 around the section of the active area 100 can first be retained
Structure 200, after forming micro- trench architectures 301, then remove the groove 300 the trench insulation structure 200 section with
Form the complete groove 300.The groove is segmented to be formed, and is formed simultaneously in the section bottom of the active area described micro-
Trench architectures to control the different depth of each section groove, while accurately controlling the irrigation canals and ditches recessed again and being formed only in and described have
The section bottom of source region, and it is not formed at the section of the trench insulation structure.In some embodiments of the invention, institute is formed
When stating micro- trench architectures 301, can first etch the groove 300 the section of the active area 100 side wall, then described
Etching barrier layer 501 is formed in the trench insulation structure 200 of side wall and the adjacent side wall, exposes the groove 300 and exists
The bottom of the section of the active area 100, then bottom described in etching processing, forms micro- trench architectures 301, then removes
The etching barrier layer 501 is etching rough surface to reach the section bottom of the active area relative to the side wall of the groove
Effect.In other embodiments of the present invention, micro- trench architectures 301 can be formed with direct etching.Alternatively, can be first
The groove 300 is removed in the section of the trench insulation structure 200, then etches and to form micro- trench architectures 301.
In addition, when forming the slot wire with micro- fin gate structure 600, gate dielectric layer can be initially formed
601, then gate electrode layer 602 is formed on the gate dielectric layer 601.Insulating layer can be formed on 602 surface of the gate electrode layer
603.The depth capacity and maximum width of the irrigation canals and ditches recessed again of micro- trench architectures are all more than the gate dielectric layer 601
Thickness and the cladding thickness less than the insulating layer 603 are formed, for avoiding the gap of micro- trench architectures completely described
Gate dielectric layer fills up, while being adjusted to current characteristics.
Embodiment one
First, (Fig. 2 a are vertical view, and Fig. 2 b are active area direction A sectional views, and Fig. 2 c are predetermined as shown in Fig. 2 a, 2b, 2c
Column direction B-section figure), semi-conductive substrate is provided, and the semiconductor substrate surface formed a plurality of active areas 100 and every
Trench insulation structure 200 from the active area 100.
Then, as shown in Fig. 2 d and 2e (Fig. 2 d are active area direction A sectional views, and Fig. 2 e are predetermined column direction B-section figure)
Hard mask layer 401 is formed, forms graphical photoresist layer 402 on the hard mask layer 401 to define the groove 300 described
The section position of active area 100 is etched to form the groove 300 described active downwards along the graphical photoresist layer 402
The section in area 100.It is exhausted that this step can first retain the irrigation canals and ditches of the groove 300 around the section of the active area 100
Edge structure 200.
Then, as shown in Fig. 2 f and 2g (Fig. 2 f are active area direction A sectional views, and Fig. 2 g are predetermined column direction B-section figure)
When forming micro- trench architectures 301, first etch the groove 300 the section of the active area 100 side wall, then in institute
It states and forms etching barrier layer 501 in the trench insulation structure 200 of side wall and the adjacent side wall, expose the groove 300
In the bottom of the section of the active area 100.Specifically, one layer of etching barrier layer 501 can be first deposited, then etching removal is recessed
Outside the slot and unwanted part in bottom, makes bottom portion of groove be exposed.
Then, as shown in Fig. 2 h and 2i (Fig. 2 h are active area direction A sectional views, and Fig. 2 i are predetermined column direction B-section figure)
Using bottom described in wet etching treatment, micro- trench architectures 301 are formed, the etching barrier layer 501 is then removed.At this
In embodiment, micro- trench architectures 301 include a plurality of irrigation canals and ditches recessed again side by side for being parallel to the predetermined column direction
3011a, and the direction of the irrigation canals and ditches 3011a recessed again is identical；Each irrigation canals and ditches recessed again in wherein described micro- trench architectures 301
3011a is intermediate recessed arc-shaped bend in the cross sectional shape for being parallel to the trench length extending direction, increases electricity to realize
The channel area of sub- transmission channel width and the transistor arrangement, while there are preferable current characteristics and the irrigation canals and ditches recessed again
Again recessed control of the depth at intermediate position in trench length extending direction；Specifically, the irrigation canals and ditches 3011a recessed again is parallel
In the groove width extending direction cross sectional shape be arc-shaped bending.And the present embodiment further utilizes arc-shaped bend
In continuous, the slowly varying characteristic of depth direction and width direction so that subsequent slot wire is filled up completely in described recessed again
Enter in irrigation canals and ditches 3011a, avoid the occurrence of gap, influences device performance.It should be noted that the present embodiment is also by recessed again by described in
The direction for entering irrigation canals and ditches 3011a is uniformly provided towards the inside of the semiconductor substrate, to further increase electron propagation ducts
Width while, increase the channel area of the transistor arrangement.Then, (Fig. 2 j are active area side as shown in Fig. 2 j and 2k
To A sectional views, Fig. 2 k are predetermined column direction B-section figure) remove the groove 300 the trench insulation structure 200 section
To form the complete groove 300.
Finally, as shown in Fig. 2 l and 2m (Fig. 2 l are active area direction A sectional views, and Fig. 2 m are predetermined column direction B-section figure)
The slot wire is formed, is embedded in the groove 300.Forming the slot wire and micro- fin gate structure
When 600, it can be initially formed gate dielectric layer 601, then gate electrode layer 602 is formed on the gate dielectric layer 601.In the gate electrode
602 surface of layer can form insulating layer 603.
Embodiment two
First, identical as embodiment one, semi-conductive substrate is provided, and formed in the semiconductor substrate surface a plurality of
Active area 100 and the trench insulation structure 200 that the active area 100 is isolated.
Then, as best shown in figures 3 a and 3b (Fig. 3 a are active area direction A sectional views, and Fig. 3 b are predetermined column direction B-section figure)
Hard mask layer 401 is formed, forms graphical photoresist layer 402 on the hard mask layer 401 to define 300 position of the groove,
It is etched to form section and the ditch of the groove 300 in the active area 100 downwards along the graphical photoresist layer 402
Section of the slot 300 in the trench insulation structure 200.Wherein it is possible to straight using the section for being dry-etched in the active area 100
Connect micro- trench architectures 301 needed for being formed.In the present embodiment, micro- trench architectures 301 include being parallel to the predetermined row side
To a plurality of irrigation canals and ditches 3011a recessed again side by side, and the direction of the irrigation canals and ditches 3011a recessed again is identical；Wherein described micro- ditch
Each irrigation canals and ditches 3011a recessed again is centre in the cross sectional shape for being parallel to the trench length extending direction in canal structure 301
Recessed arc-shaped bend has simultaneously to realize the channel area for increasing electron propagation ducts width and the transistor arrangement
Again recessed control of the depth at position in trench length extending direction among preferable current characteristics and the irrigation canals and ditches recessed again；Specifically
, the irrigation canals and ditches 3011a recessed again is arc-shaped bending in the cross sectional shape for being parallel to the groove width extending direction.And
The present embodiment further utilizes arc-shaped bend in continuous, the slowly varying characteristic of depth direction and width direction so that follow-up
Slot wire be filled up completely in the irrigation canals and ditches 3011a recessed again, avoid the occurrence of gap, influence device performance.It should be noted that
, the present embodiment by the direction of the irrigation canals and ditches 3011a recessed again also by being uniformly provided towards the semiconductor substrate
Inside while width to further increase electron propagation ducts, increases the channel area of the transistor arrangement.
Finally, as shown in figs. 3 c and 3d (Fig. 3 c are active area direction A sectional views, and Fig. 3 d are predetermined column direction B-section figure)
The slot wire is formed, is embedded in the groove 300.Forming the slot wire and micro- fin gate structure
When 600, it can be initially formed gate dielectric layer 601, then gate electrode layer 602 is formed on the gate dielectric layer 601.In the gate electrode
602 surface of layer can form insulating layer 603.
Embodiment three
As shown in figures 4a-4d, two institute of production method Yu embodiment one or embodiment of transistor arrangement described in the present embodiment
It is identical to state method, but the present embodiment and embodiment one and embodiment two difference lies in：Micro- trench architectures 301 described in the present embodiment
In each irrigation canals and ditches 3011b recessed again in the cross sectional shape for being parallel to the trench length extending direction be v-shaped bending, to realize
Increase the channel area of electron propagation ducts width and the transistor arrangement, while there is preferable current characteristics and described recessed again
Enter the again recessed control of the depth in trench length extending direction at position among irrigation canals and ditches；Specifically, the irrigation canals and ditches 3011b recessed again
Also it is v-shaped bending in the cross sectional shape for being parallel to the groove width extending direction.It should be noted that the present embodiment also passes through
The direction of the irrigation canals and ditches recessed again is uniformly provided towards to the inside of the semiconductor substrate, to further increase electron-transport
The width in channel, to increase the channel area of the transistor arrangement.
Example IV
As shown in Fig. 5 a-5d, production method and two institute of embodiment one or embodiment of transistor arrangement described in the present embodiment
It is identical to state method, but the present embodiment and embodiment one and embodiment two difference lies in：Micro- trench architectures 301 described in the present embodiment
In each irrigation canals and ditches 3011c recessed again in the cross sectional shape for being parallel to the trench length extending direction be inverted V-shaped bending, with reality
Now increase electron propagation ducts width and the transistor arrangement channel area, while have preferable current characteristics and it is described again
The depth at position is controlled in the compensation of trench length extending direction among recessed irrigation canals and ditches；Specifically, each irrigation canals and ditches recessed again
3011c is that U-bend is bent in the cross sectional shape for being parallel to the groove width extending direction.It should be noted that the present embodiment is also
By the way that the direction of the irrigation canals and ditches recessed again to be uniformly provided towards to the inside of the semiconductor substrate, to further increase electronics
The width of transmission channel, to increase the channel area of the transistor arrangement.
Embodiment five
As shown in figures 6 a-6d, two institute of production method Yu embodiment one or embodiment of transistor arrangement described in the present embodiment
It is identical to state method, but the present embodiment and embodiment one and embodiment two difference lies in：Micro- trench architectures 301 described in the present embodiment
Only include a recessed irrigation canals and ditches 3011d again；The wherein described irrigation canals and ditches 3011d recessed again is being parallel to the trench length extending direction
Cross sectional shape be intermediate recessed arc-shaped bend, to realize the ditch for increasing electron propagation ducts width and the transistor arrangement
Road area, while having the depth at position among preferable current characteristics and the irrigation canals and ditches recessed again in trench length extending direction
Recessed control again；Specifically, the irrigation canals and ditches 3011d recessed again is in the cross sectional shape for being parallel to the groove width extending direction
Arc-shaped bending.
Embodiment six
As shown in Fig. 7 a-7d, production method and two institute of embodiment one or embodiment of transistor arrangement described in the present embodiment
It is identical to state method, but the present embodiment and embodiment one and embodiment two difference lies in：Micro- trench architectures 301 described in the present embodiment
Only include a recessed irrigation canals and ditches 3011e again；The wherein described irrigation canals and ditches 3011e recessed again is being parallel to the trench length extending direction
Cross sectional shape be v-shaped bending, with realize increase electron propagation ducts width and the transistor arrangement channel area, simultaneously
Again recessed control of the depth with position among preferable current characteristics and the irrigation canals and ditches recessed again in trench length extending direction；
Specifically, the irrigation canals and ditches 3011e recessed again is also v-shaped bending in the cross sectional shape for being parallel to the groove width extending direction.
Embodiment seven
As shown in Figure 8 a-8d, two institute of production method Yu embodiment one or embodiment of transistor arrangement described in the present embodiment
It is identical to state method, but the present embodiment and embodiment one and embodiment two difference lies in：Micro- trench architectures 301 described in the present embodiment
Only include a recessed irrigation canals and ditches 3011f again；The wherein described irrigation canals and ditches 3011f recessed again is being parallel to the trench length extending direction
Cross sectional shape be inverted V-shaped bending, with realize increase electron propagation ducts width and the transistor arrangement channel area, together
When the depth with position among preferable current characteristics and the recessed irrigation canals and ditches again controlled in the compensation of trench length extending direction；
Specifically, the irrigation canals and ditches 3011f recessed again is that U-bend is bent in the cross sectional shape for being parallel to the groove width extending direction.
In conclusion the transistor arrangement and production method of the semiconductor memory of the present invention, by making special fin
Portion's structure makes channel area be increased on the basis of keeping original device size, this can further increase transmission channel
Width, to be greatly improved the device performance of field-effect transistor.
So the present invention effectively overcomes various shortcoming in the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology can all carry out modifications and changes to above-described embodiment without violating the spirit and scope of the present invention.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should by the present invention claim be covered.
Claims (25)
1. a kind of transistor arrangement of semiconductor memory, which is characterized in that including：
Semiconductor substrate, the trench insulation structure with a plurality of active areas and the isolation active area, each active area have
The first contact zone on the semiconductor substrate and the second contact zone, the semiconductor substrate are equipped with plural number in predetermined column direction
A groove, the active area being applied on predetermined column direction and the trench insulation structure, to detach the institute of the active area
The first contact zone and second contact zone are stated, wherein the groove has the first depth in the section of the active area, it is described
Groove has the second depth in the section of the trench insulation structure, and first depth is differed in second depth and not
More than the third depth of the trench insulation structure；And
A plurality of slot wires are embedded in the groove, wherein the groove further includes positioned at the section bottom of the active area
Micro- trench architectures in portion, micro- trench architectures include the section bottom recessed ditch recessed again again relative to the active area
Canal, the irrigation canals and ditches recessed again are that bending extends in the section for being parallel to the trench length extending direction, and the slot wire is more
The irrigation canals and ditches recessed again for inserting micro- trench architectures, to be formed towards micro- fin grid knot inside the semiconductor substrate
Structure, and micro- fin gate structure is integrated with the main body of the slot wire and connect.
2. the transistor arrangement of semiconductor memory according to claim 1, it is characterised in that：Micro- trench architectures packet
Include a plurality of irrigation canals and ditches recessed again side by side for being parallel to the trench length extending direction, and the irrigation canals and ditches recessed again towards phase
Together.
3. the transistor arrangement of semiconductor memory according to claim 1, it is characterised in that：The irrigation canals and ditches recessed again exist
The cross sectional shape for being parallel to the trench length extending direction includes intermediate recessed arc-shaped bend.
4. the transistor arrangement of semiconductor memory according to claim 1, it is characterised in that：The irrigation canals and ditches recessed again exist
The cross sectional shape for being parallel to the trench length extending direction includes v-shaped bending.
5. the transistor arrangement of semiconductor memory according to claim 1, it is characterised in that：The irrigation canals and ditches recessed again exist
The cross sectional shape for being parallel to the trench length extending direction includes inverted V-shaped bending.
6. the transistor arrangement of semiconductor memory according to claim 1, it is characterised in that：The irrigation canals and ditches recessed again
Depth capacity is not more than the depth difference of second depth and first depth, and the maximum width of the irrigation canals and ditches recessed again is opposite
It is not less than 0.1 in the ratio of the width of the groove.
7. the transistor arrangement of semiconductor memory according to claim 6, it is characterised in that：The irrigation canals and ditches recessed again
Depth capacity is between 2nm~20nm, and the maximum width of the irrigation canals and ditches recessed again is between 1nm~10nm.
8. the transistor arrangement of semiconductor memory according to claim 1, it is characterised in that：The section of the active area
Bottom is etching rough surface relative to the side wall of the groove.
9. the transistor arrangement of semiconductor memory according to claim 1, it is characterised in that：The slot wire surface
It is covered with insulating layer, the slot wire includes gate dielectric layer with micro- fin gate structure and is located on the gate dielectric layer
Gate electrode layer, the depth capacity and maximum width of the irrigation canals and ditches recessed again of micro- trench architectures are all more than the gate medium
Layer forms thickness and the cladding thickness less than the insulating layer.
10. according to the transistor arrangement of claim 1 to 9 any one of them semiconductor memory, it is characterised in that：Described
Two depth are more than first depth, for increasing structural strength of the slot wire in the trench insulation structure.
11. a kind of production method of the transistor arrangement of semiconductor memory, which is characterized in that the method includes following steps
Suddenly：
Semi-conductive substrate is provided, and forms a plurality of active areas in the semiconductor substrate surface and the active area is isolated
Trench insulation structure, each active area have the first contact zone and the second contact zone on the semiconductor substrate；
A plurality of grooves are formed in predetermined column direction on the semiconductor substrate, are applied in described active on predetermined column direction
Area and the trench insulation structure, to detach first contact zone and second contact zone, wherein institute of the active area
Stating groove in the section of the active area there is the first depth, the groove to have second in the section of the trench insulation structure
Depth, first depth are differed in second depth and no more than the third depth of the trench insulation structure, and
Include during forming the groove：The recessed groove again, it further includes positioned at the area of the active area to make the groove
Micro- trench architectures of section bottom, micro- trench architectures include relative to the active area section bottom it is recessed recessed again again
Irrigation canals and ditches, the irrigation canals and ditches recessed again are that bending extends in the section for being parallel to the trench length extending direction；And
A plurality of slot wires are formed, are embedded in the groove, the slot wire more inserts the institute of micro- trench architectures
Recessed irrigation canals and ditches are stated again, to be formed towards micro- fin gate structure inside the semiconductor substrate, and micro- fin grid
Structure is integrated with the main body of the slot wire and connect.
12. the production method of the transistor arrangement of semiconductor memory according to claim 11, it is characterised in that：It is described
Micro- trench architectures include being parallel to a plurality of irrigation canals and ditches recessed again side by side of the trench length extending direction, and described recessed again
The direction of irrigation canals and ditches is identical.
13. the production method of the transistor arrangement of semiconductor memory according to claim 11, it is characterised in that：It is described
Recessed irrigation canals and ditches include intermediate recessed arc-shaped bend in the cross sectional shape for being parallel to the trench length extending direction again.
14. the production method of the transistor arrangement of semiconductor memory according to claim 11, it is characterised in that：It is described
Recessed irrigation canals and ditches include v-shaped bending being parallel to the cross sectional shape of the trench length extending direction again.
15. the production method of the transistor arrangement of semiconductor memory according to claim 11, it is characterised in that：It is described
Recessed irrigation canals and ditches include inverted V-shaped bending in the cross sectional shape for being parallel to the trench length extending direction again.
16. the production method of the transistor arrangement of semiconductor memory according to claim 11, it is characterised in that：It is described
The depth capacity of recessed irrigation canals and ditches is not more than the depth difference of second depth and first depth again, the irrigation canals and ditches recessed again
Maximum width is not less than 0.1 relative to the ratio of the width of the groove.
17. the production method of the transistor arrangement of semiconductor memory according to claim 16, it is characterised in that：It is described
The depth capacity of recessed irrigation canals and ditches is between 2nm~20nm again, the maximum widths of the irrigation canals and ditches recessed again between 1nm~10nm it
Between.
18. the production method of the transistor arrangement of semiconductor memory according to claim 11, it is characterised in that：It is described
The section bottom of active area is etching rough surface relative to the side wall of the groove.
19. the production method of the transistor arrangement of semiconductor memory according to claim 11, it is characterised in that：Institute
It states and forms hard mask layer on active area, then form graphical photoresist layer on the hard mask layer to define the groove in institute
The section position of active area is stated, and is etched to form the groove in the area of the active area downwards along the graphical photoresist layer
Section.
20. the production method of the transistor arrangement of semiconductor memory according to claim 11, it is characterised in that：Using
Dry etching or wet etching form micro- trench architectures in the section bottom of the active area.
21. the production method of the transistor arrangement of semiconductor memory according to claim 11, it is characterised in that：First protect
The trench insulation structure is stayed, after forming micro- trench architectures, then removes the groove in the area of the trench insulation structure
Section is to form the complete groove.
22. the production method of the transistor arrangement of semiconductor memory according to claim 21, it is characterised in that：It is formed
When micro- trench architectures, first etch the groove the section of the active area side wall, then in the side wall and adjoining
Etching barrier layer is formed in the trench insulation structure of the side wall, exposes the groove at the bottom of the section of the active area
Portion, then bottom described in etching processing, forms micro- trench architectures, then removes the etching barrier layer.
23. the production method of the transistor arrangement of semiconductor memory according to claim 11, it is characterised in that：First move
Except the groove is in the section of the trench insulation structure, micro- trench architectures are re-formed.
24. the production method of the transistor arrangement of semiconductor memory according to claim 11, it is characterised in that：Institute
It states slot wire surface and forms insulating layer, and when forming the slot wire with micro- fin gate structure, be initially formed grid
Dielectric layer, then gate electrode layer is formed on the gate dielectric layer, the maximum of the irrigation canals and ditches recessed again of micro- trench architectures is deep
Degree and maximum width are all more than the cladding thickness for forming thickness and being less than the insulating layer of the gate dielectric layer.
25. the production method of the transistor arrangement of the semiconductor memory according to any one of claim 11 to 24,
It is characterized in that：Second depth is more than first depth, for increasing the slot wire in the trench insulation structure
In structural strength.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710682071.8A CN107342327A (en) | 2017-08-10 | 2017-08-10 | The transistor arrangement and preparation method of a kind of semiconductor memory |
| CN2017106820718 | 2017-08-10 |
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| Publication Number | Publication Date |
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| CN108717947A true CN108717947A (en) | 2018-10-30 |
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| CN201821270491.1U Active CN208489201U (en) | 2017-08-10 | 2018-08-08 | Transistor structure of semiconductor memory |
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| CN110517989A (en) * | 2018-05-21 | 2019-11-29 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110880510A (en) * | 2018-09-06 | 2020-03-13 | 长鑫存储技术有限公司 | Semiconductor device structure and preparation method thereof |
| CN110911476B (en) * | 2018-09-14 | 2024-05-14 | 长鑫存储技术有限公司 | Buried gate structure and manufacturing method thereof |
| CN110931514B (en) * | 2019-11-29 | 2022-04-08 | 云谷（固安）科技有限公司 | Array substrate and display panel |
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| CN108717947B (en) | 2024-03-26 |
| CN208489201U (en) | 2019-02-12 |
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