CN108712656B - Remote video processing method and video service terminal - Google Patents
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Abstract
The invention belongs to the technical field of image dynamic reconfiguration, in particular to a remote video processing method for processing dynamic reconfiguration images, which simultaneously provides a remote video service terminal for processing dynamic reconfiguration images, wherein the pipeline type parallel operation method respectively inputs data which are input in parallel into N-level operation threads, image processing results are respectively output by corresponding image processing functions of each level of the N-level operation threads, and the image processing results which are respectively output are accumulated to output the multiplication result or the addition result of the image processing functions or the addition result of multi-level cascade The beneficial technical effects of high execution efficiency, high practicability and high applicability of the whole system are improved.
Description
Technical Field
The invention belongs to the technical field of dynamic reconfiguration of images, in particular to a remote video processing method for processing dynamic reconfiguration images.
Background
At present, Discrete Cosine Transform (DCT) is a real number domain transform, the transform kernel of which is a real number cosine function, and many important visual information about an image after performing discrete cosine transform on an image are concentrated in a small part of coefficients of the DCT transform, so the discrete cosine transform is the core of lossy image compression JPEG, and meanwhile, one of the main transform domains of a so-called "transform domain information hiding algorithm" is provided, because image processing adopts one-dimensional discrete cosine transform, the prior art has the problem that the prior art is not suitable for scientific operation of image processing due to the low efficiency of serial execution codes of a general-purpose processor.
Disclosure of Invention
The invention provides a remote video processing method for dynamically reconfiguring image processing and a video service terminal, which aim to solve the problem that the prior art is not suitable for scientific operation of image processing due to low efficiency of serial execution codes of a general processor.
The technical problem solved by the invention is realized by adopting the following technical scheme: a remote video processing method of dynamically reconfiguring image processing, comprising: the method for the pipeline parallel operation comprises the following steps:
a flow parallel operation equation:
the n is a corresponding level numerical value in the level set of the parallel dynamic reconfiguration hierarchical operation;
the N is the maximum stage number of the parallel dynamic reconfiguration hierarchical operation;
the k is 1 to the maximum stage number N of the stage-by-stage operation, and is increased by 1 in the stage-by-stage operation process;
the operational equation of x (k) is:
the operational equation of e (n) is as follows:
f (n) is an image processing function;
the f (n) is an intermediate value of the image processing of the corresponding stage of the image processing result which is respectively output through a pipeline parallel operation equation;
and the x (k) stage of corresponding image processing function respectively outputs an image processing result.
Further, the set of the levels of the hierarchical operation is a set of natural numbers from 0 to N-1.
Further, the pipeline parallel operation method inputs the parallel input data into N-level operation threads respectively, the image processing functions corresponding to each level of the N-level operation threads output image processing results respectively, and the output image processing results output image processing function multiplication results or addition results or multi-level cascade addition results through accumulation.
Further, the pipeline parallel operation method comprises eight-stage parallel operation with N-8.
Further, the eight-stage parallel operation includes an eight-stage operation thread.
Further, the addition operation equation of the multistage cascade of the eight-stage operation threads is as follows:
fn(8)＝f(0)+f(1)+f(2)+f(3)+f(4)+f(5)+f(6)+f(7)；
the f (0) is a first-level operation thread;
the f (1) is a second-level operation thread;
the f (2) is a third-level operation thread;
the f (3) is a fourth-stage operation thread;
the f (4) is a fifth-level operation thread;
the f (5) is a sixth-level operation thread;
the f (6) is a seventh-level operation thread;
the f (7) is an eighth-level operation thread;
and fn (8) is the running result of the parallel operation of the eight-level operation threads.
Meanwhile, the invention also provides a remote video service terminal for dynamically reconfiguring image processing, which comprises a pipeline type parallel operation module, wherein the pipeline type parallel operation module comprises:
a flow parallel operation equation:
the n is a corresponding level numerical value in the level set of the parallel dynamic reconfiguration hierarchical operation;
the N is the maximum stage number of the parallel dynamic reconfiguration hierarchical operation;
the k is 1 to the maximum stage number N of the stage-by-stage operation, and is increased by 1 in the stage-by-stage operation process;
the operational equation of x (k) is:
the operational equation of e (n) is as follows:
f (n) is an image processing function;
the f (n) is an intermediate value of the image processing of the corresponding stage of the image processing result which is respectively output through a pipeline parallel operation equation;
and the x (k) stage of corresponding image processing function respectively outputs an image processing result.
Further, the set of the levels of the hierarchical operation is a set of natural numbers from 0 to N-1.
Further, the pipeline parallel operation method inputs the parallel input data into N-level operation threads respectively, the image processing functions corresponding to each level of the N-level operation threads output image processing results respectively, and the output image processing results output image processing function multiplication results or addition results or multi-level cascade addition results through accumulation.
Further, the pipelined parallel operation method includes eight-level parallel operation with N-8, where the eight-level parallel operation includes eight-level operation threads, and the multi-level cascaded addition operation equation of the eight-level operation threads is:
fn(8)＝f(0)+f(1)+f(2)+f(3)+f(4)+f(5)+f(6)+f(7)；
the f (0) is a first-level operation thread;
the f (1) is a second-level operation thread;
the f (2) is a third-level operation thread;
the f (3) is a fourth-stage operation thread;
the f (4) is a fifth-level operation thread;
the f (5) is a sixth-level operation thread;
the f (6) is a seventh-level operation thread;
the f (7) is an eighth-level operation thread;
and fn (8) is the running result of the parallel operation of the eight-level operation threads.
The beneficial technical effects are as follows:
1. the method for the pipeline parallel operation comprises the following steps:
a flow parallel operation equation:
the n is a corresponding level numerical value in the level set of the parallel dynamic reconfiguration hierarchical operation;
the N is the maximum stage number of the parallel dynamic reconfiguration hierarchical operation;
the k is 1 to the maximum stage number N of the stage-by-stage operation, and is increased by 1 in the stage-by-stage operation process;
the operational equation of x (k) is:
the operational equation of e (n) is as follows:
f (n) is an image processing function, and f (n) is an intermediate value of image processing of the corresponding stage of the image processing result respectively output through a pipeline parallel operation equation; the corresponding image processing function of each level x (k) respectively outputs an image processing result; the flow type parallel operation method respectively inputs the data which are input in parallel into N-level operation threads, the image processing function corresponding to each level of the N-level operation threads respectively outputs the image processing result, the image processing result which is respectively output is accumulated to output the multiplication operation result or the addition operation result of the image processing function or the addition operation result of multi-level cascade connection, because the algorithm has high parallelism and regular data flow, a large class of image processing algorithms are realized, at the moment, the algorithm based on the pulse array realizes the interactive realization which is actually converted into operation nodes, for the realization that all the nodes are possibly realized in a single chip, for the algorithm which has complicated algorithm and large node scale, a plurality of threads can correspond to one operation node, and because of the parallelism and the flow type of the pulse processing, a plurality of algorithms can be realized in real time, therefore, the method avoids the inefficiency of serial execution of codes of a general-purpose processor, and is more suitable for scientific operation of image processing.
2. This patent adopts the fast algorithm of one-dimensional DCT, can see from the algorithm, whole operation adopts the parallel mode to handle 8 input data simultaneously, and the regularity and the hierarchy nature of the data flow direction in the structure show that the algorithm can adopt the mode of running water to handle, therefore, software operation can obtain higher operational efficiency, the node in the flow chart includes multiplication, addition and delay unit, can realize node operation through realizing multiplier, adder and latch in single chip or procedure, in software, provide adder unit, utilize this unit not only can realize addition operation in the node unit, multiplication can also realize through the cascade of multistage adder, the operational speed of multiplier has been improved.
3. For a specific algorithm, the method can be realized efficiently by adopting a proper hardware structure, however, a scientific operation program comprises a plurality of intensive operation codes, each section of code realizes different algorithms, in order to reduce the burden of a general processor and improve the operation efficiency, each section of intensive operation code can be realized by adopting hardware or software, the circuit structure is continuously changed or the configuration of threads is changed in the operation stage of the program, the reconfiguration mode is also adopted, the section of code is transferred to a reasonable hardware structure for execution, and the execution efficiency of the whole system is improved.
4. The method adopts the pipeline parallel operation module to realize the pipeline parallel operation method, thereby improving the practicability and the application of the dynamic reconfiguration image processing device.
Drawings
FIG. 1 is a flow chart of a remote video processing method for dynamically reconfiguring image processing according to the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings:
in the figure:
s101, respectively inputting data input in parallel into N-level operation threads by a pipeline type parallel operation method;
s102, outputting image processing results by the corresponding image processing functions of each level of the N-level operation threads respectively;
s103, accumulating the image processing function multiplication operation result or addition operation result or multi-stage cascade addition operation result of the respectively output image processing result;
example (b):
in this embodiment: as shown in fig. 1, a remote video processing method for dynamically reconfiguring image processing, includes: the method for the pipeline parallel operation comprises the following steps:
a flow parallel operation equation:
the n is a corresponding level numerical value in the level set of the parallel dynamic reconfiguration hierarchical operation;
the N is the maximum stage number of the parallel dynamic reconfiguration hierarchical operation;
the k is 1 to the maximum stage number N of the stage-by-stage operation, and is increased by 1 in the stage-by-stage operation process;
the operational equation of x (k) is:
the operational equation of e (n) is as follows:
f (n) is an image processing function;
the f (n) is an intermediate value of the image processing of the corresponding stage of the image processing result which is respectively output through a pipeline parallel operation equation;
and the x (k) stage of corresponding image processing function respectively outputs an image processing result.
The stage set of the hierarchical operation is a natural number set from 0 to N-1.
The method comprises the steps of inputting data input in parallel into N-level operation threads S101 respectively, outputting image processing results S102 by image processing functions corresponding to each level of the N-level operation threads respectively, and outputting multiplication results or addition results of the image processing functions or multi-level cascaded addition results S103 by accumulating the output image processing results respectively.
The pipeline parallel operation method comprises the following steps:
a flow parallel operation equation:
the n is a corresponding level numerical value in the level set of the parallel dynamic reconfiguration hierarchical operation;
the N is the maximum stage number of the parallel dynamic reconfiguration hierarchical operation;
the k is 1 to the maximum stage number N of the stage-by-stage operation, and is increased by 1 in the stage-by-stage operation process;
the operational equation of x (k) is:
the operational equation of e (n) is as follows:
f (n) is an image processing function, and f (n) is an intermediate value of image processing of the corresponding stage of the image processing result respectively output through a pipeline parallel operation equation; the corresponding image processing function of each level x (k) respectively outputs an image processing result; the flow type parallel operation method respectively inputs the data which are input in parallel into N-level operation threads, the image processing function corresponding to each level of the N-level operation threads respectively outputs the image processing result, the image processing result which is respectively output is accumulated to output the multiplication operation result or the addition operation result of the image processing function or the addition operation result of multi-level cascade connection, because the algorithm has high parallelism and regular data flow, a large class of image processing algorithms are realized, at the moment, the algorithm based on the pulse array realizes the interactive realization which is actually converted into operation nodes, for the realization that all the nodes are possibly realized in a single chip, for the algorithm which has complicated algorithm and large node scale, a plurality of threads can correspond to one operation node, and because of the parallelism and the flow type of the pulse processing, a plurality of algorithms can be realized in real time, therefore, the method avoids the inefficiency of serial execution of codes of a general-purpose processor, and is more suitable for scientific operation of image processing.
The pipeline parallel operation method comprises eight-stage parallel operation with N-8.
As a one-dimensional DCT fast algorithm is adopted, the algorithm can be seen that 8 input data are simultaneously processed in a parallel mode in the whole operation, and the regularity and hierarchy of the data flow direction in the structure indicate that the algorithm can be processed in a running mode, so that higher operation efficiency can be obtained in software operation.
The eight-stage parallel operation includes an eight-stage operation thread.
Because a specific algorithm can be efficiently realized by adopting a proper hardware structure, but a scientific operation program comprises a plurality of intensive operation codes, and each section of code realizes different algorithms, in order to reduce the burden of a general processor and improve the operation efficiency, each section of intensive operation codes can be realized by adopting hardware or software, the circuit structure is continuously changed or the configuration of threads is changed in the running stage of the program, the reconfiguration mode is also adopted, and the section of code is transferred to a reasonable hardware structure to be executed, so that the execution efficiency of the whole system is improved.
The multistage cascade addition operation equation of the eight-stage operation thread is as follows:
fn(8)＝f(0)+f(1)+f(2)+f(3)+f(4)+f(5)+f(6)+f(7)；
the f (0) is a first-level operation thread;
the f (1) is a second-level operation thread;
the f (2) is a third-level operation thread;
the f (3) is a fourth-stage operation thread;
the f (4) is a fifth-level operation thread;
the f (5) is a sixth-level operation thread;
the f (6) is a seventh-level operation thread;
the f (7) is an eighth-level operation thread;
and fn (8) is the running result of the parallel operation of the eight-level operation threads.
Including pipelined parallel operation module, pipelined parallel operation module includes:
a flow parallel operation equation:
the n is a corresponding level numerical value in the level set of the parallel dynamic reconfiguration hierarchical operation;
the N is the maximum stage number of the parallel dynamic reconfiguration hierarchical operation;
the k is 1 to the maximum stage number N of the stage-by-stage operation, and is increased by 1 in the stage-by-stage operation process;
the operational equation of x (k) is:
the operational equation of e (n) is as follows:
f (n) is an image processing function;
the f (n) is an intermediate value of the image processing of the corresponding stage of the image processing result which is respectively output through a pipeline parallel operation equation;
the corresponding image processing function of each level x (k) respectively outputs an image processing result;
the pipeline parallel operation module is adopted to realize the pipeline parallel operation method, so the practicability and the application of the dynamic reconfiguration image processing device are improved.
The stage set of the hierarchical operation is a natural number set from 0 to N-1.
The method comprises the steps of inputting data input in parallel into N-level operation threads respectively, outputting image processing results by image processing functions corresponding to each level of the N-level operation threads respectively, and outputting image processing function multiplication operation results or addition operation results or multi-level cascaded addition operation results by accumulating the output image processing results respectively.
The pipelined parallel operation method comprises eight-level parallel operation with N being 8, the eight-level parallel operation comprises eight-level operation threads, and the multi-level cascaded addition operation equation of the eight-level operation threads is as follows:
fn(8)＝f(0)+f(1)+f(2)+f(3)+f(4)+f(5)+f(6)+f(7)；
the f (0) is a first-level operation thread;
the f (1) is a second-level operation thread;
the f (2) is a third-level operation thread;
the f (3) is a fourth-stage operation thread;
the f (4) is a fifth-level operation thread;
the f (5) is a sixth-level operation thread;
the f (6) is a seventh-level operation thread;
the f (7) is an eighth-level operation thread;
and fn (8) is the running result of the parallel operation of the eight-level operation threads.
The working principle is as follows:
the method for the pipeline parallel operation comprises the following steps:
a flow parallel operation equation:
the n is a corresponding level numerical value in the level set of the parallel dynamic reconfiguration hierarchical operation;
the N is the maximum stage number of the parallel dynamic reconfiguration hierarchical operation;
the k is 1 to the maximum stage number N of the stage-by-stage operation, and is increased by 1 in the stage-by-stage operation process;
the operational equation of x (k) is:
the operational equation of e (n) is as follows:
f (n) is an image processing function, and f (n) is an intermediate value of image processing of the corresponding stage of the image processing result respectively output through a pipeline parallel operation equation; the corresponding image processing function of each level x (k) respectively outputs an image processing result; the flow type parallel operation method respectively inputs the data which are input in parallel into N-level operation threads, the image processing function corresponding to each level of the N-level operation threads respectively outputs the image processing result, the image processing result which is respectively output is accumulated to output the multiplication operation result or the addition operation result of the image processing function or the addition operation result of multi-level cascade connection, because the algorithm has high parallelism and regular data flow, a large class of image processing algorithms are realized, at the moment, the algorithm based on the pulse array realizes the interactive realization which is actually converted into operation nodes, for the realization that all the nodes are possibly realized in a single chip, for the algorithm which has complicated algorithm and large node scale, a plurality of threads can correspond to one operation node, and because of the parallelism and the flow type of the pulse processing, a plurality of algorithms can be realized in real time, the invention solves the problem that the prior art is not suitable for scientific operation of image processing due to low efficiency of serial execution codes of a general processor, and has the beneficial technical effects of being more suitable for scientific operation of image processing, improving the operation speed of a multiplier and improving the execution efficiency, the practicability and the applicability of the whole system.
The technical solutions of the present invention or similar technical solutions designed by those skilled in the art based on the teachings of the technical solutions of the present invention are all within the scope of the present invention to achieve the above technical effects.
Claims (2)
1. A remote video processing method for dynamically reconfiguring image processing is characterized by comprising a pipeline parallel operation method, wherein the pipeline parallel operation method comprises the following steps:
respectively inputting the data input in parallel into N-level operation threads, respectively outputting image processing results by corresponding image processing functions of each level of the N-level operation threads, and accumulating the respectively output image processing results by a pipeline parallel operation equation to output a multi-level cascade addition operation result;
a flow parallel operation equation:
the n is a corresponding level numerical value in the level set of the parallel dynamic reconfiguration hierarchical operation;
the N is the maximum stage number of the parallel dynamic reconfiguration hierarchical operation;
the k is 1 to the maximum stage number N of the stage-by-stage operation, and is increased by 1 in the stage-by-stage operation process;
the operational equation of x (k) is:
the operational equation of e (n) is as follows:
f (n) is an image processing function;
the f (n) is an intermediate value of image processing of a corresponding stage through a pipeline parallel operation equation;
the corresponding image processing function of each level x (k) respectively outputs an image processing result;
the stage set of the hierarchical operation is a natural number set from 0 to N-1;
the pipeline parallel operation method comprises eight-stage parallel operation with N being 8;
the eight-stage parallel operation comprises an eight-stage operation thread;
the multistage cascade addition operation equation of the eight-stage operation thread is as follows:
fn(8)＝f(0)+f(1)+f(2)+f(3)+f(4)+f(5)+f(6)+f(7)；
the f (0) is a first-level operation thread;
the f (1) is a second-level operation thread;
the f (2) is a third-level operation thread;
the f (3) is a fourth-stage operation thread;
the f (4) is a fifth-level operation thread;
the f (5) is a sixth-level operation thread;
the f (6) is a seventh-level operation thread;
the f (7) is an eighth-level operation thread;
and fn (8) is the running result of the parallel operation of the eight-level operation threads.
2. A remote video service terminal for dynamically reconfiguring image processing is characterized by comprising a pipeline type parallel operation module, wherein the pipeline type parallel operation module comprises a pipeline type parallel operation method, and the pipeline type parallel operation method comprises the following steps:
respectively inputting the data input in parallel into N-level operation threads, respectively outputting image processing results by corresponding image processing functions of each level of the N-level operation threads, and accumulating the respectively output image processing results by a pipeline parallel operation equation to output a multi-level cascade addition operation result;
a flow parallel operation equation:
the n is a corresponding level numerical value in the level set of the parallel dynamic reconfiguration hierarchical operation;
the N is the maximum stage number of the parallel dynamic reconfiguration hierarchical operation;
the k is 1 to the maximum stage number N of the stage-by-stage operation, and is increased by 1 in the stage-by-stage operation process;
the operational equation of x (k) is:
the operational equation of e (n) is as follows:
f (n) is an image processing function;
the f (n) is an intermediate value of the image processing of the corresponding stage of the image processing result which is respectively output through a pipeline parallel operation equation;
the corresponding image processing function of each level x (k) respectively outputs an image processing result;
the stage set of the hierarchical operation is a natural number set from 0 to N-1;
the pipelined parallel operation method comprises eight-level parallel operation with N being 8, the eight-level parallel operation comprises eight-level operation threads, and the multi-level cascaded addition operation equation of the eight-level operation threads is as follows:
fn(8)＝f(0)+f(1)+f(2)+f(3)+f(4)+f(5)+f(6)+f(7)；
the f (0) is a first-level operation thread;
the f (1) is a second-level operation thread;
the f (2) is a third-level operation thread;
the f (3) is a fourth-stage operation thread;
the f (4) is a fifth-level operation thread;
the f (5) is a sixth-level operation thread;
the f (6) is a seventh-level operation thread;
the f (7) is an eighth-level operation thread;
and fn (8) is the running result of the parallel operation of the eight-level operation threads.
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| CN102007768A (en) * | 2008-04-16 | 2011-04-06 | 弗朗霍夫应用科学研究促进协会 | Bit-depth scalability |
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|---|
| 基于多核DSP的数字图像处理并行化方法研究;寇福东;《中国优秀硕士学位论文全文数据库 信息科技辑》;20150715;全文 * |
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Effective date of registration: 20221128 Address after: 250013 Room 903, Block A, Jinyu Center, No. 5777, Jingshi Road, Jinan District, China (Shandong) Pilot Free Trade Zone, Jinan City, Shandong Province Patentee after: Shandong Qingcheng Shilian Information Technology Co.,Ltd. Address before: 256603, No. five, 391 the Yellow River Road, Bincheng District, Shandong, Binzhou Patentee before: BINZHOU University |