CN108712418B

CN108712418B - A receiver

Info

Publication number: CN108712418B
Application number: CN201810478208.2A
Authority: CN
Inventors: 张书迁; 钱永学; 王志华; 叶晓斌; 杨清华
Original assignee: Shenzhen Angrui Microelectronics Technology Co ltd
Current assignee: Shenzhen Angrui Microelectronics Technology Co ltd
Priority date: 2018-05-18
Filing date: 2018-05-18
Publication date: 2021-07-27
Anticipated expiration: 2038-05-18
Also published as: CN108712418A

Abstract

The application provides a data packet and a receiver thereof, the data packet comprises: a preamble; a synchronization address interfacing with the preamble; a guard interval contiguous with the synchronization address; a payload concatenated with the guard interval. According to the data packet, the guard interval is added between the synchronous address and the effective load, and the data is cached by the buffer instead of the buffer, so that the use of the buffer in the receiver is avoided, the implementation of the receiver is simplified, and the cost of the receiver is reduced.

Description

A receiver

Technical Field

The present application relates to the field of wireless communication technologies, and in particular, to a data packet and a receiver thereof.

Background

With the continuous development of the internet of things technology, the application based on various short-distance wireless communication protocols is more and more, and the application field is more and more extensive. A short-distance wireless communication system based on an FSK (Frequency-shift keying) modulation scheme is widely used due to the advantages of simple implementation, small chip area, low power consumption, high transmission efficiency, strong anti-interference and anti-attenuation performances, and the like.

Fig. 1 shows a conventional data packet structure based on an FSK modulation scheme, which includes a Preamble, a synchronization Address, and a Payload, and the data packet needs to be received by a conventional receiver, as shown in fig. 2, fig. 2 is a conventional FSK receiver architecture, and since a synchronization circuit of the receiver finds out synchronization position information and has a hysteresis effect, the conventional FSK receiver architecture must have a buffer to buffer a certain amount of load information. Taking 32-bit synchronous address, lag time of 8 bits, delay from mixer to buffer of data path of 40 sampling points as an example, if the symbol oversampling rate is 8 times that of common, and the width of I, Q data on data path is 10 bits, then the buffer needs at least N_T1＝20×(40+8×8)＝2080， N_T2As compared with a simple FSK receiver, the area occupied by the registers is still large, i.e., 7200 registers (20 × 40+8 × 8+32 × 8).

In view of the above, there is a need for a new type of data packet and a receiver thereof, so as to avoid using a buffer in the receiver, thereby achieving the purposes of simplifying the implementation of the receiver and reducing the cost of the receiver.

Disclosure of Invention

The application provides a data packet and a receiver thereof, so as to avoid the use of a buffer in a traditional receiver, thereby simplifying the implementation of the receiver and reducing the cost of the receiver.

In order to achieve the above object, the present application provides the following technical solutions:

a data packet, comprising:

a preamble;

a synchronization address interfacing with the preamble;

a guard interval contiguous with the synchronization address;

a payload concatenated with the guard interval.

Preferably, the length of the guard interval is not less than the sum of the number of bits corresponding to the synchronization delay and the number of bits corresponding to the delay of the data path.

Preferably, the length of the guard interval is not less than the sum of the number of bits corresponding to the synchronization delay, the number of bits corresponding to the delay of the data path, and the number of bits corresponding to the length of the synchronization address.

Preferably, the data corresponding to the synchronous address is stored in the last 4 bytes of the guard interval and is sorted according to the address order.

Preferably, in the content of the guard interval, the difference between the numbers of 0 and 1 does not exceed a preset value.

Preferably, the content of the guard interval is different from the content of the synchronization address.

A receiver for receiving a data packet according to any one of the above, the receiver comprising:

the analog-to-digital converter ADC is used for receiving input data containing the data packet and carrying out analog-to-digital conversion on the input data to obtain a digital signal;

the down-sampling filter is used for carrying out down-sampling processing on the digital signal to obtain a down-sampled signal;

the intermediate frequency removing circuit is used for carrying out frequency mixing processing on the down-sampling signal by utilizing an intermediate frequency value and a carrier frequency offset estimation value to obtain a frequency mixing signal;

the channel filter is used for carrying out-of-band noise filtering processing on the frequency mixing signal to obtain a filtering signal;

the FSK demodulator is used for demodulating the filtering signal to obtain demodulation information and providing data input for the synchronizer by using the demodulation information before synchronous position information is obtained;

the synchronizer is used for outputting synchronous position information to the FSK modulator, controlling to open an input switch of the FSK demodulator after the FSK demodulator obtains the synchronous position information, and simultaneously outputting the carrier frequency offset estimation value to the IF removal circuit until the input data is data needing demodulation and detection, and controlling to close the input switch to connect a data path;

and the detector is used for detecting the demodulation information and outputting the demodulation information.

Preferably, the down-sampling filter is specifically configured to down-sample the digital signal to 8 times the code rate.

Preferably, the mixing process includes: removing intermediate frequency processing and carrier frequency offset processing.

As can be seen from the above technical solutions, the present application provides a data packet and a receiver thereof, where the data packet includes: a preamble; a synchronization address interfacing with the preamble; a guard interval contiguous with the synchronization address; a payload concatenated with the guard interval. According to the data packet, the guard interval is added between the synchronous address and the effective load, and the data is cached by the buffer instead of the buffer, so that the use of the buffer in the receiver is avoided, the implementation of the receiver is simplified, and the cost of the receiver is reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a schematic diagram of a conventional data packet structure based on FSK modulation;

fig. 2 is a schematic diagram of a conventional FSK receiver architecture;

fig. 3 is a schematic structural diagram of a data packet according to an embodiment of the present application;

fig. 4 is a schematic diagram of an FSK receiver architecture according to a second embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In order to avoid the use of a buffer in a traditional receiver, thereby simplifying the implementation of the receiver and reducing the cost of the receiver, the application provides a data packet and a receiver thereof, and the specific scheme is as follows:

example one

An embodiment of the present application provides a novel data packet, as shown in fig. 3, fig. 3 is a schematic structural diagram of the data packet provided in the embodiment of the present application, where the data packet includes:

a Preamble;

a synchronous Address connected with the Preamble;

a Guard interval Guard connected with the synchronous Address;

payload that interfaces with Guard interval Guard.

Specifically, generally, the number of Preamble is 8 bits, followed by the synchronization Address, the number of which is 32 bits, the Payload, the length of which is N bits, and depending on the difference in the number of different applications, the present invention adds a Guard interval Guard of N bits between the synchronization Address and the Payload. The lengths of the preamble, the synchronization address and the guard interval may also be different, and do not affect the meaning of the present invention.

In this application, the length of the guard interval corresponds to the length of the data stored in the buffer, and the specific length setting mode is as follows:

in one case, if it is not necessary to retrace (at this time, carrier frequency offset is corrected) after synchronization to detect all synchronization addresses, a shorter guard interval is used, Ng ≧ Nt1 ═ Ndelay + Ndpath, where Ng denotes the length of the guard interval, and Nt1 includes the number of bits Ndelay corresponding to the synchronization delay and the number of bits Ndpath corresponding to the delay of the data path, that is, the length of the guard interval is not less than the sum of the number of bits corresponding to the synchronization delay and the number of bits corresponding to the delay of the data path;

in another case, if all synchronization addresses need to be retraced (at this time or corrected for carrier frequency offset) after synchronization, a longer guard interval is used, Ng ≧ Nt2 ═ Ndelay + Ndpath + Naddr, where Naddr denotes the length of a synchronization address, that is, the length of the guard interval is not less than the sum of the number of bits corresponding to the synchronization delay, the number of bits corresponding to the delay of the data path, and the number of bits corresponding to the length of the synchronization address. It should be noted that, in this case, the added data corresponding to the synchronization address needs to be placed in the last 4 bytes of the guard interval and sorted according to the address order; the first data that the receiver needs to demodulate and detect at this time is the 1 st bit of the 4 bytes.

In particular, the second benefit is: after synchronization, carrier frequency offset is corrected, so that re-demodulated data is more accurate, and error synchronization can be avoided in time after comparison with a reference address; the bad part is: the Guard length is increased, thereby reducing the payload transmission rate of the system as a whole, since the really useful data is in payload.

The first case has the advantage of increasing the payload transmission rate compared to the second case; the disadvantage is that if the data packet is in error synchronization, the data error is not found until the whole data packet is received, and the data error is generally found through CRC check at the tail end of payload.

Taking a 32-bit synchronous address, a lag time of 8 bits, and a data path mixer-to-buffer delay of 40 samples as an example, if a common 8-fold symbol oversampling rate is adopted, then in the first case, a time length of (40/8+8) ═ 13 bits is required, that is, the Guard interval Guard needs at least 13 bits; in the second case, a time length of (40/8+8+32) ═ 45bit is required, i.e. the Guard interval Guard requires at least 45 bit. For convenience, the Guard interval Guard will generally take an integer byte length; i.e. a Guard interval Guard of length 2 and 6 bytes, respectively.

The content of the guard interval is relatively arbitrary with respect to the length of the guard interval, preferably without affecting the operation of the synchronizer, but preferably is not repeated or similar to the content of the synchronization address, i.e. the content of the guard interval is different from the content of the synchronization address, in order to avoid an increase in the mis-synchronization rate. And secondly, the difference between the number of 0 and 1 of the guard interval is not too large, the difference between the number of 0 and 1 is not more than a preset value, and the guard interval is selected according to the actual situation.

As can be seen from the foregoing technical solutions, the data packet provided in the first embodiment of the present application includes: a preamble; a synchronization address that interfaces with the preamble; a guard interval interfacing with the synchronization address; a payload concatenated with a guard interval. According to the data packet provided by the application, the guard interval is added between the synchronous address and the effective load, and the data is cached by the buffer instead of the buffer, so that the use of the buffer in the receiver is avoided, the implementation of the receiver is simplified, and the cost of the receiver is reduced.

Example two

A second embodiment of the present application provides a receiver, configured to receive the data packet according to the first embodiment, as shown in fig. 4, where fig. 4 is a schematic diagram of an architecture of an FSK receiver according to the second embodiment of the present application. The receiver includes:

the analog-to-digital converter ADC101 is used for receiving input data containing data packets and performing analog-to-digital conversion on the input data to obtain digital signals;

the down-sampling filter 102 is configured to perform down-sampling processing on the digital signal to obtain a down-sampled signal;

specifically, the down-sampling filter down-samples the digital signal to 8 times the code rate.

The intermediate frequency removing circuit 103 is used for performing frequency mixing processing on the down-sampled signal by using the intermediate frequency value and the carrier frequency offset estimation value to obtain a frequency mixing signal;

the mixing process comprises: removing intermediate frequency processing and carrier frequency offset processing.

The channel filter 104 is configured to perform out-of-band noise filtering processing on the mixed signal to obtain a filtered signal;

an FSK demodulator 105 for demodulating the filtered signal to obtain demodulation information and providing data input to the synchronizer 106 using the demodulation information before obtaining the synchronization position information;

a synchronizer 106, configured to output synchronization position information to the FSK modulator 105, after the FSK demodulator 105 obtains the synchronization position information, control to open an input switch of the FSK demodulator 105, and simultaneously output a carrier frequency offset estimation value to the if removal circuit 103, until the input data is data to be demodulated and detected, control to close the input switch to connect a data path;

and a detector 107 for detecting the demodulated information and outputting it.

Specifically, after data is collected from an ADC (Analog-to-digital converter), down-sampling is generally performed first, and I, Q two paths of digital signals are down-sampled to 8 times of a code rate (symbol rate), for a low-intermediate frequency architecture which is commonly adopted, the signals are down-sampled and then pass through an intermediate frequency removing circuit, which is actually a mixer circuit, and simultaneously receives a carrier frequency offset estimation value transmitted from a carrier frequency offset estimation module, and the estimation value and the intermediate frequency value are summed to be used as input of the mixer, so as to achieve the purpose of removing the intermediate frequency and the carrier frequency offset simultaneously; the signal without intermediate frequency is input into a channel filter to filter out the out-of-band noise outside the channel, and then enters an FSK demodulator, so as to obtain demodulated data information, wherein the data information is still 8 times of bit rate.

The receiver architecture provided by the application has no buffer, and the essence lies in that the data buffer is replaced by the Guard interval Guard of the data packet, thereby simplifying the design of the receiver. In the structure, the synchronous position information output by the synchronizer directly controls an input switch of the FSK demodulator, the switch is in a closed state before the synchronous position information is obtained, and the FSK demodulator provides data input for the synchronizer; and after the synchronous position information is obtained, the switch is opened, and simultaneously, the frequency offset estimation information is output to the frequency mixer, until the input data is the data needing demodulation and detection, the switch is closed, and the data path is switched on.

According to the technical scheme, the receiver provided by the second embodiment of the application avoids the use of a buffer, the Guard interval Guard of the data packet replaces the buffer for buffering the data, the design of the receiver is simplified, the production cost of the receiver is reduced, and the performance of the receiver cannot be reduced.

Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A receiver configured to receive a data packet, the data packet being applied to an FSK-based modulation scheme, the receiver comprising: a preamble; a synchronization address interfacing with the preamble; a guard interval contiguous with the synchronization address; a payload concatenated with the guard interval;

the receiver includes:

2. The receiver according to claim 1, wherein the down-sampling filter is specifically configured to down-sample the digital signal to 8 times a code rate.

3. The receiver of claim 1, wherein the mixing process comprises: removing intermediate frequency processing and carrier frequency offset processing.

4. The receiver of claim 1, wherein the length of the guard interval is not less than the sum of the number of bits corresponding to the synchronization delay and the number of bits corresponding to the delay of the data path.

5. The receiver of claim 1, wherein the length of the guard interval is not less than the sum of the number of bits corresponding to the synchronization delay, the number of bits corresponding to the delay of the data path, and the number of bits corresponding to the length of the synchronization address.

6. The receiver of claim 5, wherein the data corresponding to the synchronization address is stored in the last 4 bytes of the guard interval and is sorted in address order.

7. The receiver of claim 1, wherein the difference between the number of 0 s and the number of 1 s in the content of the guard interval does not exceed a predetermined value.

8. The receiver of claim 1, wherein the content of the guard interval is different from the content of the synchronization address.