CN108695373A - A kind of semiconductor device - Google Patents
A kind of semiconductor device Download PDFInfo
- Publication number
- CN108695373A CN108695373A CN201710226683.6A CN201710226683A CN108695373A CN 108695373 A CN108695373 A CN 108695373A CN 201710226683 A CN201710226683 A CN 201710226683A CN 108695373 A CN108695373 A CN 108695373A
- Authority
- CN
- China
- Prior art keywords
- groove
- layer
- polysilicon
- metal
- semiconductor material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 69
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 42
- 239000002184 metal Substances 0.000 claims abstract description 33
- 229920005591 polysilicon Polymers 0.000 claims abstract description 27
- 239000011810 insulating material Substances 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims description 35
- 239000000758 substrate Substances 0.000 claims description 30
- 230000004888 barrier function Effects 0.000 claims description 9
- 239000002019 doping agent Substances 0.000 claims description 7
- 239000012774 insulation material Substances 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 8
- 239000004020 conductor Substances 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 239000002210 silicon-based material Substances 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 6
- 230000000903 blocking effect Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000009527 percussion Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0646—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a kind of semiconductor devices, different conduction-types semi-conducting material is arranged between groove, top setting conductive material metal or polysilicon in the trench, lower part setting conductive material metal or polysilicon in the trench, insulating layer is arranged in trenched side-wall, and insulating materials is arranged between upper and lower conductive material;Semiconductor device of the present invention reduces drift layer vertex and bottom point peak value electric field, and multiple peak value electric fields are arranged in drift layer, and realizing reduces conducting resistance and simplified manufacturing method.
Description
Technical field
The present invention relates to a kind of semiconductor device, semiconductor device of the present invention is Schottky rectifying device and MOSFET
Foundation structure.
Background technology
Semiconductor power device, such as field effect transistor switch device, IGBT or Schottky rectifying device it is expected low electric conduction
Resistance and high blocking voltage.There has been proposed new constructions thus for accomplishing this.
Including the charge compensation structure for being alternately arranged different conducting semiconductor materials is introduced in device, change is partly led
Body material field distribution realizes ideal rectangle field distribution, and realizes broached-tooth design on rectangle electric field top, realizes device
The low on-resistance of part or high blocking voltage.
This structure is harsh for the requirement of different semi-conducting material charge compensations, needs more abundant charge compensation, otherwise shadow
The realization of the breakdown reverse voltage of Chinese percussion instrument part;This charge compensation structure is easy to have electric field point in semi-conducting material top bottom end
Peak, it is suppressed that the distributed rectangular of device electric fields;This charge compensation structure is by semi-conducting material doping concentration itself and depletion layer phase
Contradictory limitation is mutually overlapped, the sharp pointed tooth of broached-tooth design electric field is inhibited to be formed.
Invention content
Needle of the present invention provides a kind of semiconductor device.
A kind of semiconductor device, substrate layer are the first conducting semiconductor material of high-concentration dopant;Drift layer is located at substrate
It is the first conducting semiconductor material on layer;Multiple grooves are located on substrate layer and run through drift layer, and trenched side-wall setting is exhausted
Edge material layer, metal or polysilicon is arranged in upper and lower part setting metal or polysilicon, groove internal upper part and lower part in the trench
Between be isolated by insulating materials, lower metal or polysilicon are connected with substrate layer in groove;Wherein polysilicon is including being highly concentrated
Degree doping or low concentration doping polysilicon, polysilicon include for N-type or p-type DOPOS doped polycrystalline silicon;Groove internal upper part polysilicon, including
It is that high-concentration dopant first is conductive or the second conductive polycrystalline silicon lower part is the second conductive polycrystalline silicon of low concentration doping for top;Xiao Te
Base barrier junction, layer surface of drifting about between groove;Second conducting semiconductor material, between drift layer and groove, second
Conducting semiconductor material top is not contacted with schottky barrier junction, and the second conducting semiconductor material lower part is set less than lower part in groove
Metal or polysilicon upper surface are set, the second conducting semiconductor material lower part includes not contacted with substrate layer;Trenched side-wall setting
The insulating materials being arranged between metal or polysilicon up and down in insulation material layer and groove includes for different insulative material, such as groove
Side wall is silica, is silicon nitride in groove;Upper surface electrode metal, upper surface electrode metal connect schottky barrier junction and
Groove internal upper part metal or polysilicon;Lower surface electrode metal is located at the substrate layer back side.
A kind of semiconductor device, substrate layer are the first conducting semiconductor material of high-concentration dopant;Drift layer is located at substrate
It is the first conducting semiconductor material on layer;Multiple grooves are located on substrate layer and run through drift layer, and trenched side-wall setting is exhausted
Edge material layer, metal or polysilicon is arranged in upper and lower part setting metal or polysilicon, groove internal upper part and lower part in the trench
Between be isolated by insulating materials, lower metal or polysilicon are connected with substrate layer in groove;PN junction drifts about between groove
Layer surface;Second conducting semiconductor material, between drift layer and groove, the second conducting semiconductor material top not with groove
Between drift about layer surface PN junction interfacial contact, the second conducting semiconductor material lower part is less than lower part setting metal or polycrystalline in groove
Silicon upper surface, the second conducting semiconductor material lower part include not contacted with substrate layer;Metal or polysilicon is arranged in groove internal upper part
Independent triggers electrode can be used as.Semiconductor device of the present invention is the foundation structure for manufacturing MOSFET.
The first conducting semiconductor material and the second conducting semiconductor material is arranged in semiconductor device of the present invention between groove,
And conductive material metal or polysilicon is arranged in upper and lower part in the trench;Semiconductor device reduction drift of the present invention under reverse biased
Layer vertex and bottom point peak value electric field are moved, and multiple peak value electric fields are set in drift layer, reduces conducting resistance, simplifies manufacturer
Method.
Description of the drawings
Fig. 1 is the Schottky semiconductor device diagrammatic cross-section of the present invention.
Fig. 2 is second of Schottky semiconductor device diagrammatic cross-section of the present invention.
Fig. 3 is the third Schottky semiconductor device diagrammatic cross-section of the present invention.
Fig. 4 is the PN junction semiconductor device diagrammatic cross-section of the present invention.
Fig. 5 is second of PN junction semiconductor device diagrammatic cross-section of the present invention
Wherein, 1, substrate layer;2, drift layer;3, the second conducting semiconductor material;5, DOPOS doped polycrystalline silicon;6, silica;
7, schottky barrier junction.
Specific implementation mode
Fig. 1 is the Schottky semiconductor device diagrammatic cross-section of the present invention, and substrate layer 1 is high-concentration dopant N conduction types
Semiconductor silicon material;Drift layer 2 is located on substrate layer 1, is N conductive type semiconductor silicon materials;Multiple grooves are located at drift
It is contacted with substrate layer in layer, the second conducting semiconductor material 3 is P conductive type semiconductor silicon materials, is located at groove and drift layer 2
Between, it is not contacted with drift layer upper surface;DOPOS doped polycrystalline silicon 5 setting up and down in groove, DOPOS doped polycrystalline silicon 5 are arranged with trenched side-wall
Insulating materials silica 6 is isolated, and insulating materials silica 6, which is arranged, in upper and lower DOPOS doped polycrystalline silicon 6 is isolated;Schottky barrier junction 7,
2 surface of drift layer between groove;Upper surface electrode metal is set on this basis, and upper surface electrode metal connects Schottky
Barrier junction and groove internal upper part DOPOS doped polycrystalline silicon, lower surface electrode metal are located at the substrate layer back side, form Schottky rectifier
Part.
Fig. 2 is second of Schottky semiconductor device diagrammatic cross-section of the present invention, and structure is similar with Fig. 1, difference
Technical characteristic is that 5 upper surface of DOPOS doped polycrystalline silicon is arranged less than lower part in groove in 3 upper surface of the second conducting semiconductor material.Fig. 3 is
The third Schottky semiconductor device diagrammatic cross-section of the present invention, structure is similar with Fig. 1, distinguishing feature second
3 upper surface of conducting semiconductor material is higher than 5 lower surface of groove internal upper part setting DOPOS doped polycrystalline silicon.
Fig. 4 is the PN junction semiconductor device diagrammatic cross-section of the present invention, and substrate layer 1 is high-concentration dopant N conduction types half
Conductor silicon materials;Drift layer 2 is located on substrate layer 1, is N conductive type semiconductor silicon materials;Multiple grooves are located at drift layer
In contacted with substrate layer, between groove drift layer upper surface be arranged the second conductive semiconductor silicon materials formed PN junction;Second is conductive
Semi-conducting material 3 be P conductive type semiconductor silicon materials, between groove and drift layer 2, not with drift layer upper surface PN junction
Interfacial contact;DOPOS doped polycrystalline silicon 5 setting up and down in groove, DOPOS doped polycrystalline silicon 5 and trenched side-wall setting insulating materials silica 6
Isolation, insulating materials silica 6, which is arranged, in upper and lower DOPOS doped polycrystalline silicon 6 is isolated;Upper and lower surface electrode metal is set on this basis,
It sets groove internal upper part DOPOS doped polycrystalline silicon 5 to independent triggers electrode, such as gate electrode, forms switch mosfet device basis knot
Structure.Above-described embodiment can be applied to IGBT, set substrate layer to P-type conduction semi-conducting material, while groove and drift is arranged
Second conducting semiconductor material 3 is not contacted with substrate layer between moving layer 2.
Fig. 5 is second of PN junction semiconductor device diagrammatic cross-section of the present invention, and structure is similar with Fig. 4, distinguishes skill
Art is characterized as 3 upper surface of the second conducting semiconductor material less than setting DOPOS doped polycrystalline silicon 5 upper surface in lower part in groove.
The present invention is elaborated by examples detailed above, while other examples can also be used to realize the present invention, the present invention not office
It is limited to above-mentioned specific example, therefore the present invention is limited by attached claim scope.
Claims (3)
1. a kind of semiconductor device, it is characterised in that:Including:
Substrate layer is the first conducting semiconductor material of high-concentration dopant;
Drift layer is located on substrate layer, is the first conducting semiconductor material;
Multiple grooves are located on substrate layer and run through drift layer, and insulation material layer is arranged in trenched side-wall, and top is under in the trench
Metal or polysilicon is arranged in portion, is isolated by insulating materials between groove internal upper part and lower part setting metal or polysilicon, groove
Interior lower metal or polysilicon are connected with substrate layer;
Schottky barrier junction, layer surface of drifting about between groove;
Second conducting semiconductor material, between drift layer and groove, the second conducting semiconductor material top not with Schottky
Barrier junction contacts, and the second conducting semiconductor material lower part is less than lower part setting metal or polysilicon upper surface in groove;
Upper surface electrode metal connects schottky barrier junction and groove internal upper part metal or polysilicon;
Lower surface electrode metal is located at the substrate layer back side.
2. a kind of semiconductor device, it is characterised in that:Including:
Substrate layer is the first conducting semiconductor material of high-concentration dopant;
Drift layer is located on substrate layer, is the first conducting semiconductor material;
Multiple grooves are located on substrate layer and run through drift layer, and insulation material layer is arranged in trenched side-wall, and top is under in the trench
Metal or polysilicon is arranged in portion, is isolated by insulating materials between groove internal upper part and lower part setting metal or polysilicon, groove
Interior lower metal or polysilicon are connected with substrate layer;
PN junction, layer surface of drifting about between groove;
Second conducting semiconductor material, between drift layer and groove, the second conducting semiconductor material top not with groove it
Between drift about layer surface PN junction interfacial contact, the second conducting semiconductor material lower part is less than lower part setting metal or polysilicon in groove
Upper surface.
3. semiconductor device as claimed in claim 2, it is characterised in that:The groove internal upper part setting metal or polysilicon are made
For independent triggers electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710226683.6A CN108695373A (en) | 2017-04-09 | 2017-04-09 | A kind of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710226683.6A CN108695373A (en) | 2017-04-09 | 2017-04-09 | A kind of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108695373A true CN108695373A (en) | 2018-10-23 |
Family
ID=63843103
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710226683.6A Withdrawn CN108695373A (en) | 2017-04-09 | 2017-04-09 | A kind of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108695373A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040256690A1 (en) * | 2001-10-17 | 2004-12-23 | Kocon Christopher Boguslaw | Schottky diode using charge balance structure |
| US20060065923A1 (en) * | 2004-09-24 | 2006-03-30 | Infineon Technologies Ag. | High-voltage-resistant semiconductor component having vertically conductive semiconductor body areas and a trench structure |
| US20080246096A1 (en) * | 2007-04-03 | 2008-10-09 | Denso Corporation | Semiconductor device including schottky barrier diode and method of manufacturing the same |
| CN103378171A (en) * | 2012-04-28 | 2013-10-30 | 朱江 | Groove Schottky semiconductor device and preparation method thereof |
-
2017
- 2017-04-09 CN CN201710226683.6A patent/CN108695373A/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040256690A1 (en) * | 2001-10-17 | 2004-12-23 | Kocon Christopher Boguslaw | Schottky diode using charge balance structure |
| US20060065923A1 (en) * | 2004-09-24 | 2006-03-30 | Infineon Technologies Ag. | High-voltage-resistant semiconductor component having vertically conductive semiconductor body areas and a trench structure |
| US20080246096A1 (en) * | 2007-04-03 | 2008-10-09 | Denso Corporation | Semiconductor device including schottky barrier diode and method of manufacturing the same |
| CN103378171A (en) * | 2012-04-28 | 2013-10-30 | 朱江 | Groove Schottky semiconductor device and preparation method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20181023 |
|
| WW01 | Invention patent application withdrawn after publication |