CN108695233A - Semiconductor devices and its manufacturing method - Google Patents

Semiconductor devices and its manufacturing method Download PDF

Info

Publication number
CN108695233A
CN108695233A CN201710233250.3A CN201710233250A CN108695233A CN 108695233 A CN108695233 A CN 108695233A CN 201710233250 A CN201710233250 A CN 201710233250A CN 108695233 A CN108695233 A CN 108695233A
Authority
CN
China
Prior art keywords
layer
metal gate
gate electrode
work
semiconductor devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710233250.3A
Other languages
Chinese (zh)
Other versions
CN108695233B (en
Inventor
韩秋华
曾德强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201710233250.3A priority Critical patent/CN108695233B/en
Publication of CN108695233A publication Critical patent/CN108695233A/en
Application granted granted Critical
Publication of CN108695233B publication Critical patent/CN108695233B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The present invention provides a kind of semiconductor devices and its manufacturing method, and air gap is formed in the metal gate electrode layer side wall of metal gate stack structure, and the parasitic capacitance between thereby reducing metal gate electrode and the source-drain area conductive structure that is subsequently formed improves device performance.

Description

Semiconductor devices and its manufacturing method
Technical field
The present invention relates to ic manufacturing technology field more particularly to a kind of semiconductor devices and its manufacturing methods.
Background technology
With the continuous development of integrated circuit (integrated-circuit, IC) manufacturing technology, metal-oxide-half The characteristic size of conductor (Metal-Oxide-Semiconductor, MOS) device is also smaller and smaller.With the feature of MOS device Size enter 45nm technology nodes and it is following when, in order to significantly reduce gate tunneling current and gate resistance, eliminate polysilicon consumption Effect to the greatest extent improves device reliability, alleviates fermi level pinning effect, using high K (dielectric constant) gate dielectric layer/metal gate electricity The gate stack structure (high-K metal gate, HKMG) of pole replaces the gate stack of traditional silica/polysilicon folded Layer structure has become the common recognition of industry.
However, in the gate stack structure of current high-K gate dielectric layer and metal gate electrode, the vertical sidewall of gate openings On be equally covered with high-K gate dielectric layer and work-function layer, this causes the parasitic capacitance between source and drain contact hole and metal gate electrode to increase Add.And this can make device performance degradation, such as switching speed reduction, signal delay or power consumption increase etc..On the other hand, even if it is right In the not high device of performance requirement, it is also desirable to obtain low-power consumption, and therefore also be intended to reduce the parasitic capacitance.
Invention content
It is an object of the invention to a kind of semiconductor devices and its manufacturing methods, can reduce metal gate electrode and source-drain area Parasitic capacitance between conductive structure improves device performance.
To achieve the goals above, the present invention provides a kind of manufacturing method of semiconductor devices, includes the following steps:
The semiconductor substrate for being formed with the first interlayer dielectric layer on surface is provided, gold is formed in first inter-level dielectric Belong to gate stack structure, the metal gate stack structure includes metal gate electrode layer and is centered around the metal gate electrode layer The work-function layer of side wall, the top of the metal gate electrode layer are not higher than the top of the first interlayer dielectric layer, the work-function layer Top be less than the metal gate electrode layer top;
Sacrificial layer is formed at the top of the work-function layer, the top of the sacrificial layer is not higher than the metal gate electrode layer Top;
Capping layer is formed in the top of the metal gate electrode layer and sacrificial layer;
The sacrificial layer is removed, to form air gap between the capping layer and the work-function layer.
Optionally, the step of providing the semiconductor substrate include:
The semiconductor base for being formed with the first interlayer dielectric layer on surface is provided, top is formed in first inter-level dielectric The metal gate stack structure that portion is flushed with the first interlayer top of media, the metal gate stack structure includes metal gate Electrode layer and the work-function layer for being centered around the metal gate electrode layer side wall;
It is etched back to the metal gate electrode layer and the work-function layer, or is only etched back to the work-function layer, so that institute The top for stating work-function layer is less than the top of the metal gate electrode layer.
Optionally, when being etched back to the metal gate electrode layer and the work-function layer, the work-function layer is etched back to depth Degree be the metal gate electrode layer be etched back to depth 2 times~6 times.
Optionally, the sacrificial layer is the organic polymer that can be thermally decomposed.
Optionally, the organic polymer can thermally decompose in 300 DEG C of temperatures above.
Optionally, the step of forming the sacrificial layer include:In first interlayer dielectric layer and the metal gates Deposited sacrificial layer on the surface of laminated construction;The sacrificial layer is etched back to until the top of the sacrificial layer is not higher than the metal Gate electrode layer.
Optionally, the sacrificial layer is etched back to using dry etch process.
Optionally, the capping layer includes the oxide layer sequentially formed on the metal gate electrode layer and sacrificial layer surface And nitration case.
Optionally, the forming process of the capping layer includes:
It is less than 200 DEG C of technique using temperature, in first interlayer dielectric layer, the sacrificial layer and the metal gate The top of pole laminated construction forms oxide layer;
The cvd nitride layer on the surface of the oxide layer;
Nitration case and oxide layer extra above first interlayer dielectric layer are removed using CMP process.
Optionally, by annealing process, ultraviolet light technique or infrared light radiation process to remove the sacrificial layer, To form the air gap.
Optionally, when providing the semiconductor substrate for being formed with the first interlayer dielectric layer on surface, the work-function layer, which is removed, to be covered It covers other than the side wall of the metal gate electrode layer, also partly covers or be completely covered the bottom of the metal gate electrode layer, and There is high-K gate dielectric layer between the work-function layer and the semiconductor substrate.
Optionally, the semiconductor devices is fin transistor.
Optionally, after forming the air gap, the is formed on the surface of the capping layer and the first interlayer dielectric layer Two interlayer dielectric layers.
Optionally, the dielectric constant of first interlayer dielectric layer and the second interlayer dielectric layer is below the capping layer Dielectric constant.
The present invention also provides a kind of semiconductor devices, including:
Semiconductor substrate;
First interlayer dielectric layer is located on the semiconductor substrate surface;
Metal gate stack structure is located in first interlayer dielectric layer, and the metal gate stack structure includes Metal gate electrode layer and the work-function layer for being centered around the metal gate electrode layer side wall, the top of the metal gate electrode layer is not Higher than the top of first interlayer dielectric layer, the top of the work-function layer is less than the top of the metal gate electrode layer;
Capping layer is located above the metal gate electrode layer, and forms air gap between the work-function layer.
Optionally, the capping layer includes the oxide layer sequentially formed in the metal gate electrode layer surface and nitridation Layer.
Optionally, the work-function layer is in addition to the side wall for covering the metal gate electrode layer, also part covering or complete The bottom of metal gate electrode layer described in all standing, and also have high-K gate dielectric between the work-function layer and the semiconductor substrate Layer.
Optionally, the semiconductor devices further includes being covered on the capping layer and the first interlayer dielectric layer surface The second interlayer dielectric layer.
Optionally, the dielectric constant of first interlayer dielectric layer and the second interlayer dielectric layer is below the capping layer Dielectric constant.
Optionally, the semiconductor devices is fin transistor.
Compared with prior art, technical scheme of the present invention has the following technical effects:
1, by the space that the difference in height of the work-function layer of metal gate stack structure and metal gate electrode layer is formed Formed air gap, to the conductive structures such as the contact hole of metal gate electrode and source-drain area, metal silicide or metal interconnecting wires it Between form air gap, greatly reduce the parasitic capacitance between source and drain contact hole and metal gate electrode, improve device performance.
2, it is higher than the envelope of the first interlayer dielectric layer and the second interlayer dielectric layer by the dielectric constant formed above air gap Cap rock, for example, low temperature oxide layer and silicon nitride layer laminated construction, ensure air gap at mechanical performance, to ensure the electricity of device Learn stability and reliability.
Description of the drawings
Fig. 1 is the manufacturing method flow chart of the semiconductor devices of the specific embodiment of the invention;
Fig. 2A to 2H is the device profile structural representation in the manufacturing method of the semiconductor devices of the specific embodiment of the invention Figure.
Specific implementation mode
To avoid influence of the metal material of metal gate electrode to MOS device other structures, in the prior art, metal gate electricity Pole substitutes (replacement gate) technique system with the metal gate stack structure generally use grid that high-K gate dielectric layer is formed Make.In the process, before source-drain area is formed, the virtual grid being made of polysilicon are formed in gate electrode position to be formed first Pole (dummy gate), the dummy gate form the process such as source-drain area for autoregistration;After forming source-drain area, meeting The dummy gate is removed, and gate openings are formed in the position of dummy gate;Then, it is sequentially filled in the gate openings High-K gate dielectric layer, work-function layer (being used for adjusting threshold voltage), metal gate electrode layer, to metal gate stack structure;It Afterwards, the device surface in metal gate stack structure and its both sides deposits the inter-level dielectric for making source-drain area conductive structure Layer, and the conductive structures such as contact hole, contact plunger or M0 layer metal interconnecting wires for being directed at source-drain area are made using interlayer dielectric layer. Since metal gate electrode is made again after source-drain area is formed, this makes the quantity of subsequent technique be reduced, and avoids gold Belong to the problem of material is unsuitable for carrying out high-temperature process.
However, make MOS device there are still many problems using above-mentioned gate replacement technique, with grid length into One step reduces, these problems can become more serious.For example, the metal gate stack structure formed in the gate replacement technique In, it is equally covered with high-K gate dielectric layer and work-function layer on the vertical sidewall of the gate openings, this leads to source-drain area and metal Parasitic capacitance between gate electrode increases.Device performance can be influenced without necessary parasitic capacitance increase.
Semiconductor devices provided by the invention and its manufacturing method, core concept are, in metal gate stack structure After formation, for make source-drain area conductive structure interlayer dielectric layer formed before, using in metal gate stack structure Space that difference in height between metal gate electrode layer and work-function layer is formed makes air gap, to come reduce metal gate electrode and Parasitic capacitance between source-drain area improves device performance.
To make the purpose of the present invention, feature be clearer and more comprehensible, the specific implementation mode of the present invention is made below in conjunction with the accompanying drawings Further instruction, however, the present invention can be realized with different forms, should not be to be confined to the embodiment described.
Referring to FIG. 1, the present embodiment provides a kind of manufacturing method of semiconductor devices, include the following steps:
S1 provides the semiconductor substrate for being formed with the first interlayer dielectric layer on surface, is formed in first inter-level dielectric There is a metal gate stack structure, the metal gate stack structure includes metal gate electrode layer and is centered around the metal gate electricity The work-function layer of pole layer side wall, the top of the metal gate electrode layer are not higher than the top of the first interlayer dielectric layer, the work content Several layers of top is less than the top of the metal gate electrode layer;
S2 forms sacrificial layer at the top of the work-function layer, and the top of the sacrificial layer is not higher than metal gate electricity The top of pole layer;
S3 to form capping layer in the top of the metal gate electrode layer and sacrificial layer;
S4 removes the sacrificial layer, to form air gap between the capping layer and the work-function layer.
A is please referred to Fig.2, in step sl, is provided with the first interlayer dielectric layer 201 and metal gate stack structure (packet Include metal gate electrode layer 205, work-function layer 204, high-K gate dielectric layer 203 and side wall 202) semiconductor substrate the step of wrap It includes:
S11, provides semiconductor base 200, and the semiconductor base 200 can be known any class in electronic field Type, such as body silicon, semiconductor on insulator (SOI), silicon germanium on insulator, FIN types or any other type.Preferably FIN types, The i.e. described semiconductor base 200 has the fin (FIN) perpendicular to surface, and making FinFET using fin, (i.e. fin is brilliant Body tube device, the device are 3 D stereos), to improve device performance, the specific forming process of fin:In semiconductor base 200 The certain thickness semiconductor epitaxial layers of epitaxial growth (such as Si layers of germanium silicon sige layer or silicon) on surface, vertical etch this partly lead Prolong in vitro to form the fin of FinFET, the thickness of epitaxial semiconductor layer can be controlled according to the design needs, to control fin Highly.Later, it by known depositing operation, such as CVD (chemical vapor deposition), atomic layer deposition, sputtering, is partly led described Gate dielectric layer, polysilicon layer and silicon nitride mask layer are sequentially depositing on 200 surface of body substrate, the deposition thickness of polysilicon layer determines The height for the metal gates stepped construction being subsequently formed, gate dielectric layer can be silica, silicon nitride, silicon oxynitride or Dielectric constant K is more than the high K dielectric of silica.
S12, by the spin coating photoresist on silicon nitride mask layer, and by including exposed and developed photoetching process Photoresist layer is formed into gate pattern, later using photoresist as mask, is covered firmly by dry method etch technology etch silicon nitride Gate pattern is transferred on silicon nitride hard mask layer by film layer, and removes photoresist layer;Then, with silicon nitride hard mask layer Polysilicon layer, gate dielectric layer are sequentially etched by dry etch process from top to bottom for mask, it is empty to be formed on fin Quasi- gate structure;
S13, by chemical vapor deposition method, on the semiconductor base 200 and the dummy gate structure surface Spacer material is deposited, and the spacer material is etched by dry etch process, the dummy gate structure is centered around to be formed The side wall 202 of side wall, silicon nitride hard mask layer protected in 202 etching process of side wall below dummy gate structure;It Afterwards, silicon nitride hard mask layer is removed by CMP process etc..
S14 is mask with dummy gate structure and side wall 202, by 202 both sides of the dummy gate structure and side wall Fin in directly carry out source-drain area ion implanting (including be lightly doped and heavy doping) and annealing activation, form the source-drain area; Alternatively, first passing through dry etch process or by dry etch process combination wet-etching technology, in the dummy gate The fin of 202 both sides of structure and side wall performs etching, and forms source and drain groove, uses selective epitaxial process in the source and drain later Groove carries out the semiconductor layer extension different from fin material, and carries out ion to the semiconductor layer of extension during extension and mix Miscellaneous or delay carry out ion implanting to semiconductor layer outside, annealing is to form the source-drain area, such as when fin is Si, source The semiconductor layer for leaking groove extension can be that either SiC (carbon silicon) is when fin is SiGe SiC to SiGe, outside source and drain groove The semiconductor layer prolonged can be Si.
S15, by known depositing operation, such as CVD (chemical vapor deposition), atomic layer deposition, sputtering, described half Conductor substrate, dummy gate structure and 202 surface of side wall deposit first interlayer dielectric layer 201, and planarize described the One interlayer dielectric layer, 201 top, until exposing the polysilicon layer surface of the dummy gate structure.First interlayer dielectric layer 201 be low-K dielectric material, and dielectric constant (can be less than 2.0) is less than silica, for example, organic porous material etc..
S16, using wet etching or dry etch process or the technique of dry etching combination wet etching, described in removal The polysilicon layer of dummy gate structure, alternatively, the polysilicon layer of the dummy gate structure and the gate dielectric layer of lower section are removed, with Form gate openings.
S17, remaining gate dielectric layer is situated between for high K after removing the polysilicon layer of the dummy gate structure in step S16 When matter, work-function layer 204 and metal gate electrode layer 205, the grid can be directly sequentially formed in the gate openings The gate dielectric layer of open bottom is as high-K gate dielectric layer 203.And works as in step S16 and remove completely dummy gate structure or step When to remove remaining gate dielectric layer after the polysilicon layer of the dummy gate structure in rapid S16 be not high K dielectric, in the grid High-K gate dielectric layer 203, work-function layer 204 and metal gate electrode layer 205 are sequentially depositing in opening.In the gate openings While being sequentially depositing work-function layer 204 and metal gate electrode layer 205, in the side wall 202 and the first interlayer dielectric layer 201 The work-function layer 204 and metal gate electrode layer 205 can also be formed on top, and chemical-mechanical planarization (CMP) hereafter may be used Technique, carries out the top flattening of metal gate electrode layer 205, until the top of the first interlayer dielectric layer 201 is exposed, to shape At the metal gate stack structure flushed with the top of the first interlayer dielectric layer 201.
High-K gate dielectric layer 203 may include hafnium oxide, hafnium silicon oxide, lanthana, zirconium oxide, zirconium silicon oxide, titanium oxide, In tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, yttrium oxide, aluminium oxide, lead oxide scandium tantalum and lead niobate zinc extremely Few one kind, particularly preferably hafnium oxide, zirconium oxide, titanium oxide and aluminium oxide.High-K gate dielectric layer 203 can by using The deposition methods such as chemical vapor deposition (CVD), low pressure chemical vapor deposition, atomic layer CVD or physical vapour deposition (PVD) (PVD) technique are formed in On whole side walls of gate openings bottom and gate openings.Preferably, anti-so as to control using atomic layer CVD process Flow velocity, the temperature and pressure for answering the metal oxide precursor (for example, metal chloride) and steam in device, in gate openings Atom smooth interface and ideal thickness are generated between surface and high-K gate dielectric layer 203.
Work-function layer 204 can be formed by atomic layer CVD process or PVD process.Work-function layer 204 may include one layer or Multilayer, when being used to form NMOS transistor, it should which (electronegativity is worth small using enough elements with relatively low electronegativity In about 1.7), such as lanthanide series metal, scandium, zirconium, hafnium, aluminium, titanium, tantalum, niobium, tungsten and other elements to come in handy include alkali metal And alkaline-earth metal, wherein alkali metal refers to the metallic element of the 1st i.e. I A races of row in the horizontal type periodic table of elements, is opened from the 2nd period Begin, including No. 3 element lithiums (Li), No. 11 elements of Na (Na), No. 19 Element Potassiums (K), No. 37 element rubidiums (Rb), No. 55 element caesiums (Cs), No. 87 element franciums (Fr);Alkaline-earth metal refers to the metallic element of the 2nd i.e. II A races of row in the horizontal type periodic table of elements, from the 2nd Period, including No. 4 element berylliums (Be), No. 12 element magnesium (Mg), No. 20 element calciums (Ca), No. 38 elements strontiums (Sr), No. 56 Elements Barium (Ba), No. 88 element franciums (Ra), it is seen then that the work-function layer 204 for being used to form NMOS transistor can be titanium nitride, nitrogen Change thallium, titanium-aluminium alloy, TiAlN and tungsten nitride, and when forming PMOS transistor, it should using enough with relatively high Electronegativity element (electronegativity value is greater than about 2.8), such as nitrogen, chlorine, oxygen, fluorine and bromine, it is seen then that be used to form PMOS transistor Work-function layer 204 can be titanium nitride, nitridation thallium and tungsten nitride etc..
Metal gate electrode layer 205 can pass through the formation such as atomic layer CVD process, PVD process or sputter deposition craft, metal Any conductive material containing metal of gate electrode layer 205 (that is, gate electrode not comprising a large amount of silicon or polysilicon) may include Alloy that aluminium, copper, silver, gold, platinum, nickel, titanium, cobalt, thallium, tantalum, tungsten, ruthenium, palladium, molybdenum, niobium and these elements and other elements are formed, Metal carbides (such as titanium carbide, zirconium carbide, ramet, tungsten carbide and carbonization thallium), metal nitride (such as tantalum nitride, nitrogen Change titanium, nitridation thallium), one kind or more in metal silicide (such as tungsten silicide, titanium silicide, cobalt silicide, nickle silicide, nitrogen silication thallium) Kind.
S18 please refers to Fig.2 B, can be to the metal gate electrode layer 205 and work-function layer 204 in metal gate stack structure It carries out different degrees of selectivity to be etched back to, the top of metal gate electrode layer 205 is made to be higher than the top of work-function layer 204 and is less than First interlayer dielectric layer, 201 top, forms grid and is etched back to slot, being etched back to technique can be with dry etching or wet etching, work content It is etched back to be etched back to depth 2 times that depth can be metal gate electrode layer 205~6 times, such as metal gate electrode for several layers 204 Layer 205 the depth that is etched back to be The depth that is etched back to of work-function layer 204 isTo metal In the case that gate electrode layer 205 and work-function layer 204 are etched back, the capping layer being subsequently formed is in metal gate electrode layer The part of 205 tops will not be higher by 201 top of the first interlayer dielectric layer;It in other embodiments of the invention, can also be only right Work-function layer 204 is etched back, and 205 top of metal gate electrode layer is kept to be flushed with 201 top of the first interlayer dielectric layer, after Part of the capping layer formed in continuous step S3 above metal gate electrode layer 205 can be higher by 201 top of the first interlayer dielectric layer, Be equivalent to dished cover, can also form air gap above work-function layer, and finally reduce metal gate electrode and source-drain area conductive structure it Between parasitic capacitance, later can also by formed be covered on the first interlayer dielectric layer 201 and capping layer have planarization Second interlayer dielectric layer of top surface, to provide flat artistic face for subsequent technique.
In step s 2, first, C is please referred to Fig.2, using low temperature chemical vapor deposition technique in the first interlayer dielectric layer 201 surfaces and grid are etched back to deposited sacrificial layer 206 on rooved face, and sacrificial layer 206 is under 300 DEG C or more of heat decomposition temperature The decomposable asymmetric choice net material of thermal decomposition, usually organic polymer.The technological parameter for depositing the sacrificial layer includes:Power be 100W~ 2000W, methane gas flow are 5SCCM~100SCCM, and pressure is 5mtorr~100mtorr, process time 6s~100s.By In in 20nm technology nodes hereinafter, the thinner thickness of the work-function layer 204 of gate openings side wall, such asAnd Its work-function layer 204 is etched back to that depth is relatively large, and metal gate electrode layer 205 is formed with 204 difference in height of work-function layer at this time Space (or interval) narrower width, i.e. the space is the slit of high-aspect-ratio, heavy using low temperature chemical vapor deposition When the sacrificial layer 206 of the heat decomposable organic polymer material of product, sacrificial layer 206 is mainly covered in metal gate electrode layer 205, height 201 surface of K dielectric layer 203 and the first interlayer dielectric layer, and be easy to be covered in metal gate electrode layer 205 and work-function layer 204 Between spatially formation air gap, and due to the gravity of the heat decomposable organic polymer films of low temperature chemical vapor deposition make Sunk and filled in the space between metal gate electrode layer 205 and work-function layer 204 automatically with, mobility and adhesive, When sacrificial layer 206 is when 201 surface of the first interlayer dielectric layer has certain thickness, bottom may arrived work-function layer 204 Surface, it is also possible to not reach the surface of work-function layer 204 also and have certain interval, therefore metal with 204 surface of work-function layer The thickness of the work-function layer 204 of gate electrode layer side wall and the material and deposition thickness of sacrificial layer 206 determine work-function layer 204 With the presence or absence of interval between top and sacrificial layer 206, it is clear that when the thickness foot of the work-function layer 204 on metal gate electrode layer side wall When enough thick, sacrificial layer 206 can be generally deposited directly on the top surface of work-function layer 204, will not be with work-function layer 204 Top surface generates interval.
Then, D is please referred to Fig.2, the sacrificial layer 206 of deposition is etched back using dry etch process, until sacrificing The top of layer 206 is not higher than the top of the metal gate electrode layer 205, such as metal gate electrode layer is compared at the top of sacrificial layer 206 205 top is lowThe technological parameter for being etched back to the sacrificial layer 206 includes:Power is 100W~2000W, The flow of oxygen is 20SCCM~200SCCM, and pressure is 5mtorr~100mtorr, process time 6s~100s.Sacrificial layer 206 After being etched back to, have in the space only between the metal gate electrode layer 205 that grid is etched back in slot and work-function layer 204 Certain thickness sacrificial layer 206,201 surface of the first interlayer dielectric layer is also without sacrificial layer 206.
In step s3, first, E is please referred to Fig.2,200 DEG C of low temperature chemical vapor deposition work is less than using technological temperature Skill or atom layer deposition process etc., in first interlayer dielectric layer 201, the table of side wall 202 and metal gate electrode layer 205 It is sequentially depositing oxide layer 207 and nitration case 208 on face, is used as the material of capping layer, wherein at the top of sacrificial layer 206 significantly When less than 205 top of metal gate electrode layer, due to the limitation of bulk and technology ability, it is similar to sacrificial layer 206 Depositing operation, oxide layer 207 can be vacantly above sacrificial layer 206, and upper surface that can also be directly with sacrificial layer 206 connects It touches, the deposition thickness of the oxide layer 207 isThe deposition thickness of nitration case 208 isSo Afterwards, F is please referred to Fig.2, the extra nitration case in first interlayer dielectric layer, 201 top is removed using CMP process 208 and oxide layer 207 so that nitration case 208 and oxide layer 207 are only filled with and are etched back in slot in grid, and nitration case 208 Top surface is flushed with the top surface of the first interlayer dielectric layer 201, and capping layer is consequently formed, i.e. capping layer includes chemical machinery Remaining nitration case 208 and oxide layer 207 after flatening process.In other embodiments of the invention, the middle area of capping layer The top in domain can also be below or above the top of the first interlayer dielectric layer 201, and neighboring area is covered in the first inter-level dielectric On 201 surface of layer.
G is please referred to Fig.2, in step s 4, passes through annealing process either ultraviolet light technique or infrared light radiation work Skill makes remaining sacrificial layer thermally decompose, so that being formed between the oxide layer 207 of capping layer and the work-function layer 204 of lower section The air gap 209 of connection.Thermally decompose the required temperature of remaining sacrificial layer can according to the chemical deposition temperature of sacrificial layer and The thickness of sacrificial layer and change.On the one hand capping layer is used to form air gap 209, be on the other hand capable of providing and the first interlayer The artistic face that 201 top of dielectric layer flushes, and its dielectric constant is usually above 201 (generally dielectric of the first interlayer dielectric layer Constant be less than 2.0 low-K dielectric) and be subsequently formed the second interlayer dielectric layer (generally dielectric constant less than 2.0 low K Jie Matter), so as to play the role of supporting succeeding layer, to ensure the mechanical strength of device.Air gap 209 has lower dielectric normal Number, so as to reduce parasitic capacitance.
H is please referred to Fig.2, after forming the air gap 209, it is possible, firstly, to pass through the continuation such as chemical vapor deposition method The second inter-level dielectric is deposited on the capping layer (i.e. nitration case 208 and oxide layer 207) and 201 surface of the first interlayer dielectric layer Layer 210, the second interlayer dielectric layer 210 can be the low-K dielectric that dielectric constant is less than silica, and material can be with first layer Between dielectric layer 201 it is identical.Then, 210 He of the second interlayer dielectric layer being sequentially etched by dry etch process above source-drain area First interlayer dielectric layer 201, to form alignment source-drain area and expose the wire laying slot or contact hole on source-drain area surface;It connects It, depositing metal conductive material etc. in the wire laying slot or contact hole of formation, to form metal interconnecting wires (M0), metallic silicon Compound contacts the conductive structures 211 such as (contact) or contact plunger (plug), and conductive structure 211 connects with the source-drain area electricity It touches, for drawing source-drain area outward.
It should be noted that the sacrificial layer in above-described embodiment is heat decomposable organic polymer material, in the present invention Other embodiment in, when sacrificial layer be not heat decomposable material when, can also select can be by techniques such as wet etchings The material of removal, later to be removed by process selectivities such as wet etchings.
H is please referred to Fig.2, the present embodiment also provides a kind of semiconductor devices, can be fin transistor, can be common High-K metal gate transistor device, the semiconductor devices include semiconductor substrate 200, the first interlayer dielectric layer 201, metal gate Pole laminated construction, capping layer, the second interlayer dielectric layer 210 and conductive structure 211.
First interlayer dielectric layer 201 is located on 200 surface of the semiconductor substrate, is formed with to expose and described partly lead The gate openings on 200 surface of body substrate.Metal gate stack structure filling is in the gate openings of first interlayer dielectric layer 201 In, including metal gate electrode layer 205 and it is centered around the work-function layer 204 of 205 side wall of the metal gate electrode layer, high K successively Gate dielectric layer 203 and side wall 202, the top of the metal gate electrode layer 205 is not higher than first interlayer dielectric layer 201 Top, the top of the work-function layer 204 are less than the top of the metal gate electrode layer 205.In the present embodiment, the work function Layer 204 also partly covers or is completely covered the metal gate in addition to the side wall that the metal gate electrode layer 205 is completely covered The bottom of electrode layer 205, and also have high-K gate dielectric layer 203 between the work-function layer 204 and the semiconductor substrate 200.This Outside, it is also formed with source/drain region in the semiconductor substrate 200 of 202 both sides of side wall.
Capping layer in the present embodiment includes the oxide layer being sequentially coated on the surface of the metal gate electrode layer 205 207 and nitration case 208, and it is formed with air gap between the bottom of oxide layer 207 and the top of the work-function layer 204, work as metal When 205 top of gate electrode layer is less than the first interlayer dielectric layer 201, it is preferable that capping layer is located in the gate openings, and top It is flushed with the first interlayer dielectric layer 201, flat artistic face is provided for the formation of the second interlayer dielectric layer 210.Work as metal gate When 205 top of electrode layer is flushed with the first interlayer dielectric layer 201, capping layer is covered in the top of the gate openings, middle area Domain is contacted with 205 top of metal gate electrode layer, and fringe region is overlapped on 203 top of high-K gate dielectric layer, and capping layer top is higher than First interlayer dielectric layer, 201 top.
Second interlayer dielectric layer 210 is covered in the capping layer, side wall 202, high-K gate dielectric layer 203 and the first layer Between dielectric layer 201 surface on, the dielectric constant of first interlayer dielectric layer, 201 and second interlayer dielectric layer 210 is preferably It is below the dielectric constant of the capping layer, the parasitic capacitance of semiconductor devices is thus reduced, improves its performance.Conductive structure 211 are applied in the second interlayer dielectric layer 210 and the second interlayer dielectric layer 210, and the semiconductor of bottom and 202 both sides of side wall serves as a contrast Source/drain region electrical contact in bottom 200.
In conclusion the semiconductor devices and its manufacturing method of the present invention, the metal gate in metal gate stack structure Electrode layer side wall forms air gap, the parasitism electricity between thereby reducing metal gate electrode and the source-drain area conductive structure that is subsequently formed Hold, improves device performance.
Obviously, those skilled in the art can carry out invention spirit of the various modification and variations without departing from the present invention And range.If in this way, these modifications and changes of the present invention belong to the claims in the present invention and its equivalent technologies range it Interior, then the present invention is also intended to include these modifications and variations.

Claims (20)

1. a kind of manufacturing method of semiconductor devices, which is characterized in that include the following steps:
The semiconductor substrate for being formed with the first interlayer dielectric layer on surface is provided, metal gate is formed in first inter-level dielectric Pole laminated construction, the metal gate stack structure include metal gate electrode layer and are centered around the metal gate electrode layer side wall Work-function layer, the top of the metal gate electrode layer is not higher than the top of the first interlayer dielectric layer, the top of the work-function layer Portion is less than the top of the metal gate electrode layer;
Sacrificial layer is formed at the top of the work-function layer, the top of the sacrificial layer is not higher than the top of the metal gate electrode layer Portion;
Capping layer is formed in the top of the metal gate electrode layer and sacrificial layer;
The sacrificial layer is removed, to form air gap between the capping layer and the work-function layer.
2. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that provide the step of the semiconductor substrate Suddenly include:
There is provided and be formed with the semiconductor base of the first interlayer dielectric layer on surface, be formed in first inter-level dielectric top with The metal gate stack structure that the first interlayer top of media flushes, the metal gate stack structure includes metal gate electrode Layer and the work-function layer for being centered around the metal gate electrode layer side wall;
It is etched back to the metal gate electrode layer and the work-function layer, or is only etched back to the work-function layer, so that the work( The top of function layer is less than the top of the metal gate electrode layer.
3. the manufacturing method of semiconductor devices as claimed in claim 2, which is characterized in that be etched back to the metal gate electrode layer When with the work-function layer, the work-function layer is etched back to be etched back to depth 2 times that depth is the metal gate electrode layer ~6 times.
4. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that the sacrificial layer is that can thermally decompose Organic polymer.
5. the manufacturing method of semiconductor devices as claimed in claim 4, which is characterized in that the organic polymer can be 300 It is thermally decomposed in DEG C temperatures above.
6. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that the step of forming the sacrificial layer is wrapped It includes:The deposited sacrificial layer on the surface of first interlayer dielectric layer and the metal gate stack structure;It is etched back to described Sacrificial layer is until the top of the sacrificial layer is not higher than the metal gate electrode layer.
7. the manufacturing method of semiconductor devices as claimed in claim 6, which is characterized in that be etched back to using dry etch process The sacrificial layer.
8. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that the capping layer is included in the gold Belong to the oxide layer sequentially formed on the surface of gate electrode layer and sacrificial layer and nitration case.
9. the manufacturing method of semiconductor devices as claimed in claim 8, which is characterized in that the forming process packet of the capping layer It includes:
It is less than 200 DEG C of technique using temperature, it is folded in first interlayer dielectric layer, the sacrificial layer and the metal gates The top of layer structure forms oxide layer;
The cvd nitride layer on the surface of the oxide layer;
Nitration case and oxide layer extra above first interlayer dielectric layer are removed using CMP process.
10. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that pass through annealing process, ultraviolet lighting It penetrates technique or infrared light radiation process removes the sacrificial layer, to form the air gap.
11. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that provide and be formed with first on surface When the semiconductor substrate of interlayer dielectric layer, the work-function layer goes back part in addition to the side wall for covering the metal gate electrode layer The bottom of the metal gate electrode layer is covered or be completely covered, and is also had between the work-function layer and the semiconductor substrate High-K gate dielectric layer.
12. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that the semiconductor devices is fin Transistor.
13. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that after forming the air gap, The second interlayer dielectric layer is formed on the capping layer and the first interlayer dielectric layer surface.
14. the manufacturing method of semiconductor devices as claimed in claim 13, which is characterized in that first interlayer dielectric layer and The dielectric constant of second interlayer dielectric layer is below the dielectric constant of the capping layer.
15. a kind of semiconductor devices, which is characterized in that including:
Semiconductor substrate;
First interlayer dielectric layer is located on the semiconductor substrate surface;
Metal gate stack structure is located in first interlayer dielectric layer, and the metal gate stack structure includes metal gate The top of electrode layer and the work-function layer for being centered around the metal gate electrode layer side wall, the metal gate electrode layer is not higher than institute The top of the first interlayer dielectric layer is stated, the top of the work-function layer is less than the top of the metal gate electrode layer;
Capping layer is located above the metal gate electrode layer, and forms air gap between the work-function layer.
16. semiconductor devices as claimed in claim 15, which is characterized in that the capping layer is included in the metal gate electrode The oxide layer and nitration case sequentially formed in layer surface.
17. semiconductor devices as claimed in claim 15, which is characterized in that the work-function layer is electric except the metal gate is covered Other than the side wall of pole layer, also partly cover or be completely covered the bottom of the metal gate electrode layer, and the work-function layer with There is high-K gate dielectric layer between the semiconductor substrate.
18. semiconductor devices as claimed in claim 15, which is characterized in that the semiconductor devices further include be covered in it is described The second interlayer dielectric layer on capping layer and the first interlayer dielectric layer surface.
19. semiconductor devices as claimed in claim 18, which is characterized in that first interlayer dielectric layer and the second interlayer are situated between The dielectric constant of matter layer is below the dielectric constant of the capping layer.
20. the semiconductor devices as described in any one of claim 15 to 19, which is characterized in that the semiconductor devices is fin Formula transistor.
CN201710233250.3A 2017-04-11 2017-04-11 Semiconductor device and method for manufacturing the same Active CN108695233B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710233250.3A CN108695233B (en) 2017-04-11 2017-04-11 Semiconductor device and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710233250.3A CN108695233B (en) 2017-04-11 2017-04-11 Semiconductor device and method for manufacturing the same

Publications (2)

Publication Number Publication Date
CN108695233A true CN108695233A (en) 2018-10-23
CN108695233B CN108695233B (en) 2021-01-01

Family

ID=63842514

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710233250.3A Active CN108695233B (en) 2017-04-11 2017-04-11 Semiconductor device and method for manufacturing the same

Country Status (1)

Country Link
CN (1) CN108695233B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112447742A (en) * 2019-08-30 2021-03-05 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN112635401A (en) * 2019-09-24 2021-04-09 长鑫存储技术有限公司 Method for forming transistor

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101241897A (en) * 2007-02-05 2008-08-13 台湾积体电路制造股份有限公司 IC structure and its forming method
US20150221742A1 (en) * 2014-02-04 2015-08-06 Samsung Electronics Co., Ltd. Semiconductor device and fabricating method thereof
CN105702714A (en) * 2014-12-16 2016-06-22 爱思开海力士有限公司 Semiconductor device having dual work function gate structure and manufacturing method thereof
US20160204262A1 (en) * 2014-01-28 2016-07-14 Kang-ill Seo Integrated circuit devices having air-gap spacers and methods of manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101241897A (en) * 2007-02-05 2008-08-13 台湾积体电路制造股份有限公司 IC structure and its forming method
US20160204262A1 (en) * 2014-01-28 2016-07-14 Kang-ill Seo Integrated circuit devices having air-gap spacers and methods of manufacturing the same
US20150221742A1 (en) * 2014-02-04 2015-08-06 Samsung Electronics Co., Ltd. Semiconductor device and fabricating method thereof
CN105702714A (en) * 2014-12-16 2016-06-22 爱思开海力士有限公司 Semiconductor device having dual work function gate structure and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112447742A (en) * 2019-08-30 2021-03-05 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN112447742B (en) * 2019-08-30 2023-09-19 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN112635401A (en) * 2019-09-24 2021-04-09 长鑫存储技术有限公司 Method for forming transistor

Also Published As

Publication number Publication date
CN108695233B (en) 2021-01-01

Similar Documents

Publication Publication Date Title
CN106206440B (en) CMOS forms source electrode and drain contact with closed growth technology method during integrating
CN104835780B (en) Semiconductor structure and its manufacturing method
JP4629674B2 (en) Metal gate manufacturing method
JP4767946B2 (en) Complementary metal oxide semiconductor integrated circuit with NMOS and PMOS transistors using different gate dielectrics
TWI397129B (en) A method of making a metal gate semiconductor device
CN104867967B (en) Semiconductor devices and its manufacture method
CN104701150B (en) The forming method of transistor
TWI517405B (en) Semiconductor device and fabrication method thereof
JP5090173B2 (en) Method of manufacturing a semiconductor device having a high dielectric constant gate dielectric layer and a silicide gate electrode
JP2007513498A (en) CVD Tantalum Compound for FET Gate Electrode (Chemical Vapor Deposition Method of Compounds Containing Ta and N and Semiconductor Field Effect Device)
TWI715218B (en) Semiconductor device and method manufacturing same
JP2008515190A (en) Metal gate electrode semiconductor device
CN101246850A (en) Insulated gate field effect transistor and method for manufacturing the same
CN108122744A (en) Semiconductor devices and its manufacturing method
CN106684116B (en) FinFET isolation structure and manufacturing method thereof
CN108807161A (en) The forming method of semiconductor device
CN107039335A (en) The forming method of semiconductor structure
CN103871895A (en) Method for fabricating a field effect transistor device
CN108878529A (en) Semiconductor devices and its manufacturing method
CN106571333A (en) Method of manufacturing semiconductor device
CN103681291B (en) A kind of forming method of metal silicide
CN108695233A (en) Semiconductor devices and its manufacturing method
TWI508296B (en) Methods of forming a replacement gate structure having a gate electrode comprised of a deposited intermetallic compound material
CN103839806B (en) Semiconductor device and method for manufacturing the same
JP2008103613A (en) Semiconductor device and manufacturing method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant