CN108683420A - A kind of lossless DSD signal number raising frequency algorithms - Google Patents
A kind of lossless DSD signal number raising frequency algorithms Download PDFInfo
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- CN108683420A CN108683420A CN201711260576.1A CN201711260576A CN108683420A CN 108683420 A CN108683420 A CN 108683420A CN 201711260576 A CN201711260576 A CN 201711260576A CN 108683420 A CN108683420 A CN 108683420A
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- digital
- raising frequency
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- bit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
- H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
-
- G—PHYSICS
- G10—MUSICAL INSTRUMENTS; ACOUSTICS
- G10L—SPEECH ANALYSIS OR SYNTHESIS; SPEECH RECOGNITION; SPEECH OR VOICE PROCESSING; SPEECH OR AUDIO CODING OR DECODING
- G10L19/00—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis
- G10L19/0017—Lossless audio signal coding; Perfect reconstruction of coded audio signal by transmission of coding error
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
- H03M3/436—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type
Abstract
The invention discloses a kind of digital raising frequency algorithms of lossless direct bit streaming digital (direct stream digital, DSD) audio signal.Entire number raising frequency system includes FIR digital low-pass filtering modules, digital interpolation module and Sigma Delta modulation modules.The single-bit DSD signals of input first pass through digital low-pass filtering module and are converted to more bit DSD signals, then the raising frequency of DSD signals is completed by digital interpolation module, finally after Sigma Delta modulation modules, more bit DSD signals are reverted into single-bit DSD signals again.The present invention can be lossless completion DSD signals digital raising frequency, to effectively reduce its proximal end (20kHz ~ 60kHz) noise, and entire algorithm is succinctly effective, realizes that required hardware cost is relatively low, can be widely applied in Audio Signal Processing industry.
Description
Technical field
The present invention relates to the processing of Audio Signal Processing field, especially DSD audio signals.
Background technology
A kind of audio that pulse code modulation scheme (pulse code modulation, PCM) is presently the most common is compiled
Code format, but there are huge bottlenecks for this coding modes of PCM, i.e. quantizing noise is evenly distributed in whole frequency ranges
, it also is difficult to reduce the quantizing noise in its base band even if continuing raising sample frequency.Therefore in order to improve this audio coding
Format obtains higher audio quality, Sony and PHILIPS Co. and proposes completely new audio coding formats jointly in 1996,
I.e. direct bit streaming digital (Direct Stream Digital, DSD) format, so-called DSD audio signals are to believe analogue audio frequency
Number the single-bit to be formed (0/1) signal is modulated by over-sampling (2.8224MHz) and Sigma-Delta, it can be with from its frequency spectrum
Find out, when signal frequency is more than 20kHz, noise has begun gradually to increase.To the human ear, it can not hear that frequency is big
It can relatively easy point in the design of the sound of 20kHz, rear end analog circuit.But for the analog circuit of rear end, 20kHz
If the excessive self-excitation for be easy to causeing amplifier of above noise or saturation.Current existing DSD signals since sample rate is relatively low,
Near-end noise is larger, is directly solved to DSD signals using existing chip AKM4490, the effect is unsatisfactory.Therefore needs pair
DSD signal frequency-raisings, to reduce its near-end noise.
Current existing solution is as shown in Figure 1.The single-bit DSD signals of input, first pass through digital decimation module, will
The sample frequency of signal is reduced to 44.1kHz from 2.8224MHz, and is converted into PCM signal.Using digital interpolation module
Sample frequency is increased to 5.6448MHz, finally after Sigma-Delta modulation modules, more bit DSD signals are turned again
It is changed to single-bit DSD signals.The structure have the shortcomings that two it is important, first as a result of 64 times of extraction and 128 times
Interpolation, it will cause to be mixed into noise in signal baseband, to reduce signal in base band (0~20kHz) precision.Second is whole
A processing procedure is excessively complicated and hardware resource consumption is more.
Invention content
The self-excitation of the amplifier of rear end analog circuit caused by near-end noise in order to solve DSD signals is excessive or saturation
Problem, and simplify the digital raising frequency algorithm of existing DSD signals, invent a kind of digital raising frequency calculation of lossless DSD signals
Method.
The present invention uses following technical scheme to solve above-mentioned technical problem：
A kind of lossless DSD signal number raising frequency algorithms, comprise the steps of：
Step 1：Single-bit DSD signals are converted into more bit DSD signals, and low-pass filtering is carried out to it；
Step 2：Filtered more bit DSD signals are subjected to digital interpolation raising frequency；
Step 3：More bit DSD signals after raising frequency are modulated by Sigma-Delta, revert to single-bit DSD again
Signal.
Step 1 is specially：The single-bit DSD signals of input are converted to by more bits using FIR digital low-pass filterings module
DSD signals, and filter out outer (signal frequency the is more than 20kHz) noise of part band.
Step 2 is specially：Digital interpolation mainly contains digital zero insertion and digital filtering.Digital zero insertion realizes each two
Digital signal is inserted into one zero, and the mirror image ingredient by digital filter by frequency more than pi/2 filters out, to realize twice
Digital raising frequency.And four times of even octuple digital raising frequencies are realized by multiple digital interpolation.
The beneficial effects of the invention are as follows：Due to the present invention be first single-bit DSD signals are converted to by digital filtering it is more
Bit DSD signals, then digital interpolation raising frequency is carried out, it is modulated finally by Sigma-Delta, more bit DSD signals are again extensive
It is single-bit DSD signals again.Entire processing procedure is more succinct effective compared to the raising frequency algorithm of existing DSD signals.Separately
Outside, since the present invention does not have digital decimation module, digital interpolation module need to only realize twice, four times of equimultiples it is lower
Digital raising frequency.Therefore compared with the raising frequency algorithm of existing DSD, the present invention can realize lossless DSD signal number raising frequencies.
Description of the drawings
Fig. 1 is the structure chart of the digital raising frequency algorithm of the DSD signals of the prior art；
Fig. 2 is a kind of structure chart of the digital raising frequency algorithm of lossless DSD signals of the present invention；
Fig. 3 is a kind of amplitude-frequency response of the FIR filter of the digital raising frequency algorithm of lossless DSD signals of the present invention；
Fig. 4 is a kind of different quantization effects of the FIR filter of the digital raising frequency algorithm of lossless DSD signals of the present invention
It answers；
Fig. 5 is a kind of amplitude-frequency response of the half-band filter of the digital raising frequency algorithm of lossless DSD signals of the present invention；
Fig. 6 is a kind of different quantization effects of the half-band filter of the digital raising frequency algorithm of lossless DSD signals of the present invention
It answers；
Fig. 7 is a kind of structure chart of the SDM modules of the digital raising frequency algorithm of lossless DSD signals of the present invention；
Fig. 8 be the present invention a kind of lossless DSD signals digital raising frequency algorithm raising frequency after DSD signal spectrums with not
The DSD signal spectrums of raising frequency compare.
Fig. 9 be the present invention a kind of lossless DSD signals digital raising frequency algorithm raising frequency after DSD signal spectrums with not
Amplification of the DSD signal spectrums comparison of raising frequency in 20kHz~120kHz.
Specific implementation mode
In the following with reference to the drawings and specific embodiments, the present invention is furture elucidated, it should be understood that these embodiments are merely to illustrate
It the present invention rather than limits the scope of the invention, after having read the present invention, those skilled in the art are to of the invention each
The modification of kind equivalent form falls within the application range as defined in the appended claims.
With reference to Fig. 2, a kind of digital raising frequency algorithm of lossless DSD signals, it comprises following steps：
Step 1：Single-bit DSD signals are converted into more bit DSD signals, and low-pass filtering is carried out to it；
Step 2：Filtered more bit DSD signals are subjected to digital interpolation raising frequency；
Step 3：More bit DSD signals after raising frequency are modulated by Sigma-Delta, revert to single-bit DSD again
Signal.
Step 1 is specially：The single-bit DSD signals of input are converted to by more bits using FIR digital low-pass filterings module
DSD signals, and filter out outer (signal frequency the is more than 20kHz) noise of part band.
Step 2 is specially：Digital interpolation mainly contains digital zero insertion and digital filtering.Digital zero insertion realizes each two
Digital signal is inserted into one zero, and the mirror image ingredient by digital filter by frequency more than pi/2 filters out, to realize twice
Digital raising frequency.And four times of even octuple digital raising frequencies are realized by multiple digital interpolation.
Implementation process of the present invention is described in detail below by a specific example.The example mainly completes
Twice of raising frequency of DSD signals includes mainly 3 modules, is FIR digital low-pass filtering modules respectively, digital interpolation module and
Sigma-Delta modulation modules.It is to illustrate to the detailed design of this 3 modules and divide the example test result below
Analysis.
The design of FIR digital low-pass filtering modules.Since DSD signal bandwidths are 20kHz, it can be considered to by filter
Passband width is arranged near 20kHz.Due to only can be to quantizing noise when more bit DSD signals are reverted to single-bit signal
It is molded, therefore the noise in more bit DSD signals outside band can also be taken as signal to handle, therefore is wanted when filter design
In view of attenuation outside a channel is big as possible.Finally, determine that the passband fluctuation of filter is 0.1dB, stopband attenuation 80dB distally declines
Subtract and be more than 100dB, cut-off frequecy of passband 40kHz, filter order is 709 ranks, and amplitude-frequency response is as shown in Figure 3.It considers
FPGA can only handle fixed-point number, it is therefore desirable to carry out quantification treatment to filter coefficient, be that its difference quantifies to it as shown in Figure 4
The influence of amplitude-frequency response.
The design of digital interpolation module.Digital zero insertion and digital filtering are mainly completed in digital interpolation module.Number filter
Wave device uses half-band filter, and design parameter is：Sample frequency 5.6448MHz, passband are 20KHz, passband by frequency
0.001dB is decayed to, the exponent number for the half-band filter that final design comes out is 14, and amplitude-frequency response is as shown in Figure 5.Such as Fig. 6 institutes
Show it is its influence of difference quantization to its amplitude-frequency response.
The design of Sigma-Delta modulation modules.Five rank monocycle Sigma-Delta modulation moulds are used in the design
Block, structure are as shown in Figure 7.The Sigma-Delta modulation modules are mainly by each structural coefficient, integrator and quantizer institute group
At.Following concrete structure coefficient is obtained by continuous emulation testing, in the realization of FPGA, integrator is in actual hardware
An adder and a d type flip flop can be equivalent in circuit.
It can obtain in fig. 8, the power spectrum of the DSD signals after raising frequency is with the power spectrum of original DSD signals (0 in base band
~20kHz) it is consistent substantially, this shows that precision of the signal in base band is not lost, and the DSD signals after raising frequency is close
Hold (20~60kHz) noise power significantly lower than original DSD signals, the noise for frequency more than 60kHz will be by rear end
Simulation low-pass filter filters out, therefore without considering.And can also be obtained from Fig. 9, the noises of former DSD signals be from
22kHz rises and significantly increases, and the noise of the DSD signals after twice of raising frequency is significantly increased from 40kHz, therefore such as
Fruit further increases the sample frequency of signal, and noise also will further extrapolate, and near-end noise can also further decrease.
Claims (3)
1. a kind of lossless DSD signal number raising frequency algorithms, it is characterised in that comprise the steps of：
Step 1：Single-bit DSD signals are converted into more bit DSD signals, and low-pass filtering is carried out to it；
Step 2：Filtered more bit DSD signals are subjected to digital interpolation raising frequency；
Step 3：More bit DSD signals after raising frequency are modulated by Sigma-Delta, revert to single-bit DSD signals again.
2. a kind of digital raising frequency algorithm of lossless DSD signals according to claim 1, the step 1 is further wrapped
It includes：The single-bit DSD signals of input are converted to more bit DSD signals by FIR digital low-pass filterings module, and are filtered out outside the band of part
(signal frequency is more than 20kHz) noise.
3. a kind of digital raising frequency algorithm of lossless DSD signals according to claim 1, the step 2 is further wrapped
It includes：Digital interpolation mainly contains digital zero insertion and digital filtering.Digital zero insertion realizes each two digital signal and is inserted into one
Zero, and the mirror image ingredient by digital filter by frequency more than pi/2 filters out, to realize twice of digital raising frequency.And
Four times of even octuple digital raising frequencies are realized by multiple digital interpolation.
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Cited By (2)
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| CN113744746A (en) * | 2021-09-07 | 2021-12-03 | 广州飞傲电子科技有限公司 | Audio data conversion playing method and device and audio player |
| CN114390400A (en) * | 2020-10-19 | 2022-04-22 | 深圳市欧思数码科技有限公司 | All-digital signal earphone amplifier applied to Soc chip |
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