CN108682693A - Thin film transistor (TFT) - Google Patents
Thin film transistor (TFT) Download PDFInfo
- Publication number
- CN108682693A CN108682693A CN201810519773.9A CN201810519773A CN108682693A CN 108682693 A CN108682693 A CN 108682693A CN 201810519773 A CN201810519773 A CN 201810519773A CN 108682693 A CN108682693 A CN 108682693A
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- layer
- tft
- film transistor
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- thin film
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- 239000010409 thin film Substances 0.000 title claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 239000004065 semiconductor Substances 0.000 claims abstract description 38
- 239000011347 resin Substances 0.000 claims abstract description 7
- 229920005989 resin Polymers 0.000 claims abstract description 7
- 239000010408 film Substances 0.000 claims abstract description 5
- 238000009413 insulation Methods 0.000 claims description 13
- 239000011810 insulating material Substances 0.000 claims description 6
- 239000007769 metal material Substances 0.000 claims description 5
- 230000003071 parasitic effect Effects 0.000 abstract description 12
- 230000001678 irradiating effect Effects 0.000 abstract 1
- 238000002161 passivation Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 7
- 239000011521 glass Substances 0.000 description 6
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 239000012528 membrane Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- WGLPBDUCMAPZCE-UHFFFAOYSA-N Trioxochromium Chemical compound O=[Cr](=O)=O WGLPBDUCMAPZCE-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 229910000423 chromium oxide Inorganic materials 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 230000001808 coupling effect Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000004064 dysfunction Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention provides a kind of thin film transistor (TFT), including：Substrate, and the grid, source electrode, drain electrode, semiconductor layer and the insulating layer that are set on substrate；Source electrode is located at same film layer with drain electrode, and is formed with gap between the two；Grid is set on substrate, and below the corresponding gap between source electrode and drain electrode；And black resin layer, it is set between substrate and semiconductor layer, also, the lightproof area of black resin layer at least covers semiconductor layer；Wherein, black resin layer blocks the light irradiating semiconductor layer into substrate for replacement gate, with reduction of gate line width, reduces grid and source electrode and/or the different layer overlapping area of drain electrode, and then reduce parasitic capacitance.
Description
Technical field
The present invention relates to display technology field more particularly to a kind of thin-film transistor structures.
Background technology
Thin film transistor (TFT) (Thin-film transistor, abbreviation TFT) is current liquid crystal display device (Liquid
Crystal Display, abbreviation LCD) and organic electroluminescence display device and method of manufacturing same (Organic Light-Emitting Diode,
Abbreviation OLED) in main driving element, be directly related to the developing direction of high performance flat display device.Therefore, whether
LCD display panel or OLED display panel usually all have tft array substrate.By taking LCD display panel as an example, it is mainly
It is made of array basal plate, a color membrane substrates and the liquid crystal layer that is configured between array substrate and color membrane substrates, work is former
Reason is to apply driving voltage by the public electrode on the corresponding thin film transistor (TFT) of array substrate and color membrane substrates, to control liquid
The light refraction of backlight module is out generated picture by the deflection of liquid crystal molecule in crystal layer.
In display panel, backlight is injected below array substrate, due to the amorphous silicon semiconductor layer of thin film transistor (TFT)
Light irradiation will produce electron-hole pair, will cause light leakage current, thus in design, gate metal as bottom gate, while
It is the shielding layer of semiconductor layer, it is contemplated that gate metal is overlapping with semiconductor layer, need to usually design line width wider.So
And the increase of grid line width so that the overlapping area between grid and source/drain increases, to which parasitic capacitance (Cgs) also increases,
Especially in the electrode for being connected to this one side of pixel electrode, since capacitance coupling effect causes Feed through voltages in panel
(feed-trough voltage), and Cgs is bigger, Feed through voltages are bigger, directly result in pixel electrode voltage positive-negative polarity not
Symmetry, and cause to flicker bad.Meanwhile the presence of Cgs also results in IS (Image Sticking, ghost), Crosstalk
Series of displays such as (crosstalks) are bad.
In conclusion the thin film transistor (TFT) of the prior art, grid for block into the light of substrate and be designed with compared with
Big line width has larger overlapping area, and then increases parasitic capacitance between grid and source/drain, and then influences display product
Matter.
Invention content
The present invention provides a kind of thin film transistor (TFT), can shield amorphous silicon semiconductor layer irradiated to avoid by light, simultaneously
Grid line width can be reduced, to reduce the overlapping area between grid and source/drain, and then reduce parasitic capacitance；It is existing to solve
The thin film transistor (TFT) of technology, grid have larger line width, between source/drain have larger overlapping area, parasitic capacitance compared with
The technical issues of influencing display quality greatly.
To solve the above problems, technical solution provided by the invention is as follows：
The present invention provides a kind of thin film transistor (TFT), including：
Substrate, and the grid, source electrode, drain electrode, semiconductor layer and the insulating layer that are set on the substrate；
The source electrode is located at same film layer with the drain electrode, and is formed with gap between the two；
The grid is set on the substrate, and below the corresponding gap between the source electrode and the drain electrode；
And
Light shield layer is set between the substrate and the grid, also, the lightproof area of the light shield layer at least covers
The semiconductor layer.
According to one preferred embodiment of the present invention, the light shield layer is prepared using insulating materials.
According to one preferred embodiment of the present invention, the light shield layer is black resin layer.
According to one preferred embodiment of the present invention, the lightproof area of the light shield layer covers the source electrode and the drain electrode.
According to one preferred embodiment of the present invention, the light shield layer is prepared using metal material, the light shield layer and the grid
Insulating layer is provided between pole.
According to one preferred embodiment of the present invention, the light shield layer is set to the substrate surface, and the grid is set to institute
State shading layer surface.
According to one preferred embodiment of the present invention, the substrate surface is provided with gate insulation layer, and the semiconductor layer is set to
The gate electrode insulation surface, the source electrode and the drain electrode are set on the semiconductor layer.
According to one preferred embodiment of the present invention, the semiconductor layer surface is provided with the first ohmic contact layer and second ohm
Contact layer is formed with gap between first ohmic contact layer and second ohmic contact layer；The source electrode is set to institute
The first Ohmic contact layer surface is stated, the drain electrode is set to the second Ohmic contact layer surface.
According to one preferred embodiment of the present invention, the line width of the grid is less than or equal to the width in the gap.
Above-mentioned purpose according to the present invention, provides a kind of array substrate, and the array substrate includes the above-mentioned of array distribution
Thin film transistor (TFT).
Beneficial effects of the present invention are：Thin film transistor (TFT) provided by the invention adds screening between substrate and semiconductor layer
Photosphere irradiates the semiconductor layer with the light that replacement gate is blocked into the substrate, can reduction of gate line width, so as to reduce
Grid and source electrode and/or the overlapping area of drain electrode, and then reduce parasitic capacitance；Solve the thin film transistor (TFT) of the prior art, grid
Pole has larger faying surface for blocking into the light of substrate and being designed with larger line width between grid and source/drain
Product increases parasitic capacitance, and then the technical issues of influence display quality.
Description of the drawings
It, below will be to embodiment or the prior art in order to illustrate more clearly of embodiment or technical solution in the prior art
Attached drawing needed in description is briefly described, it should be apparent that, the accompanying drawings in the following description is only some invented
Embodiment for those of ordinary skill in the art without creative efforts, can also be attached according to these
Figure obtains other attached drawings.
Fig. 1 is the thin film transistor (TFT) film layer structure schematic diagram that the embodiment of the present invention one provides；
Fig. 2 is thin film transistor (TFT) film layer structure schematic diagram provided by Embodiment 2 of the present invention.
Fig. 3 is the pixel cell structure schematic diagram in array substrate provided by the invention.
Specific implementation mode
The explanation of following embodiment is referred to the additional illustration, to illustrate the present invention can be used to implement particular implementation
Example.The direction term that the present invention is previously mentioned, such as [on], [under], [preceding], [rear], [left side], [right side], [interior], [outer], [side]
Deng being only the direction with reference to annexed drawings.Therefore, the direction term used be illustrate and understand the present invention, rather than to
The limitation present invention.The similar unit of structure is with being given the same reference numerals in the figure.
The present invention be directed to the prior art thin film transistor (TFT), grid for block into the light of substrate and be designed with compared with
Big line width has larger overlapping area, and then increases parasitic capacitance between grid and source/drain, and then influences display product
The technical issues of matter, the present embodiment can solve the defect.
Thin film transistor (TFT) provided by the invention, including substrate, and be set on the substrate grid, source electrode, drain electrode,
Semiconductor layer and insulating layer；The grid is set to below the semiconductor layer, between the substrate and the semiconductor layer
It is additionally provided with to block the light shield layer into the light of the substrate；The semiconductor layer surface is provided with the first ohmic contact layer
With the second ohmic contact layer, gap is formed between first ohmic contact layer and second ohmic contact layer；The source
Pole is set to the first Ohmic contact layer surface, and the drain electrode is set to the second Ohmic contact layer surface, to described
It is also formed with gap between source electrode and the drain electrode；The grid corresponds under the gap between the source electrode and the drain electrode
Side.
By taking N-type TFT as an example, when the grid imposes positive voltage, grid voltage is positioned at the exhausted of the gate surface
Electric field is generated in edge layer, power line has the grid to be directed toward the semiconductor layer surface, and charge inducing is generated at surface, with
Grid voltage increase, the semiconductor surface will be changed into electron accumulation layer by depletion layer, inversion layer be formed, when grid voltage reaches unlatching
When voltage, carrier is had between the source electrode and the drain electrode by raceway groove, the source electrode is connected with the drain electrode.
Preferably, the line width of the grid is less than or equal to the width in the gap, not influence thin film transistor (TFT) work(
The line width of the grid can be reduced as possible under the premise of property, reduce the grid with above the grid the source electrode,
Overlapping area between the drain electrode.
The substrate can be hard substrate, such as glass substrate；For another example, the substrate can also be flexible base board, such as
Polyimide substrate.
The light shield layer is prepared using insulating materials, for example, the light shield layer uses black resin material, i.e., the described shading
Layer uses identical material preparation with the black matrix" on color membrane substrates surface.
Metal material preparation also can be used in the light shield layer, as chromium oxide, crome metal, sub- titanium oxide a kind of material or
The material that the two combines.
The line width of the light shield layer is greater than or equal to the line width of the semiconductor layer.Further, the shading of the light shield layer
Source electrode described in region overlay and the drain electrode, to avoid the source electrode and the drain electrode by after backlight illumination, and by light diffraction
To the semiconductor layer, the problem of leading to semiconductor layer dysfunction.
Embodiment one
As shown in Figure 1, thin film transistor (TFT) provided by the invention, the light shield layer 101 in the thin film transistor (TFT) uses
It is prepared by insulating materials；For example, if the light shield layer 101 is using the preparation of black photosensitive type resin material.
The thin film transistor (TFT) includes glass substrate 102, and the light shield layer 101 is set to 102 surface of the glass substrate,
The grid 103 is set to 101 surface of the light shield layer, and 102 surface of the glass substrate is provided with gate insulation layer 104, described
Gate insulation layer 104 covers the grid 103 and the light shield layer 101.
The semiconductor layer 105 is set to 104 surface of the gate insulation layer, and 105 surface of the semiconductor layer is provided with
One ohmic contact layer 106 and the second ohmic contact layer 107, first ohmic contact layer 106 and second ohmic contact layer
Gap is formed between 107；The source electrode 108 is set to 106 surface of the first ohmic contact layer, 109 setting of the drain electrode
In 107 surface of the second ohmic contact layer.
104 surface of the gate insulation layer is provided with passivation layer 110, and the passivation layer 110 covers the source electrode 108, described
Drain electrode 109 and the gap between first ohmic contact layer 106 and second ohmic contact layer 107.
The corresponding position on 110 surface of the passivation layer offers through-hole, to realize the drain electrode 109 and pixel electrode
111 connection.
In the present embodiment, the light shield layer 101 is prepared using insulating materials, described when the grid 103 applies voltage
Light shield layer 101 will not be coupled, and the light shield layer 101 overlaps also not with the source electrode 108 and/or the drain electrode 109
Parasitic capacitance can be increased, therefore the grid 103 can be prepared in 101 surface of the light shield layer.The institute prepared using insulating materials
Light shield layer is stated, without coupling between the grid, can avoid generating with the overlapping region of the source electrode and the drain electrode and post
Raw capacitance.
Embodiment two
As shown in Fig. 2, thin film transistor (TFT) provided by the invention, the light shield layer 201 in the thin film transistor (TFT) uses
It is prepared by metal material；For example, the light shield layer 201 is tied using a kind of material or both of chromium oxide, crome metal, sub- titanium oxide
The material of conjunction.
The thin film transistor (TFT) includes glass substrate 202, and the light shield layer 201 is set to 202 surface of the glass substrate,
201 surface of the light shield layer is provided with an insulating layer 212, the grid 203 be set to it is described between 212 surface of insulating layer, it is described
Between 212 surface of insulating layer be provided with gate insulation layer 204, the gate insulation layer 204 covers the grid 203.
The semiconductor layer 205 is set to 204 surface of the gate insulation layer, and 205 surface of the semiconductor layer is provided with
One ohmic contact layer 206 and the second ohmic contact layer 207, first ohmic contact layer 206 and second ohmic contact layer
Gap is formed between 207；The source electrode 208 is set to 206 surface of the first ohmic contact layer, 209 setting of the drain electrode
In 207 surface of the second ohmic contact layer.
204 surface of the gate insulation layer is provided with passivation layer 210, and the passivation layer 210 covers the source electrode 208, described
Drain electrode 209 and the gap between first ohmic contact layer 206 and second ohmic contact layer 207.
The corresponding position on 210 surface of the passivation layer offers through-hole, to realize the drain electrode 209 and pixel electrode
211 connection.
In the present embodiment, prepare that 201 blackness of the light shield layer is preferable, and shaded effect is good using metal material；In order to avoid
When the grid 203 applies voltage, the light shield layer 201 is coupled, the light shield layer 201 and the source electrode 208 and/or institute
Drain electrode is stated 209 to overlap and increase parasitic capacitance, added between the light shield layer 201 and the grid 203 it is described between absolutely
Edge layer 212.
Foregoing invention purpose according to the present invention, proposes a kind of array substrate, as shown in figure 3, the array substrate includes
The pixel unit of array distribution, the pixel unit include：The scan line 307 being mutually parallel and the data line 308 being mutually parallel,
The scan line 307 intersects vertically to form multiple sub-pixels with the data line 308；Each sub-pixel includes being located at light transmission
The pixel electrode 301 and a thin film transistor (TFT) in region, the thin film transistor (TFT) include grid, source electrode 302 and drain electrode 303,
The grid connects the scan line 307, and the source electrode 302 connects the data line 308, the 303 connection picture of the drain electrode
Plain electrode 301.
Specifically, the thin film transistor (TFT) includes substrate, and be set on the substrate grid, source electrode 302, drain electrode
303, semiconductor layer 304 and insulating layer；The grid is set to 304 lower section of the semiconductor layer, the substrate and described half
It is additionally provided with to block the light shield layer 305 into the light of the substrate between conductor layer 304；304 surface of the semiconductor layer
Be provided with the first ohmic contact layer and the second ohmic contact layer, first ohmic contact layer and second ohmic contact layer it
Between be formed with gap；The source electrode 302 is set to the first Ohmic contact layer surface, and the drain electrode 303 is set to described the
Two Ohmic contact layer surfaces.
The gate electrode insulation surface is provided with passivation layer, the passivation layer cover the source electrode 302, the drain electrode 303 with
And the gap between first ohmic contact layer and second ohmic contact layer.
The corresponding position of the passivation layer surface offers through-hole 306, to realize the drain electrode 303 and pixel electrode
301 connection.
The operation principle of array substrate provided in this embodiment is identical as the operation principle of above-mentioned thin film transistor (TFT), specifically may be used
With reference to the operation principle of the thin film transistor (TFT) of above preferred embodiment, details are not described herein again.
It has the beneficial effect that：Thin film transistor (TFT) provided by the invention adds light shield layer between substrate and semiconductor layer, to replace
Irradiate the semiconductor layer for the light that grid is blocked into the substrate, can reduction of gate line width, so as to reduce grid and source
The overlapping area of pole and/or drain electrode, and then reduce parasitic capacitance；Solves the thin film transistor (TFT) of the prior art, grid is for hiding
Gear is designed with larger line width into the light of substrate, has larger overlapping area between grid and source/drain, increases
Parasitic capacitance, and then the technical issues of influence display quality.
In conclusion although the present invention is disclosed above with preferred embodiment, above preferred embodiment is not to limit
The system present invention, those skilled in the art can make various changes and profit without departing from the spirit and scope of the present invention
Decorations, therefore protection scope of the present invention is subject to the range that claim defines.
Claims (10)
1. a kind of thin film transistor (TFT), which is characterized in that including：
Substrate, and the grid, source electrode, drain electrode, semiconductor layer and the insulating layer that are set on the substrate；
The source electrode is located at same film layer with the drain electrode, and is formed with gap between the two；
The grid is set on the substrate, and below the corresponding gap between the source electrode and the drain electrode；And
Light shield layer is set between the substrate and the grid, also, described in the lightproof area of the light shield layer at least covers
Semiconductor layer.
2. thin film transistor (TFT) according to claim 1, which is characterized in that the light shield layer is prepared using insulating materials.
3. thin film transistor (TFT) according to claim 2, which is characterized in that the light shield layer is black resin layer.
4. thin film transistor (TFT) according to claim 1, which is characterized in that the lightproof area of the light shield layer covers the source
Pole and the drain electrode.
5. thin film transistor (TFT) according to claim 1, which is characterized in that the light shield layer is prepared using metal material, institute
It states and is provided with insulating layer between light shield layer and the grid.
6. thin film transistor (TFT) according to claim 1, which is characterized in that the light shield layer is set to the substrate surface,
The grid is set to the shading layer surface.
7. thin film transistor (TFT) according to claim 1, which is characterized in that the substrate surface is provided with gate insulation layer, institute
It states semiconductor layer and is set to the gate electrode insulation surface, the source electrode and the drain electrode are set on the semiconductor layer.
8. thin film transistor (TFT) according to claim 7, which is characterized in that the semiconductor layer surface is provided with first ohm
Contact layer and the second ohmic contact layer are formed with gap between first ohmic contact layer and second ohmic contact layer；
The source electrode is set to the first Ohmic contact layer surface, and the drain electrode is set to the second Ohmic contact layer surface.
9. thin film transistor (TFT) according to claim 8, which is characterized in that the line width of the grid is less than or equal to the sky
The width of gap.
10. a kind of array substrate, which is characterized in that including the thin film transistor (TFT) described in any one of claim 1-9 claims
Array.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810519773.9A CN108682693A (en) | 2018-05-28 | 2018-05-28 | Thin film transistor (TFT) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810519773.9A CN108682693A (en) | 2018-05-28 | 2018-05-28 | Thin film transistor (TFT) |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108682693A true CN108682693A (en) | 2018-10-19 |
Family
ID=63808362
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810519773.9A Pending CN108682693A (en) | 2018-05-28 | 2018-05-28 | Thin film transistor (TFT) |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110109304A (en) * | 2019-04-02 | 2019-08-09 | 惠科股份有限公司 | Array substrate, manufacturing method of array substrate and display panel |
| CN112490282A (en) * | 2020-12-03 | 2021-03-12 | Tcl华星光电技术有限公司 | Thin film transistor and preparation method thereof |
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| US20050275038A1 (en) * | 2004-06-14 | 2005-12-15 | Yi-Chi Shih | Indium oxide-based thin film transistors and circuits |
| CN103474430A (en) * | 2012-06-07 | 2013-12-25 | 群康科技(深圳)有限公司 | Thin-film transistor substrate, preparation method thereof and display |
| CN104157696A (en) * | 2014-07-16 | 2014-11-19 | 京东方科技集团股份有限公司 | Thin film transistor and preparation method thereof, as well as array baseplate and liquid crystal display device |
| CN106415801A (en) * | 2014-06-03 | 2017-02-15 | 夏普株式会社 | Semiconductor device and method for manufacturing same |
-
2018
- 2018-05-28 CN CN201810519773.9A patent/CN108682693A/en active Pending
Patent Citations (4)
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|---|---|---|---|---|
| US20050275038A1 (en) * | 2004-06-14 | 2005-12-15 | Yi-Chi Shih | Indium oxide-based thin film transistors and circuits |
| CN103474430A (en) * | 2012-06-07 | 2013-12-25 | 群康科技(深圳)有限公司 | Thin-film transistor substrate, preparation method thereof and display |
| CN106415801A (en) * | 2014-06-03 | 2017-02-15 | 夏普株式会社 | Semiconductor device and method for manufacturing same |
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| CN110109304A (en) * | 2019-04-02 | 2019-08-09 | 惠科股份有限公司 | Array substrate, manufacturing method of array substrate and display panel |
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Application publication date: 20181019 |
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