CN108667593B - FPGA-based time diversity parallel synchronization method for resisting helicopter rotor wing shielding - Google Patents
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Abstract
The invention relates to the technical field of satellite communication for resisting rotor wing shielding of a helicopter, and discloses a time diversity parallel synchronization method for resisting rotor wing shielding of a helicopter based on an FPGA (field programmable gate array). The invention fully utilizes the parallelism of the FPGA to quickly synchronize the subframe positions. The invention has the characteristics of simplicity, high efficiency, strong expansibility, wide application range and the like, can reduce storage resources, improve the frame synchronization rate and has good transmission error code performance.
Description
Technical Field
The invention relates to the technical field of satellite communication for resisting rotor wing shielding of a helicopter, in particular to a time diversity parallel synchronization method for resisting rotor wing shielding of a helicopter based on an FPGA (field programmable gate array).
Background
At present, helicopters play more and more important roles in non-war military operations such as anti-terrorism, rescue and relief, frontier emergency handling and the like. The helicopter satellite communication system is a point-to-point communication system formed by a helicopter and a ground fixed station through a synchronous satellite. Because the satellite communication radio wave propagation mode is direct wave, communication is required under the condition of no shielding, and in the flight process of the helicopter, the rotor blades can periodically shield the antenna, so that the periodic fading of communication signals is caused, and the normal communication is influenced. The data are transmitted by adopting double time diversity, the influence of rotor shielding can be effectively resisted, but some problems still exist in the frame synchronization and data recombination processes and need to be solved.
In a helicopter satellite communication system, a DSP is often adopted to realize frame synchronization, but the method needs to store a large amount of data, the synchronization rate is slow, and the actual requirement can be hardly met along with the improvement of the communication rate. In addition, because the data is transmitted by adopting double time diversity, how to utilize the information in the source frame and the copy frame to the maximum extent after the data is synchronized by the frame is also very important to improve the system performance.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides the time diversity parallel synchronization method for resisting the shielding of the helicopter rotor based on the FPGA, which has the characteristics of simplicity, high efficiency, strong expansibility, wide application range and the like, and can improve the frame synchronization rate and reduce the storage resources.
In order to achieve the purpose of the invention, the invention adopts the technical scheme that:
a time diversity parallel synchronization method for resisting helicopter rotor shielding based on an FPGA (field programmable gate array) comprises the following steps:
the method comprises the steps that data packaging and sending are carried out on sending data in a double time diversity mode, the sending data comprise a source frame and a copy frame of the source frame, each subframe of the source frame comprises a frame header, service data after coding and filling data, and the frame header adopts a ZC (Zadoff-Chu) sequence with strong correlation performance;
frame synchronization is realized in an FPGA (field programmable gate array), data received by a helicopter are simultaneously subjected to sliding cross-correlation operation with a local N-channel ZC (Zadoff-Chu) sequence in parallel, the obtained cross-correlation value is subjected to normalization processing, a write clock of the FPGA is set to be L/TsWhere L denotes the frame length of the transmitted data, i.e. the total frame length of the source frame and the copy frame, TsRepresenting an occlusion period, i.e. a data period; the value of N is the number of the subframe of the sending data, namely N is 2K, wherein K represents the number of the subframe of the source frame, and the number of the subframe of the copying frame is the same as that of the source frame; setting a read clock of the FPGA based on the local parallelism (N) and the write clock of the FPGA;
carrying out threshold judgment on the normalized cross-correlation value, if the normalized cross-correlation value is greater than a preset threshold, indicating that a subframe is found, and determining a subframe index according to the number of a local ZC sequence, so that frame synchronization is realized to represent the current corresponding subframe, and further determining the position of the synchronized subframe, wherein the threshold is an empirical value and is usually selected to slightly increase along with the increase of a signal-to-noise ratio;
according to the synchronous sub-frame index number and position, the effective data in the source frame and the copy frame can be obtained, so that the merging method data recombination is carried out on the source frame and the copy frame according to the synchronous sub-frame index number and position, and the frame decoding result is obtained.
Further, according to a timing metric function
Get the synchronization position of each sub-frame, where cu(d) The cross-correlation value of the received signal with the starting position d and the local synchronous frame head sequence with the root sequence number u of the ZC sequence is expressed by
pu(d) The average value of the energy of the received sequence and the local synchronous frame head sequence is expressed as
Where M is the frame header length of the sub-frame, u represents the root sequence number of the synchronization frame header, r (-) is the received signal sequence, the superscript "+" represents the adjoint matrix symbol of the matrix, su(k) For locally synchronizing the frame header sequence, the expression is:
k is more than or equal to 1 and less than or equal to M, and i is an imaginary unit.
During cross-correlation operation and normalization processing, calculating and sliding the energy of input data of M points and the energy of a local ZC sequence under a read clock of an FPGA and acquiring an average value of the energy (namely the energy of the input data of the M points and the energy of the local ZC sequence); meanwhile, a CORDIC core (basic addition and shift operation replaces multiplication operation) is adopted to calculate a module of a sliding cross-correlation value of the received data and a local N-path ZC sequence, and the module of the sliding cross-correlation value is divided by an energy average value to obtain a normalized cross-correlation value.
In summary, due to the adoption of the technical solutions, one or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:
the method of the invention can adopt double time diversity to send data, uses ZC sequences to perform sliding cross-correlation operation to realize frame synchronization, fully uses the parallelism of FPGA, simultaneously performs sliding cross-correlation operation on local multi-channel ZC sequences and received data, searches the index and position of a subframe, then performs merging method recombination on the data obtained by frame synchronization, and fully uses the information in a source frame and a copy frame. The method not only can quickly and accurately find the index and the position of the subframe to complete frame synchronization, but also fully utilizes the information in the source frame and the copy frame to ensure the error code performance of signal transmission. In short, the method has the characteristics of simplicity, high efficiency, strong expansibility, wide application range and the like, can reduce storage resources, improves the frame synchronization rate, and has good transmission error code performance.
Drawings
Fig. 1 is a diagram of a frame format for transmitting data;
FIG. 2 is a diagram of a helicopter rotor occlusion model;
FIG. 3 is a block diagram of correlation detection;
FIG. 4 is a diagram of a frame synchronization hardware architecture;
FIG. 5 is a block diagram of an example 1 system;
FIG. 6 is a graph comparing the performance of different recombination regimes;
FIG. 7 is a block diagram of an example 2 system;
FIG. 8 is a diagram of a frame synchronization hardware simulation, where A is a locally enlarged region identifier;
fig. 9 is a partially enlarged view of a labeled region a in fig. 8.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the following embodiments and accompanying drawings.
The invention adopts double time diversity to send data to realize communication resisting helicopter rotor wing shielding, a receiving end simultaneously and parallelly performs sliding cross-correlation operation with a local N (N has the same value as the number of subframes, for example, is set to be 64) way ZC sequence after receiving the data, frame synchronization is realized, and merging recombination is performed through subframe indexes and positions obtained by frame synchronization. The specific implementation comprises the following steps:
step A: designing a frame format by adopting a dual time diversity mode, wherein a ZC sequence with strong correlation is used as a frame header;
and B: frame synchronization is realized in an FPGA, data received by a helicopter are simultaneously subjected to sliding cross-correlation operation with a local ZC sequence in parallel, and the obtained cross-correlation value is subjected to normalization processing;
and C: threshold judgment is carried out on the normalized cross-correlation value, and the index number and the position of the subframe are determined, namely frame synchronization processing is completed;
step D: according to the subframe index numbers and positions of the frame synchronization, effective data (encoded service data and filling data of the subframes) in the source frame and the copy frame are obtained, and then the data content based on the subframe index numbers and positions of the frame synchronization is deframed in a merging method recombination mode;
in the step A, the amplitude of the signal is attenuated due to the shielding of the helicopter rotor wing, so that the signal cannot be restored. Therefore, the invention solves the problem that the signals cannot be restored due to the shielding of the helicopter rotor by transmitting data through double time diversity. The frame format of the sending data is shown in fig. 1, and includes a source frame and a copy frame of the source frame (the frame number of the source frame is the same as that of the copy frame), and the source frame includes a frame header, encoded service data and padding data. The frame header adopts a ZC sequence with strong correlation performance, and sliding cross-correlation operation is carried out on the received data and the ZC sequence at a receiving end to realize frame synchronization. The frame length (L) and the number of subframes (N) are set according to the occlusion state, the occlusion model is shown in FIG. 2, and the occlusion period (data period T)s) 31.25ms, the occlusion duration (7.8125ms) occupies 25% of the occlusion period, if the frame length L is set to 80000, the number of subframes N is set to 64, that is, 32 subframes each for the source frame and the copy frame, the subframe length L/N is 1250, the frame header length of each subframe is 131, the encoded service data length 1008 and the padding data length 111, the occlusion rate of 48% at maximum can be satisfied.
In the step B, the data are received and paralleled simultaneouslyThe earth and the local synchronization sequence perform sliding cross correlation operation to realize frame synchronization, and the detection block diagram is shown in fig. 3, where N is the number of subframes 64. The frame synchronization algorithm based on the cross-correlation has the timing measurement function as follows:
wherein c isu(d) The cross-correlation value, p, of the received signal with starting position d and the root sequence number u of the ZC sequenceu(d) Indicating the energy average of the received sequence and the local synchronization frame header sequence.
Wherein the cross-correlation value cu(d) The expression of (a) is:
average value of energy pu(d) The expression of (a) is:
where M is the length 131 of the frame header of the subframe, u represents the root sequence number of the synchronization frame header, r (-) is the received signal sequence, the superscript "+" represents the adjoint matrix symbol of the matrix, su(k) For locally synchronizing the frame header sequence, the expression is:
k is more than or equal to 1 and less than or equal to M, and i is an imaginary unit.
According to the formula
The maximum value of the sub-frame can determine the synchronous position of each sub-frame
Namely, it is
The frame synchronization design block diagram based on the FPGA is shown in fig. 4, firstly, the input data is processed by asynchronous clock, and is realized by adopting asynchronous FIFO (first in first out), and the FIFO write clock is set to 2.56Mhz (namely, based on the frame length L and the data period T)sRatio L/T ofsObtained), the FIFO read clock is based on a value matched with the read clock setting based on the parallelism, for 64-way parallel data, and for a write clock of 2.56Mhz, the read clock needs to be greater than or equal to 2.56 × 64 ═ 163.84M, so in this specific embodiment, the FIFO read clock is set to 200Mhz, the input data energy of 131 points and the energy of the local ZC sequence are calculated in a sliding manner under the clock of 200Mhz, the average is taken for normalization, meanwhile, the input data and the local 64-way ZC sequence are subjected to sliding cross-correlation operation at the same time, a CORDIC core (basic addition and shift operation is used for multiplication operation) is used to obtain a modulus of the sliding cross-correlation value, and then the energy average value is divided by the modulus of the cross-correlation value to obtain the normalized cross-correlation value.
And in the step C, judging a threshold value according to the normalized cross-correlation value obtained in the step B, wherein the threshold value selection is slightly increased along with the increase of the signal-to-noise ratio, when the normalized cross-correlation value is larger than the set threshold value, a subframe is found, and a subframe index is determined according to the local ZC sequence number, so that the frame synchronization is realized.
In the step D, data reassembly is performed according to the subframe number and subframe position obtained in the step C, for example, for the example of the source frame index corresponding to the subframe number 0-31 and the duplicated frame index corresponding to the subframe number 32-63, the reassembly mode is merging reassembly, that is, the detected bits corresponding to the source frame data and the duplicated frame data are added, for example, the data of the frame-removed header of the frame 0 and the frame 32, the frame 1 and the frame 33, and the frame 2 and the frame 34 are added according to the bit position.
The present invention will be further described with reference to the following specific examples.
Example 1
The simulation platform used in example 1 is MATLAB R2011b, the occlusion model used is as shown in fig. 2, the occlusion rate is 25%, the occlusion period is 31.25ms, the occlusion fall and occlusion rise times respectively account for 40% of the occlusion time, the complete occlusion time accounts for 20% of the occlusion time, the signal energy attenuation is 40dB when completely occluded, the signal energy attenuation is 0dB when not occluded, and the occlusion model curve occlusion fall and rise are both linear variation processes.
The test block diagram adopted in example 1 is shown in fig. 5, and a random 0,1 signal is generated first, QPSK (quadrature phase shift keying) mapping is performed, data framing is performed in a dual time diversity mode, occlusion model processing is performed, and then noise is added to obtain a received signal (gaussian occlusion channel processing); and carrying out frame synchronization on the received signals at the receiving end, carrying out frame de-framing on the data subjected to frame synchronization, respectively adopting a combination method for recombination and a comparison method for recombination in the frame de-framing, carrying out de-mapping and hard decision on the recombined data, and then carrying out bit error rate statistics. The performance curve obtained by the test is shown in fig. 6, and it can be seen that the recombination performance by adopting the combination method is about 1db better than that by adopting the comparison method.
Example 2
The simulation platforms used in example 2 are ISE 14.7 and Modelsim 10.1a, and the processing process block diagram is shown in fig. 7, where data is first framed, subjected to occlusion model processing and noise adding processing, then frame synchronization is performed, and finally, frame synchronized data is merged and reassembled. Fig. 8 is a simulation diagram of frame synchronization, and fig. 9 is a partially enlarged view of a white dotted frame marked at the left end of fig. 8. As can be seen from fig. 8 and 9, the sliding correlation operation is performed between the local ZC sequence and the source frame and the replicated frame, and when the corresponding frame header is detected, the normalized correlation value is much higher than other positions of the frame, that is, the frame synchronization can synchronize the synchronized frame header in real time and obtain the corresponding sub-frame index. For example, when the local ZC sequence numbered 0 is sliding-correlated with the received data, a maximum correlation value and the position of the value are obtained, i.e., the synchronization frame header of sub-frame 0 is synchronized. In addition, as can be seen from fig. 8, a normalized cross-correlation value obtained by synchronizing a source frame with a local ZC sequence has a section of region without an obvious peak at the middle position, because the region is a blocked region, the blocking may cause a decrease in the cross-correlation value, or even a synchronization frame header cannot be synchronized, and thus a transmitting end needs to perform dual time diversity for transmitting data.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (3)
1. A time diversity parallel synchronization method for resisting helicopter rotor wing shielding based on FPGA is characterized by comprising the following steps:
performing data encapsulation and transmission on transmission data by adopting a dual time diversity mode, wherein the transmission data comprises a source frame and a copy frame of the source frame, each subframe of the source frame comprises a frame header, coded service data and filling data, and the frame header adopts a ZC (Zadoff-Chu) sequence with strong correlation performance;
frame synchronization is realized in an FPGA (field programmable gate array), data received by a helicopter are simultaneously subjected to sliding cross-correlation operation with a local N-channel ZC (Zadoff-Chu) sequence in parallel, the obtained cross-correlation value is subjected to normalization processing, a write clock of the FPGA is set to be L/TsWhere L denotes the frame length of the transmitted data, i.e. the total frame length of the source frame and the copy frame, TsRepresenting an occlusion period, i.e. a data period; the value of N is the number of the sub-frames of the transmitted data; setting a read clock of the FPGA based on the local parallelism and the write clock of the FPGA;
carrying out threshold judgment on the normalized cross-correlation value, if the normalized cross-correlation value is greater than a preset threshold, determining a subframe index according to the local ZC sequence number to obtain a synchronous subframe index, and further determining the synchronous position of a subframe;
according to the synchronous subframe index number and the synchronous subframe position, merging method data recombination is carried out on the source frame and the copied frame to obtain a frame decoding result; wherein, the data recombination of the merging method is as follows: and adding the data of the source frame and the data of the replica frame except the frame head according to the bit position.
2. The method of claim 1, wherein determining the synchronization position of the subframe specifically comprises:
according to a timing metric function
Get the synchronization position of each sub-frame, where cu(d) The cross-correlation value of the received signal with the starting position d and the local synchronous frame head sequence with the root sequence number u of the ZC sequence is expressed by
pu (d) represents the energy average value of the received sequence and the frame head sequence of the local synchronization, and the expression is
Where M is the frame header length of the sub-frame, u represents the root sequence number of the synchronization frame header, r (-) is the received signal sequence, the superscript "+" represents the adjoint matrix symbol of the matrix, su(k) For locally synchronizing the frame header sequence, the expression is:
i is an imaginary unit.
3. The method according to claim 1 or 2, wherein, during the cross-correlation operation and normalization processing, the energy of input data of M points and the energy of the local ZC sequence are calculated by sliding calculation under the read clock of FPGA and the average value of the ability is obtained; and meanwhile, calculating a module of the sliding cross-correlation value of the received data and the local N-path ZC sequence by using basic addition and shift operation instead of multiplication operation, and dividing the module of the sliding cross-correlation value by an energy average value to obtain a normalized cross-correlation value.
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| CN104660323A (en) * | 2015-03-10 | 2015-05-27 | 中国人民解放军国防科学技术大学 | Rotor wing shielding resisting satellite communication method for helicopter |
| CN107124219A (en) * | 2017-06-30 | 2017-09-01 | 广东电网有限责任公司电力科学研究院 | Solution and system that a kind of depopulated helicopter satellite communication is blocked by rotor |
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| CN104660323A (en) * | 2015-03-10 | 2015-05-27 | 中国人民解放军国防科学技术大学 | Rotor wing shielding resisting satellite communication method for helicopter |
| CN107124219A (en) * | 2017-06-30 | 2017-09-01 | 广东电网有限责任公司电力科学研究院 | Solution and system that a kind of depopulated helicopter satellite communication is blocked by rotor |
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