CN108665972A - A kind of PET Electronic datas processing method and PET electronic systems - Google Patents
A kind of PET Electronic datas processing method and PET electronic systems Download PDFInfo
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- CN108665972A CN108665972A CN201810469097.9A CN201810469097A CN108665972A CN 108665972 A CN108665972 A CN 108665972A CN 201810469097 A CN201810469097 A CN 201810469097A CN 108665972 A CN108665972 A CN 108665972A
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- G—PHYSICS
- G16—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR SPECIFIC APPLICATION FIELDS
- G16H—HEALTHCARE INFORMATICS, i.e. INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR THE HANDLING OR PROCESSING OF MEDICAL OR HEALTHCARE DATA
- G16H40/00—ICT specially adapted for the management or administration of healthcare resources or facilities; ICT specially adapted for the management or operation of medical equipment or devices
- G16H40/60—ICT specially adapted for the management or administration of healthcare resources or facilities; ICT specially adapted for the management or operation of medical equipment or devices for the operation of medical equipment or devices
- G16H40/63—ICT specially adapted for the management or administration of healthcare resources or facilities; ICT specially adapted for the management or operation of medical equipment or devices for the operation of medical equipment or devices for local operation
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B6/00—Apparatus for radiation diagnosis, e.g. combined with radiation therapy equipment
- A61B6/02—Devices for diagnosis sequentially in different planes; Stereoscopic radiation diagnosis
- A61B6/03—Computerised tomographs
- A61B6/037—Emission tomography
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- G—PHYSICS
- G16—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR SPECIFIC APPLICATION FIELDS
- G16H—HEALTHCARE INFORMATICS, i.e. INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR THE HANDLING OR PROCESSING OF MEDICAL OR HEALTHCARE DATA
- G16H40/00—ICT specially adapted for the management or administration of healthcare resources or facilities; ICT specially adapted for the management or operation of medical equipment or devices
- G16H40/40—ICT specially adapted for the management or administration of healthcare resources or facilities; ICT specially adapted for the management or operation of medical equipment or devices for the management of medical equipment or devices, e.g. scheduling maintenance or upgrades
Abstract
The invention discloses a kind of PET Electronic datas processing method and PET electronic systems.This method is：1) it utilizes FPGA to receive the configuration data of Analog ASIC chip, configures the running parameter of the Analog ASIC chip, the working condition of asic chip is made to meet the requirement of PET electronics for imaging processing；2) utilize FPGA receive Analog ASIC chip tuning parameter, configure asic chip inside the signal testing to be exported point, if inside asic chip want the output signal of output signal test point meet PET electronics processing requirement if carry out step 3)；3) data of asic chip Serial output are converted into N channel parallel datas, then extract the charge per road, time data and are converted into binary charge, time data, N then is carried out to the roads N charge, time data：It is exported after 1 data prediction.This invention ensures that ASIC is working properly controllable and reliable.
Description
Technical field
The present invention relates to nuclear medicine fields, are related to a kind of PET electronics numbers based on asic chip-Petiroc2a
According to processing method and PET electronic systems.
Background technology
PET is important computed tomography (SPECT) system in the field of nuclear medicine, excellent by the protrusion in terms of early diagnosis of tumor
Gesture is just gradually becoming the detection means that related medical field can not replace.Its physical principle is：The pharmaceutical indications agent of injection exists
Internal nuclear decay and the positive electron (e+) of generation fall into oblivion the γ photons of the pairs of 511KeV energy of generation with internal electronics (e-),
After this is detected photon by detector system, pairs of analog pulse signal is exported, electronic system is given and is further processed, to
The charge information and temporal information of paired pulse signal are obtained, this pair of of charge, temporal information are transmitted to computer again, such as schemed
Shown in 1.Computer software developer is using a large amount of charge information pairs of as described above and temporal information, by specific
Algorithm can reconstruct pharmaceutical indications agent in distribution situation in patient body, to realize the early detection and positioning of tumour.
It is divided into two modules inside PET electronic systems：Charge measurement module and time measurement module.Charge measurement module
For obtaining the charge information of analog pulse signal, what which reflected is the energy information of the γ photons generated in vivo；When
Between measurement module be used for obtaining the temporal information of analog pulse signal, temporal information reflection is when internal γ photons are
It generates.Analog pulse signal first passes through the integral amplification of slow amplifying circuit, using rear stage in charge measurement module
Filter wave-shaping circuit signal shaping, finally pass through A-D converter (Analog to Digital Converter, ADC, with
Lower abbreviation ADC) digitized charge information is exported, which is further obtained by FPGA.Analog pulse is believed
Number in time measurement module, fast amplifying circuit is first passed through, makes the signal by undistorted amplification, using simulation timing circuit
Timing discriminator, the output pulse after timing discriminator finally passes through time-to-digit converter (Time to Digital
Converter, TDC, hereinafter referred to as TDC), digitized temporal information is exported, which is further obtained by FPGA.
After FPGA obtains charge information, temporal information, further logical process is needed so that charge, temporal information are suitble to computer
The charge handled, time data are finally transferred to computer, the processing of entire electronic system by the image procossing of software end
Flow chart is as shown in Figure 2.
The mainstream commercialization PET device to have come into operation in the world realizes entire PET electronics using discrete device
Function, volume is big, power consumption is high so that entire PET system integrated level is not high, and installation, the debugging of hardware are extremely inconvenient.At present
International many research institutions are developing the PET electronics based on special asic chip, just using a piece of asic chip
Charge, the time measurement that can complete multichannel, greatly improve the integrated level of PET electronic systems, and asic chip is being set
Power problems are just considered at the beginning of meter, power consumption when being normally carried out charge, time measurement is very low.
The technical problem to be solved by the present invention is to：Although dedicated asic chip is integrated with the institute achieved by discrete device
It is functional, but in order to make its normal work, FPGA must real-time control its running parameter, and according to sequential as defined in asic chip
Receive digitized charge, the time data of its output.And the state modulator of the asic chip up to 835bit, wherein 640bit
For the parameter of its normal work, in addition 195bit is the parameter of the ASIC debugging modes；In addition the ASIC often complete a charge,
Time measures, and the output of total serial data amount is up to 960bit；Therefore, although being easy to take with the ASIC on hardware configuration
For current discrete device electronic manner, but how with FPGA to control the asic chip, obtains the correct charge of signal, time
Information is a technological difficulties for needing to solve.
Invention content
For the technical problems in the prior art, the purpose of the present invention is to provide one kind being based on Petiroc2a
The PET electronic systems data processing method and PET electronic systems of asic chip.This method passes through field programmable gate array
(Field-Programmable Gate Array, FPGA, hereinafter referred to as FPGA) is realized to Petiroc2a working conditions
The real-time acquisition of the charge, time data of real-time control and PET system front-end detector output signal, while FPGA passes through network
Module is communicated with computer in real time, finally realizes real time computer control Petiroc2a, obtains the mould of detector output in real time
The function of the charge information and temporal information of quasi- signal.
The technical scheme is that：
A kind of PET Electronic datas processing method, step include：
1) FPGA is utilized to receive the configuration data of Analog ASIC chip, the acquisition parameter configuration module of FPGA is matched according to
The running parameter for setting the data configuration Analog ASIC chip makes the working condition of the Analog ASIC chip meet PET image-forming electrons
Learn the requirement of processing；
2) FPGA is utilized to receive the tuning parameter of Analog ASIC chip, the tuning parameter configuration module of FPGA is according to the tune
The examination parameter configuration Analog ASIC chip interior signal testing to be exported point, if the Analog ASIC chip interior will export
The requirement that the output signal of signal testing point meets the processing of PET electronics then carries out step 3), otherwise changes and reconfigures this
The running parameter of Analog ASIC chip；
3) Data acquisition and Proclssing module is utilized to obtain the roads N charge, the time data of the Analog ASIC chip Serial output,
And N channel parallel datas are converted into, the charge per road, time data are then extracted and add corresponding channel number；Then
The charge on every road, time data decoding are converted into charge, the time data of binary format, then to the roads N charge, time number
According to progress N：It is exported after 1 data prediction.
Further, the Analog ASIC chip is 32 channel Petiroc2a chips.
Further, the acquisition parameter configuration module configures the work of the Analog ASIC chip according to the configuration data
The method of parameter is：The acquisition parameter configuration module includes configuration sending module 640, configuration receiving module 640 and compares mould
Block 640；Configuration sending module 640 reads the configuration data and is repeated 2 times the configuration for being sent to the Analog ASIC chip
Module 640；While configuration sending module 640 sends the configuration data the 2nd time, configuration receiving module 640 receives the simulation
The configuration data that the configuration module 640 of asic chip is sent；When the configuration data that configuration sending module 640 completes the 2nd time is sent
When, configuration receiving module 640 synchronously completes the configuration data for receiving and being sent from the configuration module 640；Comparison module 640 judges
Whether the configuration data that the configuration data and configuration receiving module 640 that configuration sending module 640 is sent receive is identical, if phase
Together, then the configuration parameter configuration success of the Analog ASIC chip, otherwise judges that the configuration parameter configuration of the Analog ASIC chip is lost
It loses.
Further, the tuning parameter configuration module configures the Analog ASIC chip interior according to the tuning parameter and wants
The method of the signal testing point of output is：The tuning parameter configuration module includes configuration sending module 195, configuration receiving module
195 and comparison module 195；Configuration sending module 195, which reads the tuning parameter and is repeated 2 times, is sent to the Analog ASIC
The configuration module 195 of chip, while configuring the 2nd transmission tuning parameter of sending module 195, configuration receiving module 195 receives
The tuning parameter that the configuration module 195 is sent；When the tuning parameter that configuration sending module 195 completes the 2nd time is sent, configuration connects
It receives module 195 and synchronously completes the tuning parameter for receiving and being sent from configuration module 195；Comparison module 195 judges that configuration sends mould
Whether the tuning parameter that the tuning parameter and configuration receiving module 195 that block 195 is sent receive is identical, if identical, the mould
Intend the tuning parameter configuration successful of asic chip, otherwise configuration failure.
Further, the carry out N：The method of 1 data prediction is：By the roads N charge, time data in same clock
Rising edge input data transmission module, then within next N number of clock cycle, each clock rising edge data transmission module
1 road charge, time data are exported, by N number of clock cycle, completes data transmission module N：1 data prediction.
A kind of PET electronic systems, which is characterized in that including Analog ASIC chip and FPGA；The FPGA includes acquisition
Parameter configuration module, tuning parameter configuration module and data acquisition and processing module module；Wherein,
The acquisition parameter configuration module, for the configuration data according to the FPGA Analog ASIC chips received, configuration should
The running parameter of Analog ASIC chip makes the working condition of the Analog ASIC chip meet the requirement of PET electronics for imaging processing
After start the tuning parameter configuration module；
The tuning parameter configuration module, for the tuning parameter according to the FPGA Analog ASIC chips received, configuration should
The Analog ASIC chip interior signal testing to be exported point, if the Analog ASIC chip interior wants output signal test point
Output signal meet PET electronics processing requirement then log-on data obtain with processing module module, otherwise change and match again
Set the running parameter of the Analog ASIC chip；
The Data acquisition and Proclssing module, for obtain the Analog ASIC chip Serial output the roads N charge, when
Between data, and be converted into N channel parallel datas, then extract the charge per road, time data and add corresponding channel and compile
Number；Then the charge on every road, time data decoding are converted into charge, the time data of binary format, then to the roads N electricity
Lotus, time data carry out N：It is exported after 1 data prediction.
Present invention uses the newest 32 tunnels analogy asic chips of industry -- Petiroc2a (https://
Www.weeroc.com/en/products/petiroc-2a), and pass through the work shape of the FPGA real-time controls asic chip
State realizes the acquisition and processing of the charge information, temporal information of 32 tunnels analogy input signal of front end, structure such as Fig. 3.
FPGA is realized as core of the invention device by developing software logic function：
1, FPGA to the charge, time data of computer transmission.
2, the configuration data transmission of 640bit, 195bit of computer to FPGA.
3, FPGA configure the acquisition parameter and tuning parameter of ASIC in real time；
4, FPGA obtain and handle the charge of ASIC, time data in real time.
The features of the present invention includes：
1, it is received and is calculated by network module using the FPGA of the model XC5VLX110T-FFG1136 of xilinx companies
The 640bit acquisition parameters of generator terminal, and pass through the acquisition parameter of the configuration of acquisition parameter configuration module 1 ASIC.
2, the 195bit acquisition parameters of computer terminal are received by network module using the FPGA of xilinx companies, and pass through
Tuning parameter configuration module 2 configures the tuning parameter of ASIC.
3,32 are realized together with network module using the Data acquisition and Proclssing module of the FPGA design of xilinx companies
The charge of road analog signal, temporal information acquire and are transmitted to computer analyzing processing in real time.
Compared with prior art, the positive effect of the present invention is：
1, each complete modularization of function, function facilitate update, maintenance, transplanting inside FPGA.
2, by computer can real-time control ASIC, greatly reduce the use complexity of ASIC.
3, acquisition parameter and the realization method of tuning parameter configuration ensure that the reliable of ASIC normal works.
Description of the drawings
Fig. 1 is PET system functional block diagram；
Fig. 2 is that electronic system handles block diagram；
Fig. 3 is the electronic system structure diagram based on ASIC；
Fig. 4 is that technical solution of the present invention realizes block diagram；
Fig. 5 is the realization block diagram of Data acquisition and Proclssing；
Fig. 6 is the Na-22 energy spectrum diagrams measured using the present invention；
Fig. 7 is to meet time spectrogram using what the present invention measured.
Wherein, 1- acquisition parameters configuration module, 2- tuning parameters configuration module, 3- Data acquisition and Proclssing modules.
Specific implementation mode
In following specific implementation examples, in conjunction with attached drawing, the present invention is further described in detail.By enough in detail
These implementation examples of thin description so that those skilled in the art can put into practice the present invention.Do not depart from the present invention purport and
In the case of range, logic, realize and others change can be made to implementation.Therefore, following detailed description should not
It is understood to that limited significance, the scope of the present invention are only defined solely by the appended claims.
The realization block diagram of the technical solution of this patent application inside FPGA as shown in figure 4, mainly pass through 3 modules：Acquisition
Parameter configuration module 1, tuning parameter configuration module 2 and Data acquisition and Proclssing module 3 come realize control to ASIC and
Charge, temporal information obtain, then charge, time data are transferred to computer digital animation software by network module.
The function of acquisition parameter configuration module 1 is to configure the parameter of ASIC work, makes ASIC internal amplification circuits, is filtered into
The working condition of the modules such as shape circuit, timing circuit, ADC, TDC meets the requirement of PET electronics for imaging processing.
The function of tuning parameter configuration module 2 is the signal testing to be exported point inside configuration ASIC.In simple terms, ASIC
The test points of many key node signals has been reserved in inside in itself, such as the letter at the input of internal amplification circuit, output node
Number, filter the input of wave-shaping circuit, the signal etc. at output node.It can be incited somebody to action by the function of tuning parameter configuration module 2
Signal output at these nodes is for user's observation, test, the thus very convenient debugging of ASIC.When discovery internal signal
When improper, user can time update and reconfigure ASIC work parameter so that ASIC is operated in optimum state.
The function of Data acquisition and Proclssing module 3 is the 32 road charges for obtaining ASIC outputs, time data.Work as acquisition parameter
Configuration module 1 and tuning parameter configuration module 2 are all normally completed to ASIC with postponing, and ASIC is operated in most suitable PET electronics
Learn the state of processing.The module starts to receive charge, the time data exported from ASIC at this time.
● 1 function of acquisition parameter configuration module is described in detail below：
First, upper computer software sends the ASIC configuration parameters of 640bit to the network module of FPGA by network module.
Next, configuration sending module 640 can read the 640bit configuration datas in network module, and by the 640bit data weights of reading
It answers 2 times and is sent to ASIC configuration modules 640.While configuration sending module 640 sends the configuration data of this 640bit the 2nd time,
Configuration receiving module 640 can receive the 640bit data of the transmission of ASIC configuration modules 640；When configuration sending module 640 completes the 2nd
When the transmission of secondary 640bit data, what configuration receiving module 640 also just synchronized completes reception from ASIC configuration modules 640
The 640bit data of transmission.Next comparison module 640 judges that the 640bit that configuration sending module 640 is sent and configuration receive mould
Whether the 640bit data that block 640 receives are identical, if data are identical, the ASIC acquisition parameter configuration successfuls, otherwise
Show the acquisition parameter configuration failure of ASIC.After ASIC configuration successfuls, FPGA can activate tuning parameter configuration module 2；If number
According to difference, then shows ASIC acquisition parameter configuration failures, fpga logic design code need to be changed.
● 2 function of tuning parameter configuration module is described in detail below：
After 1 configuration successful of ASIC acquisition parameters configuration module, fpga logic enters tuning parameter configuration module 2.The module
Logic design structure it is similar with acquisition parameter configuration module 1.Likewise, upper computer software first passes through network module transmission
Network module of the ASIC tuning parameters of 195bit to FPGA.Next, configuration sending module 195 can be read in network module
195bit tuning parameters, and the 195bit Data duplications of reading are sent to ASIC configuration modules 195 2 times.Configure sending module
While sending the tuning parameter of this 195bit 195 the 2nd times, configuration receiving module 195 can receive the transmission of ASIC configuration modules 195
195bit data；When configuring the transmission for the 195bit data that sending module 195 completes the 2nd time, receiving module 195 is configured
The 195bit data for receiving and being sent from ASIC configuration modules 195 are completed with regard to synchronous.Next comparison module 195 judges to match
It sets the 195bit that sending module 195 is sent and whether the 195bit data that configuration receiving module 195 receives is identical, if data
Identical, then the ASIC tuning parameter configuration successfuls, otherwise indicate that the tuning parameter configuration failure of ASIC.ASIC tuning parameters are matched
After being set to work(, user can be controlled by oscillograph when observing tuning parameter configuration in the test pin of asic chip
The signal of node.Once observing that signal is improper, user needs to readjust the acquisition parameter of 640bit and rerun
Acquisition parameter configuration module 1, and crucial node signal is observed again, the key node signal inside ASIC meets PET
The requirement of electronics processing.
● Data acquisition and Proclssing module is described as follows：
After key node signal inside ASIC is met the requirements, the Data acquisition and Proclssing module 3 of FPGA begins to reality
When obtain and handle 32 road charges, the time data of ASIC Serial outputs, transmit data to network module after having handled, in
Realize that block diagram is as shown in Figure 5 in portion.
After ASIC completes 32 tunnel analog signals of acquisition every time, the data transmission blocks of ASIC are all in its 80MHz built-in system
Charge, the time data to FPGA of the total 960bit in 1 tunnel of Serial output at the rising edge of work clock, this 960bit data include 32
The charge of road analog signal, temporal information, and serial arrangement in a certain order.Serioparallel exchange module receives this 960bit strings
Row data, and realize parallelization operation in inside.The 960bit parallel datas of serioparallel exchange module output subsequently enter data and carry
Modulus block, the module extract the often charge, time data on road and add corresponding channel number.Due to the charge of acquisition, time
Data are all made of gray encoding, need first to be decoded into binary coded format and could correctly be handled by computer.Therefore per road
Charge, time data enter back into Gray code and turn binary module, be converted into binary format charge, time data output simultaneously
Into data transmission module.Data transmission module realizes 32：1 network pre-transmission processing, i.e., 32 road charges, time data are same
One rising edge clock input data transmission module, then within next 32 clock cycle, each clock rising edge data
Transmission module exports 1 road charge, time data, by 32 clock cycle, completes data transmission module 32：1 data are located in advance
Reason.Network module is then responsible for the output of data transmission module being sent to computer.
Experimental result
According to the method described above, we used yttrium luetcium silicate scintillation crystal (LYSO) and silicon photomultiplier (SiPM) and
Corresponding electronics design, using Na-22 radioactive sources, the technical solution of operation this patent design obtains 32 tunnel analog signals
Charge, time data, wherein certain arbitrary Na-22 radioactive sources power spectrum all the way as shown in fig. 6, the time of certain arbitrary two-way meet
Resolution ratio is as shown in Figure 7.It being calculated analytically, the energy resolution at 511KeV is 9.7%, and it is 700ps to meet resolution ratio,
It disclosure satisfy that the requirement of PET electronic systems.
In conclusion the above is merely preferred embodiments of the present invention, being not intended to limit the scope of the present invention.
All within the spirits and principles of the present invention, any modification, equivalent substitution, improvement and etc. done should be included in the present invention's
Within protection domain.
Claims (9)
1. a kind of PET Electronic datas processing method, step include：
1) FPGA is utilized to receive the configuration data of Analog ASIC chip, the acquisition parameter configuration module of FPGA is according to the configuration number
According to the running parameter for configuring the Analog ASIC chip, the working condition of the Analog ASIC chip is made to meet at PET electronics for imaging
The requirement of reason；
2) FPGA is utilized to receive the tuning parameter of Analog ASIC chip, the tuning parameter configuration module of FPGA is joined according to the debugging
Number configures the Analog ASIC chip interior signal testing the to be exported point, if the Analog ASIC chip interior wants output signal
The requirement that the output signal of test point meets the processing of PET electronics then carries out step 3), otherwise changes and reconfigures the simulation
The running parameter of asic chip；
3) Data acquisition and Proclssing module is utilized to obtain the roads N charge, the time data of the Analog ASIC chip Serial output, and will
It is converted to N channel parallel datas, then extracts the charge per road, time data and adds corresponding channel number；It then will be every
The charge on road, time data decoding are converted into charge, the time data of binary format, then to the roads N charge, time data into
Row N：It is exported after 1 data prediction.
2. the method as described in claim 1, which is characterized in that the Analog ASIC chip is 32 channel Petiroc2a chips.
3. method as claimed in claim 2, which is characterized in that the acquisition parameter configuration module is matched according to the configuration data
The method for setting the running parameter of the Analog ASIC chip is：The acquisition parameter configuration module includes configuration sending module 640, matches
Set receiving module 640 and comparison module 640；Configuration sending module 640, which reads the configuration data and is repeated 2 times, to be sent to
The configuration module 640 of the Analog ASIC chip；While configuration sending module 640 sends the configuration data the 2nd time, configuration connects
It receives module 640 and receives the configuration data that the configuration module 640 of the Analog ASIC chip is sent；When configuration sending module 640 is completed
When 2nd configuration data is sent, configuration receiving module 640 synchronously completes the configuration for receiving and being sent from the configuration module 640
Data；Comparison module 640 judges that the configuration data that configuration sending module 640 is sent is matched with what configuration receiving module 640 received
Whether identical set data, if identical, otherwise the configuration parameter configuration success of the Analog ASIC chip judges the Analog ASIC
The configuration parameter configuration of chip fails.
4. method as claimed in claim 2, which is characterized in that the tuning parameter configuration module is matched according to the tuning parameter
The method for setting the Analog ASIC chip interior signal testing the to be exported point is：The tuning parameter configuration module includes that configuration is sent out
Send module 195, configuration receiving module 195 and comparison module 195；Configuration sending module 195 read the tuning parameter and by its
It is repeated 2 times the configuration module 195 for being sent to the Analog ASIC chip, configures the same of the 2nd transmission tuning parameter of sending module 195
When, configuration receiving module 195 receives the tuning parameter that the configuration module 195 is sent；When configuration sending module 195 is completed the 2nd time
Tuning parameter when sending, configuration receiving module 195, which synchronously completes, receives the tuning parameter that is sent from configuration module 195；Than
Judge that the tuning parameter that configuration sending module 195 is sent and the tuning parameter that configuration receiving module 195 receives are compared with module 195
It is no identical, if identical, the tuning parameter configuration successful of the Analog ASIC chip, otherwise configuration failure.
5. the method as described in claim 1, which is characterized in that the carry out N：The method of 1 data prediction is：By the roads N
Charge, time data are in same rising edge clock input data transmission module, then within next N number of clock cycle, often
Secondary clock rising edge data transmission module exports 1 road charge, time data, by N number of clock cycle, completes data transmission module
N：1 data prediction.
6. a kind of PET electronic systems, which is characterized in that including Analog ASIC chip and FPGA；The FPGA includes that acquisition is joined
Number configuration module, tuning parameter configuration module and data acquisition and processing module module；Wherein,
The acquisition parameter configuration module configures the simulation for the configuration data according to the FPGA Analog ASIC chips received
The running parameter of asic chip opens after so that the working condition of the Analog ASIC chip is met the requirement of PET electronics for imaging processing
Move the tuning parameter configuration module；
The tuning parameter configuration module configures the simulation for the tuning parameter according to the FPGA Analog ASIC chips received
The signal testing to be exported inside asic chip point, if the output for wanting output signal test point of the Analog ASIC chip interior
Signal meet PET electronics processing requirement then log-on data obtain with processing module module, otherwise change and reconfigure this
The running parameter of Analog ASIC chip；
The Data acquisition and Proclssing module, the roads N charge, time number for obtaining the Analog ASIC chip Serial output
According to, and be converted into N channel parallel datas, then extract the charge per road, time data and add corresponding channel number；So
The charge on the roads Hou Jiangmei, time data decoding are converted into charge, the time data of binary format, then to the roads N charge, time
Data carry out N：It is exported after 1 data prediction.
7. PET electronic systems as claimed in claim 6, which is characterized in that the Analog ASIC chip is 32 channels
Petiroc2a chips.
8. PET electronic systems as claimed in claim 7, which is characterized in that the acquisition parameter configuration module includes configuration
Sending module 640, configuration receiving module 640 and comparison module 640；Configuration sending module 640 reads the configuration data and will
It is repeated 2 times the configuration module 640 for being sent to the Analog ASIC chip；Configuration sending module 640 sends the configuration number the 2nd time
According to while, configuration receiving module 640 receive the Analog ASIC chip configuration module 640 send configuration data；Work as configuration
When the configuration data that sending module 640 completes the 2nd time is sent, configuration receiving module 640 synchronously completes reception and comes from the configuration mould
The configuration data that block 640 is sent；Comparison module 640 judges that the configuration data that configuration sending module 640 is sent and configuration receive mould
Whether the configuration data that block 640 receives is identical, if identical, the configuration parameter configuration success of the Analog ASIC chip is no
Then judge the configuration parameter configuration failure of the Analog ASIC chip.
9. PET electronic systems as claimed in claim 7, which is characterized in that the tuning parameter configuration module includes configuration
Sending module 195, configuration receiving module 195 and comparison module 195；Configuration sending module 195 reads the tuning parameter and will
It is repeated 2 times the configuration module 195 for being sent to the Analog ASIC chip, the 2nd transmission tuning parameter of configuration sending module 195
Meanwhile it configuring receiving module 195 and receiving the tuning parameter that the configuration module 195 is sent；When configuration sending module 195 completes the 2nd
When secondary tuning parameter is sent, configuration receiving module 195 synchronously completes the tuning parameter for receiving and being sent from configuration module 195；
Comparison module 195 judges the tuning parameter that the tuning parameter that configuration sending module 195 is sent and configuration receiving module 195 receive
It is whether identical, if identical, the tuning parameter configuration successful of the Analog ASIC chip, otherwise configuration failure.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113907776A (en) * | 2021-10-13 | 2022-01-11 | 武汉联影生命科学仪器有限公司 | Medical equipment component debugging system, device and method and electronic equipment |
| CN116338295A (en) * | 2023-03-03 | 2023-06-27 | 中国科学院近代物理研究所 | Front end readout electronic circuit of TPC detector |
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| CN116338295B (en) * | 2023-03-03 | 2023-10-13 | 中国科学院近代物理研究所 | Front end readout electronic circuit of TPC detector |
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