CN108649954B - Vernier type high-precision high-speed A/D conversion device - Google Patents

Vernier type high-precision high-speed A/D conversion device Download PDF

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CN108649954B
CN108649954B CN201810735097.9A CN201810735097A CN108649954B CN 108649954 B CN108649954 B CN 108649954B CN 201810735097 A CN201810735097 A CN 201810735097A CN 108649954 B CN108649954 B CN 108649954B
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CN108649954A (en
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张雪原
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Chengdu University of Information Technology
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Chengdu University of Information Technology
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods

Abstract

The invention relates to a vernier type high-precision high-speed A/D conversion device. The present invention includes m conversion units each for a/D conversion of a segment of a continuous number of bits, and further includes: m-1 upward rounding switch groups, wherein the input end of each upward rounding switch group is connected with the conversion unit of the corresponding bit segment and is used for outputting the minimum voltage value output by the voltage division circuit which is larger than the measured voltage in the conversion unit of the corresponding bit segment; the input end of each downward rounding switch group is connected with the conversion unit of the corresponding bit segment and is used for outputting the maximum voltage value output by the voltage division circuit which is smaller than the measured voltage in the conversion unit of the corresponding bit segment; and the input end of the data latch is sequentially connected with the digital signals output by the m conversion units from high to low according to bit sections and is used for synchronously outputting the digital signals. The vernier with different accuracies is used for continuously refining and measuring the voltage to be converted, so that the analog-to-digital conversion accuracy is ensured, and the conversion speed is improved.

Description

Vernier type high-precision high-speed A/D conversion device
Technical Field
The invention relates to the technical field of high-precision high-speed A/D conversion, in particular to a vernier type high-precision high-speed A/D conversion device.
Background
The conversion of analog signals into digital signals (analog-to-digital conversion) is an important interface between all real systems and information systems, and is a necessary channel for the information systems to perceive the real systems. Therefore, the analog-to-digital conversion technology is one of the basic technologies of modern control, communication, information and other industries, and has very important fundamental significance.
The current analog-to-digital conversion technology mainly has four types: parallel conversion, bit-by-bit comparison, double integration, and voltage-to-frequency conversion. The parallel comparison method is that a resistance network is used for equally dividing reference voltage, each voltage average value is compared with input analog voltage, and a comparison result is input into a decoder to form a number; the parallel conversion method has the advantages that the analog-to-digital conversion speed is high, and the defect that the scale of the circuit increases along with the conversion digit in a geometric series, so that the circuit cannot be realized or is too high in cost under high-precision analog-to-digital conversion. The bit-by-bit comparison method is that the highest bit of digital quantity is set to be 1, the rest bits are set to be 0, the digital quantity is converted into analog quantity, the converted analog quantity is compared with the input analog quantity, if the input analog quantity is higher than the converted analog quantity, the highest bit is kept to be 1, if the input analog quantity is lower than the converted analog quantity, the highest bit is converted to be 0, the highest bit is determined, then the values of the following binary bits are sequentially determined, the successive comparison is carried out, and finally the conversion result is obtained. The double integration method is to convert the input analog voltage into time length and then measure the time length to obtain the final digital value, and the voltage-frequency conversion method is to convert the voltage into frequency and then obtain the digital value by measuring the frequency; the accuracy of the conversion of the latter two methods does not affect the scale of the circuit, but the conversion speed is slow.
In the analog-to-digital conversion, a multi-bit pipeline analog-to-digital conversion method is also provided, each conversion link uses less bit numbers to form parallel comparison, and encoding is carried out after the parallel comparison; on one hand, the code is part of the conversion result, on the other hand, the code is subjected to digital-to-analog conversion, the digital-to-analog conversion result is subtracted from the output signal of the current stage, and then the digital-to-analog conversion result is amplified in proportion and sent to the next stage for parallel comparison. The analog-to-digital conversion of the multi-bit pipeline has high precision and high speed in theory, but because analog subtraction operation and signal amplification processing are required to be carried out step by step in the conversion process, errors generated in the analog operation and amplification process can be amplified continuously, and the measurement precision can be easily covered by systematic errors in the high-precision analog-to-digital conversion, so that the high-precision conversion of the multi-bit pipeline is difficult to realize industrially.
The analysis of the existing analog-to-digital conversion technology shows that the conversion precision and the speed of the analog-to-digital conversion cannot be compatible, the existing technology cannot realize the high precision and the high speed of the analog-to-digital conversion, or the cost of the realization is too high to bear in the practical industrial application.
Disclosure of Invention
Aiming at the defects in the prior art, the technical problem to be solved by the invention is to provide a vernier type high-precision high-speed A/D conversion device.
The technical scheme adopted by the invention for realizing the purpose is as follows: a vernier-type high-precision high-speed A/D conversion device comprises m conversion units, each conversion unit is used for A/D conversion of a section of continuous digits, and the vernier-type high-precision high-speed A/D conversion device further comprises:
m-1 upward rounding switch groups, wherein the input end of each upward rounding switch group is connected with the conversion unit of the corresponding bit segment and is used for outputting the minimum voltage value output by the voltage division circuit which is larger than the measured voltage in the conversion unit of the corresponding bit segment;
the input end of each downward rounding switch group is connected with the conversion unit of the corresponding bit segment and is used for outputting the maximum voltage value output by the voltage division circuit which is smaller than the measured voltage in the conversion unit of the corresponding bit segment;
and the input end of the data latch is sequentially connected with the digital signals output by the m conversion units from high to low according to bit sections and is used for synchronously outputting the digital signals.
The first conversion unit of the highest bit in the conversion units comprises:
a first voltage equalizing circuit having an input terminal connected to a reference voltage VrefFor applying a reference voltage VrefIs divided into 2n1Equal parts, wherein n1 is the number of bits of the digital signal obtained by the first conversion unit;
the input end of the first comparison circuit is connected with the output end of the first voltage equalizing and dividing circuit and the voltage to be measured, the voltage to be measured is compared with the output voltage of the first voltage equalizing and dividing circuit respectively, the voltage to be measured is input into the non-inverting input end of each comparator, the output voltage of the first voltage equalizing and dividing circuit is input into the inverting input end of the corresponding comparator, and the corresponding high and low levels are obtained according to the comparison result;
and the input end of the first decoder is connected with the output end of the comparison circuit and is used for compiling the output result of the comparison circuit into an n 1-bit digital signal, and the numerical value of the decoded output corresponds to the high level quantity output by the first comparison circuit from small to large.
The second conversion unit to the m-1 th conversion unit of the middle bit in the conversion units all comprise:
the input end of the voltage equalizing and dividing circuit is connected with the output end of the upper-stage rounding switch group and a reference voltage with the voltage equalizing value of the upper-stage voltage equalizing and dividing circuit superposed on the output voltage of the upper-stage rounding switch group, and the voltage equalizing and dividing circuit is used for dividing the reference voltage into 2nsEqually dividing, wherein ns is the number of bits of the digital signal obtained by the conversion unit, and s is an integer greater than 1 and less than m;
the input end of the superposed voltage-sharing circuit is connected with the measured voltage and a reference voltage with the voltage-sharing value of the upper-stage voltage-sharing circuit, and the superposed voltage-sharing circuit is used for dividing the reference voltage into 2nsIn equal parts and superposed onAbove the measured voltage;
the input end of the comparison circuit is connected with the output end of the upper rounding switch group of the upper stage and the output end of the superposition voltage-sharing circuit of the current stage, the output voltage of the output end of the upper rounding switch group of the upper stage is input into the non-inverting input end of each comparator, the output voltage of the superposition voltage-sharing circuit of the current stage is input into the inverting input end of the corresponding comparator, and the corresponding high and low levels are obtained according to the comparison result;
and the input end of the decoder is connected with the output end of the comparison circuit and is used for compiling the output result of the comparison circuit into an ns-bit digital signal, and the numerical value output by the decoder is corresponding to the high level quantity output by the comparison circuit from small to large.
The m-th conversion unit of the lowest order among the conversion units includes:
an m-th superposed voltage-sharing circuit for dividing the reference voltage into 2 by the measured voltage and the reference voltage having the voltage-sharing value of the upper-stage voltage-sharing circuitnmEqually dividing and superposing the equally divided parts on the measured voltage, wherein nm is the digit of the digital signal obtained by the mth conversion unit;
the input end of the mth comparison circuit is connected with the output end of the mth-1 upward rounding switch group and the output end of the mth superposed voltage-sharing circuit, the output voltage of the output end of the mth-1 upward rounding switch group is input into the non-inverting input end of each comparator, and the output voltage of the mth superposed voltage-sharing circuit is input into the inverting input end of the corresponding comparator, so that the corresponding high and low levels are obtained according to the comparison result;
and the input end of the mth decoder is connected with the output end of the mth comparison circuit and is used for compiling the output result of the mth comparison circuit into a nm-bit digital signal, wherein nm is the bit number of the digital signal to be obtained by the mth conversion unit, and the numerical value output by decoding corresponds to the high level number output by the mth comparison circuit from small to large.
The upward rounding switch group comprises 2n1Switch and a2n1A logical operation unit of bits;
2 is describedn1The input end of each switch is connected with the output end of the first voltage-sharing circuit, and the control end is connected with the logic circuitThe output ends of the calculating units are connected in parallel for output;
the input end of the logic operation unit is connected with the output end of the first comparison circuit and used for controlling the on-off of the switch, so that the output voltage of the upper rounding switch group is the minimum voltage value output by the first voltage-sharing circuit and larger than the measured voltage.
The upward rounding switch group comprises 2nsA switch and a2nsA logical operation unit of bits;
2 is describednsThe input end of each switch is connected with the output end of the voltage sharing circuit, the control end of each switch is connected with the output end of the logic operation unit, and the output ends of the switches are connected in parallel for output;
the input end of the logic operation unit is connected with the output end of the comparison circuit and is used for controlling the on-off of the switch, so that the output voltage of the upper rounding switch group is the minimum voltage value output by the voltage sharing circuit and larger than the measured voltage.
The down rounding switch group comprises 2n1A switch and a2n1A logical operation unit of bits;
2 is describedn1The input end of each switch is connected with the output end of the voltage sharing circuit, the control end of each switch is connected with the output end of the logic operation unit, and the output ends of the switches are connected in parallel for output;
the input end of the logic operation unit is connected with the output end of the first comparison circuit and used for controlling the on-off of the switch, so that the output voltage of the down rounding switch group is the maximum voltage value output by the voltage sharing circuit and is smaller than the measured voltage.
The down rounding switch group comprises 2nsA switch and a2nsA logical operation unit of bits, wherein s is an integer greater than 1 and less than m-1;
2 is describednsThe input end of each switch is connected with the output end of the voltage sharing circuit, the control end of each switch is connected with the output end of the logic operation unit, and the output ends of the switches are connected in parallel for output;
the input end of the logic operation unit is connected with the output end of the comparison circuit and used for controlling the on-off of the switch, so that the output voltage of the down rounding switch group is the maximum voltage value output by the voltage sharing circuit and is smaller than the measured voltage.
The invention has the following advantages and beneficial effects:
1. in the process of converting an analog signal into a digital signal, the conversion circuit is used for carrying out detailed measurement on the voltage to be measured step by step; the method does not use a digital-to-analog conversion link or an analog calculation amplification link, thereby ensuring the analog-to-digital conversion precision, improving the conversion speed, meeting the requirements of high-precision and high-speed analog-to-digital conversion, having the advantages of simple structure, small system error, high conversion precision, high speed and the like, and having important application value.
2. The vernier voltage conversion is adopted, and the analog-to-digital conversion of the voltage can be regarded as measuring the voltage by using a voltage scale with scales.
3. Analog difference operation and signal amplification processing are not needed, and system errors caused by analog operation are avoided.
4. Digital-to-analog conversion is not needed, conversion speed is improved, circuit structure is simplified, and circuit complexity is reduced.
5. In the conversion circuit, only the switch, the comparator, the logic operation unit and other units are needed, and the circuit units have good stability, wide frequency band and high operation speed, so that the analog-to-digital conversion speed is increased, and the analog-to-digital conversion bandwidth is increased.
6. The circuit scale does not increase in geometric progression along with the conversion digit, and the scale and the complexity of the circuit are reduced.
Drawings
FIG. 1 is a block diagram of the overall structure of the present invention;
FIG. 2 is a schematic circuit diagram of the A/D conversion section of the present invention;
FIG. 3 is a circuit diagram of a data latch portion of the present invention;
fig. 4 is a schematic circuit diagram of the first set of rounding-up switches S11 according to the embodiment of the present invention;
fig. 5 is a schematic circuit diagram of the first set of rounding switches S12 according to the embodiment of the present invention;
fig. 6 is a schematic circuit diagram of a second set of rounding-up switches S21 in an embodiment of the invention;
fig. 7 is a schematic circuit diagram of a second set of rounding switches S22 in an embodiment of the invention;
FIG. 8 is a schematic diagram of vernier voltage conversion according to the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples.
The design idea of the A/D conversion device of the invention is as follows: and (3) carrying out direct and indirect mixed measurement on the input voltage by using voltage scales with different accuracies to obtain an analog-to-digital conversion result.
The reference voltage is averaged by the resistor network and the averaged voltage is compared to the input voltage to obtain a converted value. The voltage equally divided by the resistance network is the voltage scale, and the comparison of the equally divided voltage of the resistance network and the input voltage is the measurement of the input voltage.
The first level voltage scale measures the input voltage directly, and the other voltage scales measure the voltage input signal indirectly.
Except for the first stage voltage scale, the remaining voltage scales are superimposed on the input voltage.
Except for the first-stage voltage scale, the divided voltages of the other voltage scales are relatively fixed (scale relative values), but the absolute values of the divided voltages change along with the change of the input voltage, and the divided voltages are like cursors.
Except for the first-stage voltage scale, the length of each stage of voltage scale is the minimum scale value of the last-stage voltage scale.
The scale of each level of voltage scale, if the level converts the binary digit number to N, the scale value of the level of voltage scale is divided by 2N。
The result of each stage of voltage scale measurement is analog-to-digital conversion which is only input.
Except the first-stage voltage scale measurement, the values directly measured by the other voltage scales are the sum of the voltage values which are only input in all the previous stages of measurement and then the voltage value of the scale of the previous-stage voltage scale; the level measurement is obtained indirectly by comparing the voltage value with a cursor superimposed on the input voltage.
As shown in fig. 1, the vernier-type high-precision high-speed a/D conversion device provided by the present invention includes m conversion units, each conversion unit is used for a/D conversion of a segment of continuous digits, and further includes:
m-1 upward rounding switch groups, wherein the input end of each upward rounding switch group is connected with the conversion unit of the corresponding bit segment and is used for outputting the minimum voltage value output by the voltage division circuit which is larger than the measured voltage in the conversion unit of the corresponding bit segment;
the input end of each downward rounding switch group is connected with the conversion unit of the corresponding bit segment and is used for outputting the maximum voltage value output by the voltage division circuit which is smaller than the measured voltage in the conversion unit of the corresponding bit segment;
and the input end of the data latch is sequentially connected with the digital signals output by the m conversion units from high to low according to bit sections and is used for synchronously outputting the digital signals.
The first conversion unit of the highest bit in the conversion units comprises: a first voltage equalizing circuit having an input terminal connected to a reference voltage VrefFor applying a reference voltage VrefIs divided into 2n1Equal parts, wherein n1 is the number of bits of the digital signal obtained by the first conversion unit; the input end of the first comparison circuit is connected with the output end of the first voltage equalizing and dividing circuit and the voltage to be measured, the voltage to be measured is compared with the output voltage of the first voltage equalizing and dividing circuit respectively, the voltage to be measured is input into the non-inverting input end of each comparator, the output voltage of the first voltage equalizing and dividing circuit is input into the inverting input end of the corresponding comparator, and the corresponding high and low levels are obtained according to the comparison result; and the input end of the first decoder is connected with the output end of the comparison circuit and is used for compiling the output result of the comparison circuit into an n 1-bit digital signal, and the numerical value of the decoded output corresponds to the high level quantity output by the first comparison circuit from small to large.
The second conversion unit to the m-1 th conversion unit of the middle bit in the conversion units all comprise: the input end of the voltage equalizing and dividing circuit is connected with the output end of the upper-stage downward rounding switch group and the voltage equalizing and dividing circuit with the size of the upper-stage voltage equalizing and dividing circuitA reference voltage of a voltage value (the reference voltage is superposed on the output voltage of the last-stage down-rounding switch group) for dividing the reference voltage into 2nsEqually dividing, wherein ns is the number of bits of the digital signal obtained by the conversion unit, and s is an integer greater than 1 and less than m; the input end of the superposed voltage-sharing circuit is connected with the measured voltage and a reference voltage with the voltage-sharing value of the upper-stage voltage-sharing circuit, and the superposed voltage-sharing circuit is used for dividing the reference voltage into 2nsEqual parts are added and are superposed on the measured voltage; the input end of the comparison circuit is connected with the output end of the upper rounding switch group of the upper stage and the output end of the superposition voltage-sharing circuit of the current stage, the output voltage of the output end of the upper rounding switch group of the upper stage is input into the non-inverting input end of each comparator, the output voltage of the superposition voltage-sharing circuit of the current stage is input into the inverting input end of the corresponding comparator, and the corresponding high and low levels are obtained according to the comparison result; and the input end of the decoder is connected with the output end of the comparison circuit and is used for compiling the output result of the comparison circuit into an ns-bit digital signal, and the numerical value output by the decoder is corresponding to the high level quantity output by the comparison circuit from small to large.
The m-th conversion unit of the lowest order among the conversion units includes: an m-th superposed voltage-sharing circuit for dividing the reference voltage into 2 by the measured voltage and the reference voltage having the voltage-sharing value of the upper-stage voltage-sharing circuitnmEqually dividing and superposing the equally divided parts on the measured voltage, wherein nm is the digit of the digital signal obtained by the mth conversion unit; the input end of the mth comparison circuit is connected with the output end of the mth-1 upward rounding switch group and the output end of the mth superposed voltage-sharing circuit, the output voltage of the output end of the mth-1 upward rounding switch group is input into the non-inverting input end of each comparator, and the output voltage of the mth superposed voltage-sharing circuit is input into the inverting input end of the corresponding comparator, so that the corresponding high and low levels are obtained according to the comparison result; and the input end of the mth decoder is connected with the output end of the mth comparison circuit and is used for compiling the output result of the mth comparison circuit into a nm-bit digital signal, wherein nm is the bit number of the digital signal to be obtained by the mth conversion unit, and the numerical value output by decoding corresponds to the high level number output by the mth comparison circuit from small to large.
The reference voltage in fig. 1 is a scale value of the previous stage, that is, the average voltage value of the voltage-sharing circuit, and is provided by the reference voltage source circuit, and each reference voltage is independent of each other.
The upward rounding switch group comprises 2n1Switch and a2n1A logical operation unit of bits; 2 is describedn1The input end of each switch is connected with the output end of the first voltage-sharing circuit, the control end of each switch is connected with the output end of the logic operation unit, and the output ends of the switches are connected in parallel for output; the input end of the logic operation unit is connected with the output end of the first comparison circuit and used for controlling the on-off of the switch, so that the output voltage of the upper rounding switch group is the minimum voltage value output by the first voltage-sharing circuit and larger than the measured voltage.
The upward rounding switch group comprises 2nsA switch and a2nsA logical operation unit of bits; 2 is describednsThe input end of each switch is connected with the output end of the voltage sharing circuit, the control end of each switch is connected with the output end of the logic operation unit, and the output ends of the switches are connected in parallel for output; the input end of the logic operation unit is connected with the output end of the comparison circuit and is used for controlling the on-off of the switch, so that the output voltage of the upper rounding switch group is the minimum voltage value output by the voltage sharing circuit and larger than the measured voltage.
The down rounding switch group comprises 2n1A switch and a2n1A logical operation unit of bits; 2 is describedn1The input end of each switch is connected with the output end of the voltage sharing circuit, the control end of each switch is connected with the output end of the logic operation unit, and the output ends of the switches are connected in parallel for output; the input end of the logic operation unit is connected with the output end of the first comparison circuit and used for controlling the on-off of the switch, so that the output voltage of the down rounding switch group is the maximum voltage value output by the voltage sharing circuit and is smaller than the measured voltage.
The down rounding switch group comprises 2nsA switch and a2nsA logical operation unit of bits, wherein s is an integer greater than 1 and less than m-1; 2 is describednsThe input end of each switch is connected with the output end of the voltage sharing circuit, the control end of each switch is connected with the output end of the logic operation unit, and the output ends of the switches are connected in parallel for output; the logicThe input end of the edit operation unit is connected with the output end of the comparison circuit and is used for controlling the on-off of the switch, so that the output voltage of the down rounding switch group is the maximum voltage value output by the voltage dividing circuit and is smaller than the measured voltage.
As shown in fig. 2, to illustrate the technical content of the present invention, the present invention provides an embodiment, which is described by taking a 16-bit analog-to-digital conversion as an example.
The binary number of the output of the 16-bit analog-to-digital conversion can be represented as a sequence: (D15D 14D 13D 12D 11D 10D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0), this sequence shows from left to right that the 16 bits go from high to low. The 16-bit binary bit segments are grouped. (D15D 14D 13D 12) is the first group of fragments, (D11D 10D 9D 8) is the second group of fragments, (D7D 6D 5D 4) is the third group of fragments, and (D3D 2D 1D 0) is the fourth group of fragments. Each group of bit segments is converted in parallel. The conversion unit U10 converts the first bit segment group in parallel, the conversion unit U20 converts the second bit segment group in parallel, the conversion unit U30 converts the third bit segment group in parallel, the conversion unit U40 converts the fourth bit segment group in parallel, and the data output unit U50 collects the results of the conversion units and outputs data.
In the conversion unit U10, a first voltage equalizing circuit is formed by the resistor networks R101 to R116, and the value of the reference voltage E101 is the reference voltage VrefAre divided into 16 equal parts, and V can be output from the resistor networks R101-R116 in sequenceref/16、2Vref/16、3Vref/16、4Vref/16、5Vref/16、6Vref/16、7Vref/16、8Vref/16、9Vref/16、10Vref/16、11Vref/16、12Vref/16、13Vref/16、14Vref/16、15Vref16, etc. The input voltage (labeled u) is compared in turn to the voltages output by the resistor networks R101-R116 by voltage comparators a 101-a 115. The comparator outputs a high level (represented by a logic 1) when the converted voltage is higher than the voltage output by the resistor networks R101-R116, and outputs a low level (represented by a logic 0) when the converted voltage is lower than the voltage output by the resistor networks R101-R116, so that,the 15 voltage comparators have 15 logic voltage outputs. These 15 logic voltages are input to the DECODER10, and the DECODER10 outputs a four-digit binary digital value (D15D 14D 13D 12).
The truth table of the decoder is as follows:
table 1 truth table of decoder
Figure GDA0002359073610000101
Since the resistor network divides the reference voltage equally in the conversion unit U10, the conversion unit U10 forms a four-digit binary number only input analog-to-digital converter. The conversion unit U20 continues to convert the discarded part.
In the conversion unit U20, the resistance networks R221 to R236 and the comparators a201 to a215 constitute a voltage division comparison circuit. The resistor networks R221 to R236 constitute a voltage dividing circuit, which divides the standard voltage E202 equally. E201 and E202 are reference voltages of the same magnitude but independent of each other. The standard voltage E202 has a reference voltage VrefAnd/16, are divided equally into 16 equal parts. The reference zero potential of the standard voltage E202 is the converted input voltage. The resistor network of the switching unit U20 may in turn output Vref/256+u、2Vref/256+u、3Vref/256+u、4Vref/256+u、5Vref/256+u、6Vref/256+u、7Vref/256+u、8Vref/256+u、9Vref/256+u、10Vref/256+u、11Vref/256+u、12Vref/256+u、13Vref/256+u、14Vref/256+u、15Vref256+ u, etc. The output voltages of the resistor networks R221-R236 of the conversion unit U20 are sequentially connected to the non-inverting input ends of the voltage comparators A201-A215; the inverting input of the voltage comparators A201-A215 is connected to the voltage delivered by the switch set S11, and the voltage is the minimum voltage value (i.e. the output voltage of S11) output by the resistor networks R221-R236 of the converting unit U10, which is larger than the converted input voltage U. The comparator outputs a high level (represented by a logic 1) when the converted voltage is lower than the voltages output by the resistor networks R221-R236, and outputs a high level (represented by a logic 1) when the converted voltage is lower than the voltages output by the resistor networks R221-R23When the voltage of the output 6 is high, the comparator outputs low level (indicated by logic 0), so that 15 voltage comparators have 15 logic voltage outputs, the 15 logic voltage inputs into the DECODER20, and the DECODER20 outputs a four-digit binary digital value (D11D 10D 9D 8). The truth table for DECODER20 is the same as the truth table for DECODER 10.
In the conversion unit U20, a circuit for averaging the standard voltage E201 is formed by the resistor networks R201 to R216. The standard voltage E201 has a reference voltage VrefAnd/16, are divided equally into 16 equal parts. The reference zero potential of the standard voltage E201 is the output voltage of the switch group S12.
In the conversion unit U30, a circuit for averaging the standard voltage E302 is formed by the resistor networks R321 to R326. The standard voltage E302 has a reference voltage VrefAnd/256, divided equally into 16 equal parts. The reference zero potential of the standard voltage E302 is the converted input voltage u. The resistor network of the switching unit U30 may in turn output Vref/4096+u、2Vref/4096+u、3Vref/4096+u、4Vref/4096+u、5Vref/4096+u、6Vref/4096+u、7Vref/4096+u、8Vref/4096+u、9Vref/4096+u、10Vref/4096+u、11Vref/4096+u、12Vref/4096+u、13Vref/4096+u、14Vref/4096+V10、15VrefAnd/4096 + u. The output voltages of the resistor networks R321-R326 of the conversion unit U30 are sequentially connected to the non-inverting input ends of the voltage comparators A301-A315; the inverting input terminals of the voltage comparators A301-A315 are connected to the voltage transmitted from the switch set S21, and the voltage is the minimum voltage value output by the resistor networks R321-R326 of the switching unit U20 and larger than the input voltage U to be switched. When the converted voltage is lower than the voltage output by the resistor networks R321-R326, the comparator outputs a high level (represented by logic 1), and when the converted voltage is higher than the voltage output by the resistor networks R321-R326, the comparator outputs a low level (represented by logic 0), so that 15 voltage comparators have 15 logic voltage outputs, the 15 logic voltage inputs to the DECODER DECODER30, and the DECODER DECODER30 outputs a four-digit binary digital value (D7D 6D 5D 4). Decoder DECODEThe truth table for R30 is the same as the DECODER10 truth table.
In the switching unit U30, a circuit for equally dividing the standard voltage E301 is formed by the resistor networks R301 to R316. The standard voltage E301 has a reference voltage VrefAnd/256, divided equally into 16 equal parts. The reference zero potential of the standard voltage E301 is the output voltage of the switch group S22.
In the switching unit U40, a circuit for averaging the standard voltage E401 is formed by the resistor networks R401 to R416. The standard voltage E401 has a reference voltage VrefAnd/4096, divided equally into 16 equal parts. The reference zero potential of the standard voltage E401 is the converted input voltage u. The resistor network R401-R416 of the switching unit U40 may in turn output Vref/65536+u、2Vref/65536+u、3Vref/65536+u、4Vref/65536+u、5Vref/65536+u、6Vref/65536+u、7Vref/65536+u、8Vref/65536+u、9Vref/65536+u、10Vref/65536+u、11Vref/65536+u、12Vref/65536+u、13Vref/65536+u、14Vref/65536+V10、15VrefAnd/65536 + u. The output voltages of the resistor networks R401-R416 of the conversion unit U40 are sequentially connected to the non-inverting input ends of the voltage comparators A401-A415; the inverted input of the voltage comparators a 401-a 415 is connected to the voltage transmitted from the switch set S301, and the voltage is the minimum voltage value output by the resistor networks R401-R416 of the switching unit U30, which is larger than the input voltage U to be switched. When the converted voltage is lower than the voltage output by the resistor networks R401-R416, the comparator outputs a high level (represented by logic 1), and when the converted voltage is higher than the voltage output by the resistor networks R401-R416, the comparator outputs a low level (represented by logic 0), so that 15 voltage comparators have 15 logic voltage outputs, the 15 logic voltage inputs to the DECODER40, and the DECODER40 outputs a four-digit binary digital value (D3D 2D 1D 0). The truth table for DECODER40 is the same as the truth table for DECODER 10.
As shown in fig. 3, after the conversion units U10, U20, U30, and U40 are stable, the four-digit binary numbers output by the conversion units U10, U20, U30, and U40 are arranged from high to low in sequence, and the required conversion result is obtained. In the above 16-bit analog-to-digital conversion, the bit segment is equally divided into four bit segment groups in sequence from high to low, actually, the bit number of each bit segment can be changed according to needs, the minimum bit number can be one, and the maximum bit number is limited by the implementation scale of the circuit. The bit segment groups are not necessarily equally divided, and the number of bits may be different for each bit segment.
In the switch group, the voltage of two ends of each resistor in the voltage-dividing resistor network is compared with the voltage to be measured of the conversion unit to form a logic value, and the switch in the switch group is controlled by carrying out logic operation on the logic value, so that the minimum resistor network output voltage which is greater than the voltage to be measured of the conversion unit is transmitted to the output end of the switch group.
As shown in fig. 4, for the switch group S11, the truth table of the logic values C101-C115 on the logic value output line and the on/off of the switches (logic value 1 indicates that the switches are on, and logic value 0 indicates that the switches are off) is as follows. The logic value sequence on the logic output line is (C115C 114C 113C 112C 111C 110C 109C 108C 107C 106C 105C 104C 103C 102C101), and the switch logic sequence in the switch group is (S115S 114S 113S 112S 111S 110S 109S 108S 107S 106S 105S 104S 103S 102S 101).
TABLE 2 switch logic to round up switch bank S11
Switch set S11 input logic value Switch block S11 switch state
000 0000 0000 0000 0000 0000 0000 0001
000 0000 0000 0001 0000 0000 0000 0010
000 0000 0000 0011 0000 0000 0000 0100
000 0000 0000 0111 0000 0000 0000 1000
000 0000 0000 1111 0000 0000 0001 0000
000 0000 0001 1111 0000 0000 0010 0000
000 0000 0011 1111 0000 0000 0100 0000
000 0000 0111 1111 0000 0000 1000 0000
000 0000 1111 1111 0000 0001 0000 0000
000 0001 1111 1111 0000 0010 0000 0000
000 0011 1111 1111 0000 0100 0000 0000
000 0111 1111 1111 0000 1000 0000 0000
000 1111 1111 1111 0001 0000 0000 0000
001 1111 1111 1111 0010 0000 0000 0000
011 1111 1111 1111 0100 0000 0000 0000
111 1111 1111 1111 1000 0000 0000 0000
The voltage output lines B101-B116 of the resistor network of the switching unit U10 are correspondingly connected to the input terminals of the switches S101-S116, and the output terminals of the switches S101-S116 are connected in parallel and then output. Thus, the switch block S11 outputs a voltage having a minimum voltage value greater than the measured voltage in the switching unit U10.
As shown in fig. 5, for the switch group S12, the truth table of the logic values C101-C115 on the logic value output line and the on/off of the switches (logic value 1 indicates that the switches are on, and logic value 0 indicates that the switches are off) is as follows. The logic value sequence on the logic output line is (C115C 114C 113C 112C 111C 110C 109C 108C 107C 106C 105C 104C 103C 102C101), and the switch logic sequence in the switch group is (S135S 134S 133S 132S 131S 130S 129S 128S 127S 126S 125S 124S 123S 122S 121).
Table 3 switch logic for rounding down switch bank S12
Switch set S12 input logic value Switch block S12 switch state
000 0000 0000 0000 0000 0000 0000 0000
000 0000 0000 0001 0000 0000 0000 0001
000 0000 0000 0011 0000 0000 0000 0010
000 0000 0000 0111 0000 0000 0000 0100
000 0000 0000 1111 0000 0000 0000 1000
000 0000 0001 1111 0000 0000 0001 0000
000 0000 0011 1111 0000 0000 0010 0000
000 0000 0111 1111 0000 0000 0100 0000
000 0000 1111 1111 0000 0000 1000 0000
000 0001 1111 1111 0000 0001 0000 0000
000 0011 1111 1111 0000 0010 0000 0000
000 0111 1111 1111 0000 0100 0000 0000
000 1111 1111 1111 0000 1000 0000 0000
001 1111 1111 1111 0001 0000 0000 0000
011 1111 1111 1111 0010 0000 0000 0000
111 1111 1111 1111 0100 0000 0000 0000
The voltage output lines B101-B116 of the resistor network of the switching unit U10 are correspondingly connected to the input terminals of the switches S121-S136, and the output terminals of the switches S121-S136 are connected in parallel and then output. Thus, the switch block S12 outputs a voltage having a maximum voltage value smaller than the measured voltage in the switching unit U10.
As shown in fig. 6, for the switch group S21, the truth table of the logic values C201-C215 on the logic value output line and the on/off of the switches (logic value 1 indicates that the switches are on, and logic value 0 indicates that the switches are off) is as follows. The logic value sequence on the logic output line is (C215C 214C 213C 212C 211C 210C 209C 208C 206C 205C 204C 203C 202C201), and the logic sequence of the switches in the switch group is (S215S 214S 213S 212S 211S 210S 209S 208S 207S 205S 204S 203S 202S 201).
Table 4 switch logic for rounding switch block S21 upward
Switch set S2 input logic value Switch block S2 switch state
000 0000 0000 0000 0000 0000 0000 0001
100 0000 0000 0000 0000 0000 0000 0010
110 0000 0000 0000 0000 0000 0000 0100
111 0000 0000 0000 0000 0000 0000 1000
111 1000 0000 0000 0000 0000 0001 0000
111 1100 0000 0000 0000 0000 0010 0000
111 1110 0000 0000 0000 0000 0100 0000
111 1111 0000 0000 0000 0000 1000 0000
111 1111 1000 0000 0000 0001 0000 0000
111 1111 1100 0000 0000 0010 0000 0000
111 1111 1110 0000 0000 0100 0000 0000
111 1111 1111 0000 0000 1000 0000 0000
111 1111 1111 1000 0001 0000 0000 0000
111 1111 1111 1100 0010 0000 0000 0000
111 1111 1111 1110 0100 0000 0000 0000
111 1111 1111 1111 1000 0000 0000 0000
The voltage output lines B201-B216 of the resistor network of the conversion unit U20 are correspondingly connected with the input ends of the switches S201-S216, and the output ends of the switches S201-S216 are output after being connected in parallel. Thus, the switch block S21 outputs a voltage having a minimum voltage value greater than the measured voltage in the switching unit U20.
As shown in fig. 7, for the switch group S22, the truth table of the logic values C201-C215 on the logic value output line and the on/off of the switches (logic value 1 indicates that the switches are on, and logic value 0 indicates that the switches are off) is as follows. The logic value sequence on the logic output line is (C215C 214C 213C 212C 211C 210C 209C 208C 207C 205C 204C 203C 202C201), and the switch logic sequence in the switch group is (S235S 234S 233S 232S 231S 230S 229S 228S 227S 226S 224S 223S 222S 221).
TABLE 5 switch logic for rounded-down switch bank S22
Switch groupS2 input logic value Switch block S2 switch state
000 0000 0000 0000 0000 0000 0000 0000
100 0000 0000 0000 0000 0000 0000 0001
110 0000 0000 0000 0000 0000 0000 0010
111 0000 0000 0000 0000 0000 0000 0100
111 1000 0000 0000 0000 0000 0000 1000
111 1100 0000 0000 0000 0000 0001 0000
111 1110 0000 0000 0000 0000 0010 0000
111 1111 0000 0000 0000 0000 0100 0000
111 1111 1000 0000 0000 0000 1000 0000
111 1111 1100 0000 0000 0001 0000 0000
111 1111 1110 0000 0000 0010 0000 0000
111 1111 1111 0000 0000 0100 0000 0000
111 1111 1111 1000 0000 1000 0000 0000
111 1111 1111 1100 0001 0000 0000 0000
111 1111 1111 1110 0010 0000 0000 0000
111 1111 1111 1111 0100 0000 0000 0000
The voltage output lines B201-B216 of the resistor network of the conversion unit U20 are correspondingly connected to the input ends of the switches S221-S236, and the output ends of the switches S221-S236 are connected in parallel and then output. Thus, the switch block S22 outputs a voltage having a maximum voltage value smaller than the measured voltage in the switching unit U20.
The structure of the switch group S31 corresponds to the structure of the switch group S21.
The vernier voltage conversion is adopted, and the analog-to-digital conversion of the voltage can be regarded as measuring the voltage by using a voltage scale with scales. As shown in fig. 8, in the conversion unit U10, the voltage is measured using a coarse-scale voltage scale, and if the accuracy of the voltage scale is Vref/16 (the length of L3), the result of the voltage measurement is that the measured voltage is greater than NVref/16 but less than (N +1) Vref/16, and falls between the voltage scale scales NVref/M and (N +1) Vref/16. NVref/16 can be considered as the result of the first coarse measurement. In order to improve the accuracy of the measurement, a voltage scale with smaller scales is needed, so that a voltage scale L4 with the length being Vref/16 (the length of L4 is equal to L3) and a measurement voltage scale with the length being divided equally by 15 scales and the accuracy being Vref/256 are used in the second-stage measurement. Since voltage scale L4 is superimposed on the measured voltage. Therefore, the upper scale voltage scale (N +1) Vref/16 falls within the scale range of the voltage scale L4, and the distance between the top end of the voltage scale L4 and the upper scale voltage scale (N +1) Vref/16 and the distance between the measured voltage u and the upper scale voltage scale (N +1) Vref/16 are equal, so that the measured value can be obtained by measuring the distance between the top end of the voltage scale L4 and the upper scale voltage scale (N +1) Vref/16. The voltage scale L4 always floats with the change of the measured voltage u due to the voltage scale L4 being superimposed on the measured voltage u, but the minimum voltage value of the upper-stage measurement scale at which the measured voltage u is the largest always falls within the scale range of the voltage scale L4 and can always be measured. In the latter voltage measurement, the previous measurement results need to be superimposed to form a new indirectly measured object.

Claims (8)

1. A vernier type high-precision high-speed A/D conversion device is characterized by comprising m conversion units, wherein each conversion unit is used for A/D conversion of a section of continuous digits, and the vernier type high-precision high-speed A/D conversion device further comprises:
m-1 upward rounding switch groups, wherein the input end of each upward rounding switch group is connected with the conversion unit of the corresponding bit segment and is used for outputting the minimum voltage value output by the voltage division circuit which is larger than the measured voltage in the conversion unit of the corresponding bit segment;
the input end of each downward rounding switch group is connected with the conversion unit of the corresponding bit segment and is used for outputting the maximum voltage value output by the voltage division circuit which is smaller than the measured voltage in the conversion unit of the corresponding bit segment;
and the input end of the data latch is sequentially connected with the digital signals output by the m conversion units from high to low according to bit sections and is used for synchronously outputting the digital signals.
2. A vernier high accuracy high speed a/D converter as claimed in claim 1, wherein the first conversion unit of the highest order of the conversion units comprises:
a first voltage equalizing circuit having an input terminal connected to a reference voltage VrefFor applying a reference voltage VrefIs divided into 2n1Equal parts, wherein n1 is the number of bits of the digital signal obtained by the first conversion unit;
the input end of the first comparison circuit is connected with the output end of the first voltage equalizing and dividing circuit and the voltage to be measured, the voltage to be measured is compared with the output voltage of the first voltage equalizing and dividing circuit respectively, the voltage to be measured is input into the non-inverting input end of each comparator, the output voltage of the first voltage equalizing and dividing circuit is input into the inverting input end of the corresponding comparator, and the corresponding high and low levels are obtained according to the comparison result;
and the input end of the first decoder is connected with the output end of the comparison circuit and is used for compiling the output result of the comparison circuit into an n 1-bit digital signal, and the numerical value of the decoded output corresponds to the high level quantity output by the first comparison circuit from small to large.
3. The vernier high accuracy high speed A/D converter according to claim 1, wherein the second to m-1 th conversion units of the middle of the conversion units each comprise:
the input end of the voltage equalizing and dividing circuit is connected with the output end of the upper-stage rounding switch group and a reference voltage with the voltage equalizing value of the upper-stage voltage equalizing and dividing circuit superposed on the output voltage of the upper-stage rounding switch group, and the voltage equalizing and dividing circuit is used for dividing the reference voltage into 2nsEqually dividing, wherein ns is the number of bits of the digital signal obtained by the conversion unit, and s is an integer greater than 1 and less than m;
the input end of the superposed voltage-sharing circuit is connected with the measured voltage and a reference voltage with the voltage-sharing value of the upper-stage voltage-sharing circuit, and the superposed voltage-sharing circuit is used for dividing the reference voltage into 2nsEqual parts are added and are superposed on the measured voltage;
the input end of the comparison circuit is connected with the output end of the upper rounding switch group of the upper stage and the output end of the superposition voltage-sharing circuit of the current stage, the output voltage of the output end of the upper rounding switch group of the upper stage is input into the non-inverting input end of each comparator, the output voltage of the superposition voltage-sharing circuit of the current stage is input into the inverting input end of the corresponding comparator, and the corresponding high and low levels are obtained according to the comparison result;
and the input end of the decoder is connected with the output end of the comparison circuit and is used for compiling the output result of the comparison circuit into an ns-bit digital signal, and the numerical value output by the decoder is corresponding to the high level quantity output by the comparison circuit from small to large.
4. A vernier high accuracy high speed a/D converting device according to claim 1, wherein the m-th converting unit of the lowest order of the converting units comprises:
an m-th superposed voltage-sharing circuit for dividing the reference voltage into 2 by the measured voltage and the reference voltage having the voltage-sharing value of the upper-stage voltage-sharing circuitnmEqually dividing and superposing the equally divided parts on the measured voltage, wherein nm is the digit of the digital signal obtained by the mth conversion unit;
the input end of the mth comparison circuit is connected with the output end of the mth-1 upward rounding switch group and the output end of the mth superposed voltage-sharing circuit, the output voltage of the output end of the mth-1 upward rounding switch group is input into the non-inverting input end of each comparator, and the output voltage of the mth superposed voltage-sharing circuit is input into the inverting input end of the corresponding comparator, so that the corresponding high and low levels are obtained according to the comparison result;
and the input end of the mth decoder is connected with the output end of the mth comparison circuit and is used for compiling the output result of the mth comparison circuit into a nm-bit digital signal, wherein nm is the bit number of the digital signal to be obtained by the mth conversion unit, and the numerical value output by decoding corresponds to the high level number output by the mth comparison circuit from small to large.
5. A vernier high accuracy high speed a/D converter as claimed in claim 2, wherein the set of up-rounding switches comprises 2n1Switch and a2n1A logical operation unit of bits;
2 is describedn1The input end of each switch is connected with the output end of the first voltage-sharing circuit, the control end of each switch is connected with the output end of the logic operation unit, and the output ends of the switches are connected in parallel for output;
the input end of the logic operation unit is connected with the output end of the first comparison circuit and used for controlling the on-off of the switch, so that the output voltage of the upper rounding switch group is the minimum voltage value output by the first voltage-sharing circuit and larger than the measured voltage.
6. A vernier high accuracy high speed a/D converter as claimed in claim 3, wherein said up-rounding switch group comprises 2nsA switch and a2nsA logical operation unit of bits;
2 is describednsThe input end of each switch is connected with the output end of the voltage sharing circuit, the control end of each switch is connected with the output end of the logic operation unit, and the output ends of the switches are connected in parallel for output;
the input end of the logic operation unit is connected with the output end of the comparison circuit and is used for controlling the on-off of the switch, so that the output voltage of the upper rounding switch group is the minimum voltage value output by the voltage sharing circuit and larger than the measured voltage.
7. A vernier high accuracy high speed a/D converter as claimed in claim 2, wherein the set of floor switches comprises 2n1A switch and a2n1A logical operation unit of bits;
2 is describedn1The input end of each switch is connected with the output end of the voltage sharing circuit, the control end of each switch is connected with the output end of the logic operation unit, and the output ends of the switches are connected in parallel for output;
the input end of the logic operation unit is connected with the output end of the first comparison circuit and used for controlling the on-off of the switch, so that the output voltage of the down rounding switch group is the maximum voltage value output by the voltage sharing circuit and is smaller than the measured voltage.
8. A vernier type high precision high speed A/D converter as claimed in claim 3Characterized in that the down rounding switch group comprises 2nsA switch and a2nsA logical operation unit of bits, wherein s is an integer greater than 1 and less than m-1;
2 is describednsThe input end of each switch is connected with the output end of the voltage sharing circuit, the control end of each switch is connected with the output end of the logic operation unit, and the output ends of the switches are connected in parallel for output;
the input end of the logic operation unit is connected with the output end of the comparison circuit and used for controlling the on-off of the switch, so that the output voltage of the down rounding switch group is the maximum voltage value output by the voltage sharing circuit and is smaller than the measured voltage.
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