CN108647038B - FPGA (field programmable Gate array) online updating system and method based on wifi and ultrasonic communication - Google Patents
FPGA (field programmable Gate array) online updating system and method based on wifi and ultrasonic communication Download PDFInfo
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Abstract
An FPGA online updating system and an FPGA online updating method based on wifi and ultrasonic communication are disclosed. The invention discloses a Field Programmable Gate Array (FPGA) updating system and method based on wifi and ultrasonic communication, wherein the system comprises a main control module, a wifi module, an ultrasonic module, an FPGA and a Flash chip which are connected with the main control module, the wifi module and the ultrasonic module are externally connected with an upper computer, the wifi module is wirelessly connected with the upper computer and is connected with the main control module and the FPGA in an Serial Peripheral Interface (SPI) bus mode, the FPGA is connected with the Flash chip in an EMIF interface protocol, and the method comprises an updating step when an Autonomous Underwater Vehicle (AUV) is in a floating state and an updating step when the AUV is in a submergence state. The system is low in cost, convenient to use and reliable in work, a special cable and a downloader do not need to be connected, wifi and ultrasonic dual-mode communication is used for guaranteeing reliability of the system, and the method can reduce AUV program updating cost and update program versions in real time so as to improve flexibility of the AUV system.
Description
Technical Field
The invention relates to the technical field of unmanned Underwater vehicles (AUV for short) and FPGAs (field programmable gate arrays), in particular to an FPGA (field programmable gate array) online updating system and an FPGA online updating method based on wifi and ultrasonic communication.
Background
The ocean occupies 71 percent of the area of the earth, has rich biological and mineral resources, has important economic value and provides a material basis for realizing social sustainable development. The AUV, as a tool for human to utilize and develop marine resources, is now receiving general attention from countries around the world and has wide applications, such as exploration of submarine resources, submarine topography survey, etc. AUV is a tool for human development and design, and has a series of development processes including debugging and testing processes. The debugging test process is verification and feedback of a theoretical design process, is an extremely important link for AUV development and design, and is a process of 'programming, testing, recovering, disassembling, programming, installing, testing and recovering' in most cases, so that a large amount of manpower, material resources and precious time are consumed. The currently used method for updating programs in debugging tests cannot meet the requirements of the modern society with high development speed and the control of manpower, material resources and time cost, so that a better program updating method is urgently needed to be applied to the debugging tests of AUVs.
Disclosure of Invention
The invention aims to provide an FPGA (field programmable gate array) online updating system and an FPGA online updating method based on wifi and ultrasonic communication aiming at the defects of the prior art. The system is low in cost, convenient to use and reliable in work, a special cable and a downloader do not need to be connected, and wifi and ultrasonic dual-mode communication are used to ensure that the system is reliable. The method can reduce the AUV program updating cost and update the program version in real time so as to improve the flexibility of the AUV system.
The technical scheme for realizing the purpose of the invention is as follows:
the FPGA online updating system based on wifi and ultrasonic communication is different from the prior art in that the system comprises a main control module, a wifi module, an ultrasonic module, an FPGA and a Flash chip, wherein the wifi module, the ultrasonic module, the FPGA and the Flash chip are connected with the main control module; the ultrasonic module is connected with the upper computer and the main control module by adopting a UART protocol; the FPGA and the Flash chip are connected by adopting an EMIF interface protocol; the main control module is connected with a high-N address line of the Flash chip and used for dynamically switching the FPGA version program, and the main control module is connected with PROG and DONE pins of the FPGA and used for reloading the FPGA program and displaying the loading result.
The online updating method of the FPGA online updating system based on wifi and ultrasonic communication comprises the following steps: the method comprises an updating step when the AUV is in a floating state and an updating step when the AUV is in a submergence state, wherein the updating step when the AUV is in the floating state comprises the following steps:
(1) The upper computer is wirelessly connected with the wifi module and issues an online updating instruction comprising a starting mark 0X55AA, an ending mark 0XAA55, an updating block area number (0-7 area) and a CRC check code, and the SPI host of the wifi module is a main control module under the default condition;
(2) After the main control module detects an online updating instruction, the FPGA is switched to an online updating program, the Flash chip is positioned in a designated area in the instruction through a high N-bit address line of the Flash chip, meanwhile, the 'assembly completion' state information is fed back to the upper computer, and then the SPI host of the wifi module is switched to the FPGA;
(3) After the upper computer obtains the state information of 'assembly completion', transmitting the programming sub-package file through a wireless connection wifi module, and sub-packaging the sub-package file according to the specified size from the programming file;
(4) The FPGA online updating program receives and verifies the burning sub-packet file through the wifi module, if the verification is passed, the Flash chip is burned through the EMIF interface, after the burning is completed, the state information of 'successful receiving of the sub-packet' is fed back to the upper computer 1 through the wifi module, if the burning fails, the burning is carried out again, 3 times of burning is finished, the burning is withdrawn, and the state information of 'failure of burning' is fed back to the upper computer through the wifi module; if the verification fails, feeding back 'sub-packet reception failure' state information to the upper computer through a wifi module;
(5) The upper computer judges through the state information fed back by the FPGA, and if the state is 'burn failure', the upper computer directly exits the updating process and displays 'update failure'; if the status is 'sub-packet receiving failure', re-issuing the re-burning sub-packet file, and directly quitting the updating process and displaying 'updating failure' after re-issuing for 3 times; if the status is 'sub-packet receiving is successful' and the sub-packet file is not the last packet, namely the sub-packet file with the end packet frame mark, continuing to perform the step (3) and sending the next burning sub-packet file; if the status is 'sub-packet receiving is successful' and the sub-packet file is the last packet, performing the step (6);
(6) The FPGA carries out total verification on the whole packet data, the programming result is sent to the main control module, and if the verification is passed, the SPI host of the wifi module is switched back to the main control module and the main control module feeds back status information of 'programming completion' to the upper computer through the wifi module; if the verification fails, switching the SPI host of the wifi module back to the main control module and feeding back burning failure state information to the upper computer through the wifi module by the main control module;
(7) The upper computer judges through the state information fed back by the main control module, and if the state is 'burn completion', the updating process is quitted and 'updating success' is displayed; if the state is 'burn failure', directly quitting the updating process and displaying 'update failure';
the updating step in the AUV diving state is as follows:
(1) The upper computer issues a version switching instruction through the ultrasonic module;
(2) The main control module receives a version switching instruction through the ultrasonic module and then enables the FPGA to start from a designated area by controlling a high N-bit address line of the Flash chip, wherein programs in each area are pre-burned from a floating state to obtain the effect of switching the programs, a successful loading mark of the FPGA is detected, and if the programs are successful, state information of 'successful switching' is fed back to the upper computer through the ultrasonic module; if the switching fails, feeding back switching failure state information to the upper computer through the ultrasonic module;
(3) The upper computer judges through state information fed back by the ultrasonic module, and if the state is 'switching failure', the upper computer exits the updating process and displays 'updating failure'; if the state is 'switching success', exiting the updating process and displaying 'updating success'.
The system is low in cost, convenient to use and reliable in work, a special cable and a downloader do not need to be connected, and wifi and ultrasonic dual-mode communication is used to ensure that the system is reliable.
Compared with the updated process in the prior art, the method can effectively reduce the labor, material and time costs of the AUV debugging test, and remarkably improve the working efficiency.
Drawings
FIG. 1 is a schematic diagram of an online FPGA update structure in an embodiment;
FIG. 2 is a schematic diagram of an FPGA online updating process in the AUV floating state in the embodiment;
fig. 3 is a schematic diagram of an FPGA online updating process in the AUV submarine state in the embodiment.
In the figure, 1, an upper computer 2, a wifi module 3, an ultrasonic module 4, a main control module 5, FPGA6 and a flash chip.
Detailed Description
The invention will be further illustrated, but not limited, by the following description of the embodiments with reference to the accompanying drawings.
Example (b):
referring to fig. 1, the FPGA online updating system based on wifi and ultrasonic communication comprises a main control module 4, a wifi module 2, an ultrasonic module 3, an FPGA5 and a Flash chip 6, wherein the wifi module 2, the ultrasonic module 3 and the Flash chip 6 are connected with the main control module 4, the wifi module 2 and the ultrasonic module 3 are externally connected with an upper computer 1, the wifi module 2 is wirelessly connected with the upper computer 1, and the main control module 4 and the FPGA5 are connected in an SPI bus mode, so that the master-slave mode can be dynamically switched; the ultrasonic module 3 is connected with the upper computer 1 and the main control module 4 by adopting a UART protocol; the FPGA5 and the Flash chip 6 are connected by adopting an EMIF interface protocol; the main control module 4 is connected with a high-N-bit address line of the Flash chip 6 and used for dynamically switching the version program of the FPGA5, and the main control module 4 is connected with PROG and DONE pins of the FPGA5 and used for reloading the FPGA5 program and displaying the loading result.
In this example, the wifi module 2 is RAK439, the ultrasonic module 3 is AquaSent AM-AUV, the main control module 4 is STM32F103, the FPGA5 is XC7K325T-2FFG900, and the flash chip 6 is S29GL01GP.
The online updating method of the FPGA online updating system based on wifi and ultrasonic communication comprises the following steps: updating step when AUV is in floating state and updating step when AUV is in submergence state, wherein, the updating step when AUV is in floating state is as shown in figure 2:
(1) The upper computer 1 is wirelessly connected with the wifi module 2 and issues an online updating instruction comprising a starting mark 0X55AA, an ending mark 0XAA55, an updating block area number (0-7 area) and a CRC check code, and an SPI host of the wifi module 2 is a main control module 4 under the default condition;
(2) After the main control module 4 detects an online updating instruction, the FPGA5 is switched to an online updating program, the Flash chip 6 is set in a designated chip area in the instruction through a high N-bit address line of the Flash chip 6, meanwhile, the status information of 'assembly completion' is fed back to the upper computer 1, and then the SPI host of the wifi module 2 is switched to the FPGA5, specifically: the main control module 4 starts to analyze the instruction to obtain the updated area code after detecting the start mark 0X55AA, and performs CRC check, and after successful, performs the following steps: pulling up a high-order 3-bit address line to select a program in a Flash chip 6 in a 7 area, reloading the program of the FPGA5 by using a PROG pin, setting the Flash chip 6 in an instruction through the high-order 3-bit address line of the Flash chip 6 to update a chip area number, simultaneously writing status information of 'assembly completion' fed back to an upper computer 1 by a wifi module 2 through an SPI bus, and then switching an SPI host of the wifi module 2 to the FPGA5;
(3) After the upper computer 1 obtains the state information of 'assembly completion', the sub-package file is burned through the wireless connection wifi module 2, and the sub-package file is obtained by the burning file in a sub-package mode according to the specified size, and the method specifically comprises the following steps: after the upper computer 1 obtains the state information of 'assembly completion', transmitting a burning sub-packet frame containing a starting mark 0X55AA, an ending mark 0XAA55, the current sub-packet number, an ending frame mark, a 4KB sub-packet program and a CRC check code through a wireless connection wifi module 2, wherein the sub-packet frame is obtained by sub-packaging a burning bin file generated by Impact according to the size of 4KB through the upper computer;
(4) The FPGA5 online updating program receives and verifies the burning sub-packet file through the wifi module 2, if the verification is passed, the Flash chip is burned through the EMIF interface, after the burning is completed, the state information of 'successful receiving of the sub-packet' is fed back to the upper computer 1 through the wifi module 2, if the burning fails, the burning is carried out again, 3 times of burning is finished, the burning is carried out, and the state information of 'failure of burning' is fed back to the upper computer 1 through the wifi module 2; if the verification fails, feeding back 'sub-packet reception failure' state information to the upper computer 1 through the wifi module 2, specifically: the online updating program of the FPGA5 analyzes the burning sub-packet frame and carries out CRC (cyclic redundancy check) after monitoring the initial mark 0X55AA through the wifi module 2, if the checking is passed, the Flash chip 6 is burned through an EMIF (external memory interface), after the burning is finished, the state information of 'successful receiving of the sub-packet' is fed back to the upper computer 1 through the wifi module 2, if the burning is failed, the burning is carried out again, 3 times of burning is finished, and the state information of 'failed burning' is fed back to the upper computer 1 through the wifi module 2; if the CRC fails, feeding back 'sub-packet reception failure' state information to the upper computer 1 through the wifi module 2;
(5) The upper computer 1 judges through the state information fed back by the FPGA5, and if the state is 'burn failure', the updating process is directly quitted and 'update failure' is displayed; if the status is 'sub-packet receiving failure', re-issuing the re-written sub-packet file, and directly quitting the updating process and displaying 'updating failure' after 3 times of re-issuing; if the status is 'sub-packet receiving is successful' and the sub-packet file is not the last packet, namely the sub-packet file with the end packet frame mark, continuing to perform the step (3) and sending the next burning sub-packet file; if the status is 'sub-packet reception is successful' and the sub-packet file is the last packet, performing the step (6);
(6) The FPGA5 performs CRC check on the whole packet data, the result is sent to the main control module 4, if the check is passed, the SPI host of the wifi module 2 is switched back to the main control module 4, and the main control module 4 feeds back burning completion state information to the upper computer 1 through the wifi module 2; if the verification fails, switching the SPI host of the wifi module 2 back to the main control module 4 and feeding back burning failure state information to the host through the wifi module 2 by the main control module 4;
(7) The upper computer 1 judges through the state information fed back by the main control module 4, and if the state is 'burn completion', the updating process is quitted and 'update success' is displayed; if the state is 'burn failure', directly quitting the updating process and displaying 'update failure';
the updating steps in the submerged state of the AUV are as shown in fig. 3:
(1) The upper computer 1 issues a version switching instruction through the ultrasonic module 3, specifically, the upper computer 1 writes the version switching instruction containing a start mark 0X55AA, an end mark 0XAA55, an update slice area number (0-7 area) and a CRC check code through the UART interface and the ultrasonic module 3;
(2) The main control module 4 starts analyzing instructions to obtain an updated chip area number after detecting an initial mark 0X55AA through the ultrasonic module 3, performs CRC check, and performs the following steps after success, the high-3-bit address line of the Flash chip 6 is controlled, and the PROG pin is used for enabling the FPGA5 to start from the specified chip area (programs in each chip area are pre-burned when the program is in a floating state) to obtain the effect of program switching, the DONE pin is successfully loaded after 3s of time, if the program is high, the ultrasonic module 3 feeds back the state information of successful switching to the upper computer 1; if the current value is low, the state information of 'switching failure' is fed back to the upper computer 1 through the ultrasonic module 3;
(3) The upper computer 1 judges through the state information fed back by the ultrasonic module 3, and if the state is 'switching failure', the updating process is quitted and 'updating failure' is displayed; if the state is 'switching success', exiting the updating process and displaying 'updating success'.
Claims (1)
1. An updating method of an FPGA online updating system based on wifi and ultrasonic communication comprises a main control module, a wifi module, an ultrasonic module, an FPGA and a Flash chip, wherein the wifi module, the ultrasonic module, the FPGA and the Flash chip are connected with the main control module; the ultrasonic module, the upper computer and the main control module are connected by adopting a UART protocol; the FPGA and the Flash chip are connected by adopting an EMIF interface protocol; the main control module is connected with a high-N address line of the Flash chip and used for dynamically switching the FPGA version program, and is connected with PROG and DONE pins of the FPGA and used for reloading the FPGA program and displaying the loading result, and the method is characterized by comprising the following steps: an updating step when the AUV is in a floating state and an updating step when the AUV is in a submergence state, wherein,
the updating step in the AUV floating state is as follows:
(1) The upper computer is wirelessly connected with the wifi module and issues an online updating instruction containing a starting mark 0X55AA, an ending mark 0XAA55, an updating block area number 0-7 and a CRC (cyclic redundancy check) code, and an SPI (serial peripheral interface) host of the wifi module is a main control module under the default condition;
(2) After the main control module detects an online updating instruction, the FPGA is switched to an online updating program, the Flash chip is positioned in a designated area in the instruction through a high N-bit address line of the Flash chip, meanwhile, the 'assembly completion' state information is fed back to the upper computer, and then the SPI host of the wifi module is switched to the FPGA;
(3) After the upper computer obtains the state information of 'assembly completion', the sub-package file is subjected to burning through a wireless connection wifi module and is obtained by sub-packaging the burning file according to the specified size;
(4) The FPGA online updating program receives and verifies the burning sub-packet file through the wifi module, if the verification is passed, the Flash chip is burned through the EMIF interface, after the burning is completed, the state information of 'successful receiving of the sub-packet' is fed back to the upper computer through the wifi module, if the burning fails, the burning is carried out again, 3 times of burning is finished, the burning is carried out, and the state information of 'failure of burning' is fed back to the upper computer through the wifi module; if the verification fails, feeding back 'sub-packet reception failure' state information to the upper computer through a wifi module;
(5) The upper computer judges through the state information fed back by the FPGA, and if the state is 'burn failure', the upper computer directly exits the updating process and displays 'update failure'; if the status is 'sub-packet receiving failure', re-issuing the re-burning sub-packet file, and directly quitting the updating process and displaying 'updating failure' after re-issuing for 3 times; if the status is 'sub-packet receiving is successful' and the sub-packet file is not the last packet, namely the sub-packet file with the end packet frame mark, continuing to perform the step (3) and sending the next burning sub-packet file; if the status is 'sub-packet reception is successful' and the sub-packet file is the last packet, performing the step (6);
(6) The FPGA carries out total verification on the whole packet data, a programming result is sent to the main control module, if the verification is passed, the SPI host of the wifi module is switched back to the main control module, and the main control module feeds back status information of 'programming completion' to the upper computer through the wifi module; if the verification fails, switching the SPI host of the wifi module back to the main control module and feeding back burning failure state information to the upper computer through the wifi module by the main control module;
(7) The upper computer judges through the state information fed back by the main control module, and if the state is 'burn completion', the updating process is quitted and 'updating success' is displayed; if the state is 'burn failure', directly quitting the updating process and displaying 'update failure';
the updating step in the AUV diving state is as follows:
(1) The upper computer issues a version switching instruction through the ultrasonic module;
(2) The method comprises the steps that a main control module receives a version switching instruction through an ultrasonic module and then enables an FPGA to be started from a specified chip area by controlling a high N-bit address line of a Flash chip, wherein programs in each chip area are pre-burned from a floating state to obtain the effect of switching the programs, a loading success mark of the FPGA is detected, and if the loading success mark is successful, state information of 'successful switching' is fed back to an upper computer through the ultrasonic module; if the switching fails, feeding back switching failure state information to the upper computer through the ultrasonic module;
(3) The upper computer judges through the state information fed back by the ultrasonic module, and if the state is 'switching failure', the upper computer exits the updating process and displays 'updating failure'; if the state is 'switching success', exiting the updating process and displaying 'updating success'.
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| CN110412913A (en) * | 2019-07-17 | 2019-11-05 | 江苏吉泰科电气股份有限公司 | Host computer switches DSP programming program control system online |
| CN110531991B (en) * | 2019-08-08 | 2023-09-05 | 惠州市蓝微电子有限公司 | Method and system for realizing universal burning platform |
| CN111984566A (en) * | 2020-07-27 | 2020-11-24 | 广西壮族自治区生态环境监测中心 | Underwater robot program downloading system with state monitoring function |
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