CN108630608A - A kind of manufacturing method of semiconductor devices - Google Patents
A kind of manufacturing method of semiconductor devices Download PDFInfo
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- CN108630608A CN108630608A CN201710161584.4A CN201710161584A CN108630608A CN 108630608 A CN108630608 A CN 108630608A CN 201710161584 A CN201710161584 A CN 201710161584A CN 108630608 A CN108630608 A CN 108630608A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention provides a kind of manufacturing method of semiconductor devices, the method includes：The semiconductor substrate with NMOS area and the areas PMOS is provided, the dummy gate structure for being formed with dielectric layer on the semiconductor substrate and being located in the dielectric layer in the NMOS area and the areas PMOS, the dummy gate structure includes dummy grid material layer；The dummy grid material layer for removing the areas PMOS, to form PMOS grooves；PMOS metal gates are formed in the PMOS grooves, the PMOS metal gates include PMOS work-function layers；PMOS metal gates described in nitrogen treatment, the nitrogen treatment convert the PMOS work-function layers to nitrogen-enriched layer.Reduce the leakage current occurred in chemical mechanical planarization process according to the method for the present invention, prevents diffusion of the metal material layer to work-function layer, reduce the defect of metal gates, improve the performance of semiconductor devices.
Description
Technical field
The present invention relates to field of semiconductor manufacture, in particular to a kind of manufacturing method of semiconductor devices.
Background technology
With the rapid development of semiconductor integrated circuit (IC) industry, high-K metal gate (HKMG) technology, which has become, partly to be led
One of the important technology in body field.With the continuous reduction of dimensions of semiconductor devices, the development of high-K metal gate (HKMG) technique
In, for the CMOS compared with fractional value process node, the high k- metal gate process more and more applies " rear grid
(Gate-last) " technique, rear grid technique are to carry out the operation of drain source ion implanting and subsequent height to semiconductor substrate
Warm annealing process re-forms the process of metal gates after completing.One typical implementation process includes：On a semiconductor substrate
Dummy gate structure is formed, the dummy gate structure is made of the gate dielectric and dummy grid material layer being laminated from bottom to top；
The both sides of dummy gate structure form side wall construction, remove gate dielectric and dummy grid material layer in dummy gate structure later,
Related interfaces layer, workfunction layers and metal gate material are sequentially formed in the groove left between side wall construction (usually
For aluminium) filling, and to after filling semiconductor substrate carry out chemical mechanical grinding form final metal gate structure.So
And the defect of metal gate structure often occurs after the chemical mechanical planarization process after completing metal gates filling smithcraft,
Decline so as to cause device performance.
Invention content
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
The present invention provides a kind of manufacturing method of semiconductor devices, the method includes：There is provided have NMOS area and
The semiconductor substrate in the areas PMOS is formed with dielectric layer and is located at the NMOS area and described on the semiconductor substrate
Dummy gate structure in the dielectric layer in the areas PMOS, the dummy gate structure include dummy grid material layer；
The dummy grid material layer for removing the areas PMOS, to form PMOS grooves；
PMOS metal gates are formed in the PMOS grooves, the PMOS metal gates include PMOS work-function layers；
PMOS metal gates described in nitrogen treatment, the nitrogen treatment convert the PMOS work-function layers to nitrogen-enriched layer.
Illustratively, the nitrogen treatment is included in the annealing process under nitrogen containing atmosphere.
Illustratively, the annealing process under nitrogen containing atmosphere is at 200~1000w of radio-frequency power, using N2O、
And/or N2, and/or NH3Gas carries out 50~100s annealing.
Illustratively, the PMOS metal gates further include PMOS soakage layers, and the nitrogen treatment further includes by the leaching
Profit layer is converted into nitrogen-enriched layer.
Illustratively, the PMOS work-function layers include TiN.
Illustratively, the PMOS soakage layers include TiAl.
Illustratively, further include the steps that NMOS metal gates are formed after carrying out PMOS metal gates described in nitrogen treatment
The step of pole.
Illustratively, described the step of PMOS grids are formed in the PMOS grooves, includes:
PMOS work-function layers and metal material layer are sequentially formed from top to bottom in the PMOS grooves；
Chemical mechanical grinding is executed, to remove the PMOS work-function layers and metal material layer outside the PMOS grooves.
Illustratively, described the step of NMOS metal gates are formed in the NMOS grooves, includes:
The dummy grid material layer for removing the NMOS area, to form NMOS grooves；
NMOS work-function layers and metal material layer are sequentially formed from top to bottom in the NMOS grooves；
Chemical mechanical grinding is executed, to remove the NMOS work-function layers and metal material layer outside the NMOS grooves.
Illustratively, the dummy gate structure further includes the high k dielectric layer being located at below the dummy grid material layer, and/
Or it is formed in the boundary layer between the semiconductor substrate and the high k dielectric layer.
The manufacturing method of semiconductor device according to the invention executes nitrogen treatment work after forming PMOS gate structures
Skill so that PMOS work-function layers are converted into nitrogen-enriched layer, on the one hand, reduce in the chemical mechanical grinding for forming NMOS metal gates
In technique, the leakage current at PMOS work-function layers interface corrosion and damage caused by PMOS work-function layers caused by lapping liquid, separately
On the one hand, metal material layer is prevented to further reduce chemical mechanical grinding to the diffusion of the other materials layer of metal gates
The possibility corroded in the process improves the performance of semiconductor devices, reduces the defect of metal gates, improves device
Performance.
Description of the drawings
The following drawings of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Fig. 1 is the schematic flow chart of method, semi-conductor device manufacturing method in the prior art；
Fig. 2A~2I shows for the structure for the device that correlation step in the manufacturing method of semiconductor devices in the prior art is formed
It is intended to；
Fig. 3 is the schematic flow chart for the method, semi-conductor device manufacturing method that one embodiment of the present of invention proposes；
Correlation step is formed in the manufacturing method for the semiconductor devices that Fig. 4 A~4J propose for one embodiment of the present of invention
Device structural schematic diagram；
Correlation step shape in the manufacturing method for the semiconductor devices that Fig. 5 A~5J propose for an alternative embodiment of the invention
At device structural schematic diagram.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed description will be proposed in following description, to illustrate of the present inventionization
Learn mechanical grinding method.Obviously, execution of the invention is not limited to the specific details that the technical staff of semiconductor applications is familiar with.
Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention can also have other realities
Apply mode.
It should give it is noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative
Intention includes plural form.Additionally, it should be understood that when using term "comprising" and/or " comprising " in the present specification
When, indicate that there are the feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of one or more
Other a features, entirety, step, operation, element, component and/or combination thereof.
Now, exemplary embodiment according to the present invention is more fully described with reference to the accompanying drawings.However, these exemplary realities
Applying example can be implemented with many different forms, and should not be construed to be limited solely to the embodiments set forth herein.It should
These embodiments that are to provide understood are in order to enable disclosure of the invention is thoroughly and complete, and by these exemplary implementations
The design of example is fully conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, the thickness of layer and region is exaggerated
Degree, and make that identical element is presented with like reference characters, thus description of them will be omitted.
In existing metal gates forming process metal gates are formed frequently with rear metal gate process.As Fig. 1 is shown now
There is the typical process flow chart for forming metal gates in technology, step S101 is first carried out, provides with NMOS area and PMOS
The semiconductor substrate in area is formed with dielectric layer and is located at the NMOS area and the PMOS on the semiconductor substrate
Dummy gate structure in the dielectric layer in area, the dummy gate structure include dummy grid material layer；As shown in Figure 2 A, with
It is formed with dielectric layer 203 and the dummy gate structure in the dielectric layer in the semiconductor substrate 200 in NMOS area and the areas PMOS,
The dummy gate structure includes the high k dielectric layer 201 being located on the semiconductor and the dummy grid in the high k dielectric layer
Material layer 202.Then, step S102 is executed：The dummy grid material layer for removing the PMOS area, to form PMOS grooves；Such as
Shown in Fig. 2 B, the dummy grid material layer 202 of the PMOS area is removed, forms PMOS grooves 204.Then, step S103 is executed：
PMOS metal gates are formed in the PMOS grooves, the PMOS metal gates include PMOS work-function layers and metal material
Layer；As shown in Fig. 2 C~2E, PMOS work-function layers 205 and metal material layer 206 are sequentially formed in the PMOS grooves, are executed
Chemical mechanical grinding, to remove the PMOS work-function layers and metal material layer outside the PMOS grooves, to form PMOS metals
Grid 207.Then, step S104 is executed：The dummy grid material layer for removing the NMOS area, to form NMOS grooves.As schemed,
Shown in 2F, the dummy grid material 202 of the NMOS area is removed in the semiconductor substrate for being formed with PMOS metal gates,
To form NMOS grooves 208.Finally, step S105 is executed：NMOS metal gates, the NMOS are formed in the NMOS grooves
Metal gates include NMOS work-function layers and metal material layer；As shown in Fig. 2 G~2I, the shape successively in the NMOS grooves 208
At NMOS work-function layers 209 and metal material layer 210, and chemical mechanical grinding is executed to remove the work content outside the NMOS grooves
Several layers 209 and metal material 210, to form NMOS metal gates.However, in existing metal gates formation process, it is commonly formed
There are the metal gate structure of the lamination including various metals or metallic compound, such as the lamination of TaN, TiN, TiAl, this just leads
Cause in chemical mechanical planarization process, tend to occur metal material to work-function layer or diffuse to form diffusion layer material, e.g., make
For the Al of metal material TaNAl materials are diffuseed to form to TaN is formed.This diffusion layer material, it is golden in NMOS such as TaNAl materials
In the chemical mechanical grinding for belonging to grid, under the action of lapping liquid, it is being ground to boundary position (A points position as illustrated in figure 2h) pole
Easily occur to form microcell leakage current with other work-function layers of PMOS, such as TiN, to damage in chemical mechanical milling tech
It loses, and generates PMOS grids and boundary corrosion defect occurs, and then influence the performance of device.For this reason, it is necessary to introduce semiconductor device
Part manufacturing method, so as to improve the defect generated in metal gates forming process.
For this purpose, the present invention provides a kind of semiconductor making methods, including：
There is provided with NMOS area and the areas PMOS semiconductor substrate, be formed on the semiconductor substrate dielectric layer and
The dummy gate structure being located in the dielectric layer in the NMOS area and the areas PMOS, the dummy gate structure include puppet
Gate material layers；
The dummy grid material layer for removing the areas PMOS, to form PMOS grooves；
PMOS metal gates are formed in the PMOS grooves, the PMOS metal gates include PMOS work-function layers；
PMOS metal gates described in nitrogen treatment, the nitrogen treatment convert the PMOS work-function layers to nitrogen-enriched layer.
The manufacturing method of semiconductor device according to the invention executes nitrogen treatment work after forming PMOS gate structures
Skill so that PMOS work-function layers are converted into nitrogen-enriched layer, on the one hand, reduce in the chemical mechanical grinding for forming NMOS metal gates
In technique, the leakage current at PMOS work-function layers interface corrosion and damage caused by PMOS work-function layers caused by lapping liquid, separately
On the one hand, metal material layer is prevented to further reduce chemical mechanical grinding to the diffusion of the other materials layer of metal gates
The possibility corroded in the process improves the performance of semiconductor devices, reduces the defect of metal gates, improves device
Performance.
Embodiment one
A kind of manufacturer of semiconductor devices of one embodiment of the present of invention proposition is described with reference to figure 3 and Fig. 4 A~4J
Method, wherein the schematic flow chart for the method, semi-conductor device manufacturing method that Fig. 3 proposes for one embodiment of the present of invention, Fig. 4 A~
4J is the knot for the semiconductor devices that correlation step is related in the method, semi-conductor device manufacturing method that one embodiment of the present of invention proposes
Structure schematic diagram figure.
First, step S301 is executed：The semiconductor substrate with NMOS area and the areas PMOS is provided, in the semiconductor substrate
On the dummy gate structure that is formed with dielectric layer and is located in the dielectric layer in the NMOS area and the areas PMOS, institute
It includes dummy grid material layer to state dummy gate structure.
As shown in Figure 4 A, semiconductor substrate 400 is provided, the areas PMOS and NMOS area are formed in the semiconductor substrate 400,
It is formed with dielectric layer 403 in the semiconductor substrate 400, and is located at the dummy gate structure in the areas PMOS and NMOS area,
The dummy gate structure includes dummy grid material layer 402.The constituent material of semiconductor substrate 400 can be undoped monocrystalline
Silicon, the monocrystalline silicon mixed with impurity, silicon-on-insulator (SOI) etc..
Illustratively, the dummy gate structure by being laminated 402 structure of high k dielectric layer 401 and dummy grid material layer from bottom to top
At.Illustratively, the related formation process for carrying out metal gate structure is formed using metal gate process after first high k dielectric layer,
It is described to form dielectric layer on a semiconductor substrate and include the step of dummy gate structure in the dielectric layer：It is partly led described
High k dielectric layer is formed in body substrate；Dummy grid material layer is formed in the high k dielectric layer；Pattern the gate material layers；
Source/drain region ion implanting is executed in the gate material layers both sides；Interlayer dielectric layer is formed on the semiconductor substrate；And it holds
Row chemical mechanical grinding is to expose the dummy grid material layer.Dummy gate structure is formed using first high k dielectric layer post tensioned unbonded prestressed concrete technique
The technique that is well known to those skilled in the art of technique, details are not described herein.
It is to be appreciated that the present embodiment forms the process of dummy grid with metal gate process after first high k dielectric layer
It is illustrated for embodiment, is not intended to limit the invention, it is any to form dielectric layer and ditch on a semiconductor substrate
Slot is suitable for the present invention for the technical process of follow-up workfunction layers and metal material filling.
Illustratively, interfacial TCO layer is formed between the high k dielectric layer 401 and semiconductor substrate 400, the boundary layer is used
Interfacial characteristics between the improvement high k dielectric layer 401 being subsequently formed and semiconductor substrate 400.The boundary layer can be oxygen
SiClx, the material of any suitable well-known to those skilled in the art such as silicon oxynitride.
Illustratively, it is formed before dummy grid material layer after forming the high k dielectric layer, in the high k dielectric layer
Surface is formed with coating, and the constituent material of coating includes lanthana, aluminium oxide, gallium oxide, indium oxide, molybdenum oxide carbonization
Tantalum, oxygen nitrogen ramet, tantalum nitride, titanium nitride, molybdenum nitride, tungsten nitride, platinum, ruthenium, iridium etc. can pass through chemical vapor deposition, atom
The suitable substance that layer deposition or physical gas-phase deposition are formed, illustratively, using physical gas-phase deposition,
At 275 DEG C, the coating of TaN is formed, the overburden cover of the TaN is 5 angstroms -20 angstroms.
It is to be appreciated that being not intended to this hair as embodiment using the technique for forming boundary layer and coating in the present invention
Bright to be limited, selection forms boundary layer and covering layer process to those skilled in the art as needed.
In addition, the semiconductor substrate is divided into as an example, being formed with isolation structure in the semiconductor substrate 400
The areas PMOS and NMOS area, the method for forming the isolation structure is known to one of skill in the art, is not repeated here herein.
The both sides of dummy gate structure are formed with side wall construction, wherein side wall construction includes at least oxide skin(coating) and/or nitride layer.Shape
It is known to those skilled in the art at the method for side wall construction, it is not repeated here herein.In partly leading for side wall construction both sides
It is formed with source/drain region in body substrate 400, embedded carbon silicon is being respectively formed in the source/drain region in NMOS area and the areas PMOS
Layer and embedded germanium silicon layer.The technical process for forming embedded carbon silicon layer and embedded germanium silicon layer is ripe for those skilled in the art
It practises, is not repeated here herein.It is formed with self-aligned silicide at the top of embedded carbon silicon layer and embedded germanium silicon layer, in order to
Simplify, it is illustrated that in omitted.
It is to be appreciated that form isolation structure, dummy grid side wall construction, source/drain in semiconductor substrate in embodiment
The embedded carbon silicon layer and embedded germanium silicon layer formed in area and source/drain region is illustrated for example and is not intended to the present invention
Be defined, any semiconductor substrate, thereon have NMOS area and the areas PMOS, dielectric layer and be located at the NMOS area and
Dummy gate structure in the dielectric layer in the areas PMOS is suitable for the present invention.
Then, step S302 is executed：The dummy grid material layer for removing the PMOS area, to form PMOS grooves.
As shown in Figure 4 B, the dummy grid material layer 402 for removing the PMOS area is formed on 400 surface of semiconductor substrate
PMOS grooves 404.The method for removing the dummy grid material layer 402 can be familiar with various by those skilled in the art
Suitable process.As an example, in the present embodiment, by implementing dry etching, removing pseudo- gate electrode layer and puppet successively
Gate dielectric layer.The technological parameter of the dry etching includes：The flow of etching gas HBr is 20-500sccm, pressure 2-
40mTorr, power 100-2000W, wherein mTorr represent milli millimetres of mercury, and sccm represents cc/min.Implementing
After the dry etching, the etch residues and impurity that the dry etching generates are removed using wet etching process.
Then, step S303 is executed：PMOS metal gates, the PMOS metal gates packet are formed in the PMOS grooves
Include PMOS work-function layers.
The step of formation PMOS gate structures includes:First, it is sequentially formed from top to bottom in the PMOS grooves
Work-function layer and metal material layer；Then, chemical mechanical grinding is executed, to remove the groove outerwork function layer and metal material
Layer.
As shown in Fig. 4 C~4E, first, work-function layer 405 and metal material are sequentially depositing in the PMOS grooves 404
Layer 406 then executes chemical mechanical grinding, removes the work-function layer 405 and metal material layer 406 outside the PMOS grooves, from
And form PMOS metal gates 407.The constituent material of the work-function layer 405 is the metal material suitable for PMOS device, packet
Titanium, ruthenium, palladium, platinum, tungsten and its alloy are included, further includes carbide, nitride of above-mentioned metallic element etc..The work-function layer can be with
It is one layer to be made adjustment according to the requirement of device performance comprising multilayer.The method for forming the work-function layer can be
Any technique well-known to those skilled in the art, including it is heavy by chemical vapor deposition, atomic layer deposition or physical vapor
The suitable substance that product technique is formed.Illustratively, the PMOS work-function layers are TiN layer, and the TiN layer uses physical vapor
Depositing operation is formed, and thickness is 30 angstroms~60 angstroms.The metal material layer includes that the those skilled in the art such as tungsten, aluminium commonly use
Various metal materials, the method for forming the metal material layer includes this fields such as chemical vapor deposition, physical vapour deposition (PVD)
The technique of various matters known to technical staff, details are not described herein.Illustratively, using aluminium as metal material layer,
Thickness is between 2500 angstroms~4000 angstroms.Further, the aluminium as metal material layer includes cold aluminium and hot aluminium, described cold
Aluminium thickness is 300 angstroms~700 angstroms, and the hot al deposition temperature is at 400 DEG C or more.
Illustratively, further include being formed in the work-function layer before filling metal material layer 406 in the trench
The step of barrier layer, the barrier layer prevent the phase counterdiffusion between metal material layer and work-function layer, and the barrier layer can
To be the common various barrier materials of the those skilled in the art such as tantalum, tantalum nitride or titanium nitride institute.The formation barrier layer
The method that method is well known to those skilled in the art, details are not described herein.
Illustratively, soakage layer can also be formed between the barrier layer and metal gate material layer, the soakage layer can
Think that the various adaptation materials including titanium or titanium-aluminium alloy, the effect for forming soakage layer are to improve barrier layer and metal gates
Interfacial characteristics between material layer.Illustratively, TiAl is formed in PMOS work-function layers as soakage layer, the TiAl infiltrations
Layer is formed using physical gas-phase deposition, and the TiAl is 60 angstroms~150 angstroms as infiltration layer thickness.
It is to be appreciated that being not intended to this hair as embodiment using the technique for forming barrier layer and soakage layer in the present invention
Bright to be limited, selection is formed with or without barrier layer and coating to those skilled in the art as needed, and forms blocking
Layer and any one or more in coating.
Then, step S304 is executed：PMOS metal gates described in nitrogen treatment, the nitrogen treatment is by the PMOS work contents
Several layers are converted into nitrogen-enriched layer.
As illustrated in figure 4f, nitrogen treatment work is executed to the semiconductor substrate 400 for being formed with PMOS metal gates 407
Skill.Nitrogenation treatment technology introduces N element in work-function layer, to which work-function layer to be modified, forms richness N work-function layers,
On the one hand this richness N work-function layers reduce work-function layer leakage current caused by lapping liquid in chemical mechanical planarization process, subtract
The microcell circuit formed in small chemical mechanical planarization process causes corrosion and damage to PMOS work-function layers, on the other hand, wherein richness N
Work-function layer changes separation layer crystal crystal boundary, and then destroys the metal material layer in metal gates and be situated between to work-function layer and high K
The diffusion path of electric constant gate dielectric layer, it is therefore prevented that the diffusion of Al electrodes is further reduced in chemical mechanical planarization process and occurs
The possibility of corrosion improves the performance of semiconductor devices.Illustratively, the PMOS work-function layers TiN layer, is moved back by nitrogen
Ignition technique, the TiN layer are converted into rich nitrogen film, to reduce microcell electric current in chemical mechanical grinding, reduce PMOS work contents
Several losses；Rich nitrogen film can reduce metal material layer, such as Al simultaneously, and the diffusion to work-function layer is further reduced chemical machine
Loss in tool grinding.Illustratively, in the metal gates for being formed with soakage layer, the nitrogenation treatment technology can further by
Soakage layer is converted into nitrogen-enriched layer.It further, illustratively, can using nitrogenation treatment technology when being used as soakage layer using TiAl layers
TiAlN layers are converted by TiAl layers, to further decrease work-function layer in chemical mechanical planarization process caused by lapping liquid
Leakage current and reduce diffusion path of the metal material layer to work-function layer and high-dielectric-coefficient grid medium layer, reduce chemistry
The possibility corroded in mechanical grinding process.
Illustratively, the nitrogenation treatment technology using annealing process is carried out in a nitrogen atmosphere, illustratively, the nitrogen
Annealing process under gas atmosphere is used at 200~1000w of radio-frequency power, using containing N2O, and/or N2, and/or NH3Gas
50~100s annealing is carried out under atmosphere.Illustratively, under 900w power, using 200sccmN2O handles 90s or 400w power
Under, using 100sccmN2With 100sccmNH3Mixed gas handle 60s.
So far, the exemplary introduction of the method for the semiconductor devices of the present invention is completed.It will be appreciated that packet of the present invention
It includes but is not limited to the above embodiments the semiconductor devices to be formed.Illustratively, further include after the semiconductor devices is formed
The step of forming NMOS metal gates.
Illustratively, the step of formation NMOS metal gates include：The dummy grid material layer of the NMOS area is removed,
To form NMOS grooves；
NMOS work-function layers and metal material layer are sequentially formed from top to bottom in the NMOS grooves；
Chemical mechanical grinding is executed, to remove the NMOS work-function layers and metal material layer outside the NMOS grooves.
Referring now to Fig. 4 G to 4J, to describe the forming process of the NMOS metal gates in the present embodiment.
First, the dummy grid material for removing the NMOS area, to form NMOS grooves.
As shown in Figure 4 G, the dummy grid material layer 402 for removing the NMOS area is formed on 400 surface of semiconductor substrate
PMOS grooves 408.The method for removing the dummy grid material layer 402 can be familiar with various by those skilled in the art
Suitable process.As an example, in the present embodiment, by implementing dry etching, removing pseudo- gate electrode layer and puppet successively
Gate dielectric layer.The technological parameter of the dry etching includes：The flow of etching gas HBr is 20-500sccm, pressure 2-
40mTorr, power 100-2000W, wherein mTorr represent milli millimetres of mercury, and sccm represents cc/min.Implementing
After the dry etching, the etch residues and impurity that the dry etching generates are removed using wet etching process.
Then, NMOS metal gates are formed in the NMOS grooves, the NMOS metal gates include NMOS work functions
Layer and metal material layer.
The step of formation NMOS gate structure includes:First, it is sequentially formed from top to bottom in the NMOS grooves
Work-function layer and metal material layer；Then, chemical mechanical grinding is executed, to remove the groove outerwork function layer and metal material
Layer.
As shown in Fig. 4 H~4J, first, work-function layer 409 and metal material are sequentially depositing in the PMOS grooves 408
Layer 410 then executes chemical mechanical grinding, removes the work-function layer 409 and metal material layer 410 outside the PMOS grooves, from
And form NMOS metal gates 411.The constituent material of the work-function layer 409 is the various metal materials suitable for NMOS device
Material, including titanium, tantalum, aluminium, zirconium, hafnium and its alloy, further include carbide, nitride of above-mentioned metallic element etc..Form the work(
The method of function layer can be any technique well-known to those skilled in the art, including pass through chemical vapor deposition, atomic layer
Deposition or physical gas-phase deposition formed suitable substance, illustratively, the NMOS work-function layers be TiAl layers,
The lamination of TiN layer.Illustratively, it is formed using physical gas-phase deposite method for described TiAl layers, thickness is 40 angstroms~80 angstroms；Institute
It states TiN layer to be formed at 350 DEG C using physical gas-phase deposition, thickness is 40 angstroms~80 angstroms.The metal constitutes metal
Grid material, the metal gate material include the common various metal materials of the those skilled in the art such as tungsten, aluminium institute, form institute
The method for stating metal material layer includes the various things well-known to those skilled in the art such as chemical vapor deposition, physical vapour deposition (PVD)
Suitable technique, details are not described herein.Illustratively using aluminium as metal material layer.Further, described to be used as metal material layer
Aluminium include cold aluminium and hot aluminium, the cold aluminium thickness is 300 angstroms~700 angstroms, and the hot al deposition temperature is at 400 DEG C or more.
Illustratively, further include being formed in the work-function layer before filling metal material layer 410 in the trench
The step of barrier layer, the barrier layer prevent the phase counterdiffusion between metal material layer and work-function layer, and the barrier layer can
To be the common various barrier materials of the those skilled in the art such as tantalum, tantalum nitride or titanium nitride institute.The formation barrier layer
The method that method is well known to those skilled in the art, details are not described herein.
Illustratively, soakage layer can also be formed between the barrier layer and metal gate material layer, the soakage layer can
Think that the various adaptation materials including titanium or titanium-aluminium alloy, the effect for forming soakage layer are to improve barrier layer and metal gates
Interfacial characteristics between material layer.Illustratively, the soakage layer uses Ti layers, and described Ti layers uses physical gas-phase deposition
It is formed, thickness is 80 angstroms~130 angstroms.
It is to be appreciated that being not intended to this hair as embodiment using the technique for forming barrier layer and soakage layer in the present invention
Bright to be limited, selection is formed with or without boundary layer and coating to those skilled in the art as needed, and forms interface
It is one or more in layer and coating.
Embodiment two
A kind of manufacture of semiconductor devices of an alternative embodiment of the invention proposition is described with reference to figure 3 and Fig. 5 A~5J
Method, wherein Fig. 3 is the schematic flow chart for the method, semi-conductor device manufacturing method that an alternative embodiment of the invention proposes, figure
5A~5J is the semiconductor device that correlation step is related in the method, semi-conductor device manufacturing method that an alternative embodiment of the invention proposes
The structural schematic diagram figure of part.
First, step S301 is executed：The semiconductor substrate with NMOS area and the areas PMOS is provided, in the semiconductor substrate
On the dummy gate structure that is formed with dielectric layer and is located in the dielectric layer in NMOS area and the areas PMOS, the dummy grid
Structure includes dummy grid material layer.
As shown in Figure 5A, semiconductor substrate 500 is provided, the areas PMOS and NMOS area are formed in the semiconductor substrate 500,
It is formed with dielectric layer 502 in the semiconductor substrate 500, and is located at the dummy gate structure in the areas PMOS and NMOS area,
The dummy gate structure includes dummy grid material layer 501.The constituent material of the semiconductor substrate 400 can be undoped list
Crystal silicon, the monocrystalline silicon mixed with impurity, silicon-on-insulator (SOI) etc..
Illustratively, the forming step of the dummy gate structure includes：Dummy grid material is formed in semiconductor substrate 500
Layer 501；Pattern the dummy grid material layer；Source/drain region ion implanting is executed in the dummy gate structure both sides；Described half
Interlayer dielectric layer 502 is formed on conductor substrate；And chemical mechanical grinding is executed to expose the dummy grid material layer 501.
In addition, the semiconductor substrate is divided into as an example, being formed with isolation structure in the semiconductor substrate 500
The areas PMOS and NMOS area, the method for forming the isolation structure is known to one of skill in the art, is not repeated here herein.
The both sides of dummy gate structure 501 are formed with side wall construction, wherein side wall construction includes at least oxide skin(coating) and/or nitride layer.
The method for forming side wall construction is known to those skilled in the art, is not repeated here herein.Half in side wall construction both sides
It is formed with source/drain region in conductor substrate 500, embedded carbon is being respectively formed in the source/drain region in NMOS area and the areas PMOS
Silicon layer and embedded germanium silicon layer.The technical process of embedded carbon silicon layer and embedded germanium silicon layer is formed as those skilled in the art institute
It is familiar with, is not repeated here herein.It is formed with self-aligned silicide at the top of embedded carbon silicon layer and embedded germanium silicon layer, is
Simplification, it is illustrated that in omitted.
Then, step S302 is executed：The dummy grid material layer for removing the PMOS area, to form PMOS grooves.
As shown in Figure 5 B, the dummy grid material layer 501 for removing the PMOS area is formed on 500 surface of semiconductor substrate
PMOS grooves 503.The method for removing the dummy grid material layer 503 can be familiar with various by those skilled in the art
Suitable process.As an example, in the present embodiment, by implementing dry etching, removing pseudo- gate electrode layer and puppet successively
Gate dielectric layer.The technological parameter of the dry etching includes：The flow of etching gas HBr is 20-500sccm, pressure 2-
40mTorr, power 100-2000W, wherein mTorr represent milli millimetres of mercury, and sccm represents cc/min.Implementing
After the dry etching, the etch residues and impurity that the dry etching generates are removed using wet etching process.
Then, step S303 is executed：PMOS metal gates, the PMOS metal gates packet are formed in the PMOS grooves
Include PMOS work-function layers and metal material layer.
The step of formation PMOS gate structures includes:First, high k dielectric is sequentially formed in the PMOS grooves
Layer, work-function layer and metal material layer；Then, execute chemical mechanical grinding, with remove the PMOS grooves outerwork function layer and
Metal material layer.It is to be appreciated that in this present embodiment, high k dielectric layer, work function are sequentially formed in the PMOS grooves
Layer and metal material layer with formed the methods of metal gates using with metal gates work after a kind of elder generation of embodiment high k dielectric layer
Metal gate process after high k dielectric layer after skill is corresponding, after after high k dielectric layer metal gate process to the present embodiment into
Row explanation is not intended to limit the invention, any to carry out nitrogen treatment to work-function layer in metal gates forming process
Method be suitable for the present invention.
As shown in Fig. 5 C~5F, first, high k dielectric layer 504, work-function layer are sequentially depositing in the PMOS grooves 503
505 and metal material layer 506, then, chemical mechanical grinding is executed, the work-function layer 505 and gold outside the PMOS grooves are removed
Belong to material layer 506, to form PMOS metal gates 507.The constituent material of the work-function layer 505 is suitable for PMOS device
Metal material, including titanium, ruthenium, palladium, platinum, tungsten and its alloy further include carbide, nitride of above-mentioned metallic element etc..Institute
State work-function layer can be one layer can also include multilayer, made adjustment according to the requirement of device performance.Form the work function
The method of layer can be any technique well-known to those skilled in the art, including pass through chemical vapor deposition, atomic layer deposition
Or the suitable substance that physical gas-phase deposition is formed.Illustratively, the PMOS work-function layers are TiN layer, the TiN
Layer is formed using physical gas-phase deposition, and thickness is 30 angstroms~60 angstroms.The metal material layer includes this fields such as tungsten, aluminium
The common various metal materials of technical staff institute, the method for forming the metal material layer includes chemical vapor deposition, physics gas
The mutually technique of the various matters well-known to those skilled in the art such as deposition, details are not described herein.Illustratively, using aluminium conduct
Metal material layer, thickness is between 2500 angstroms~4000 angstroms.Further, the aluminium as metal material layer includes cold aluminium,
With hot aluminium, the cold aluminium thickness is 300 angstroms~700 angstroms, and the hot al deposition temperature is at 400 DEG C or more.
Illustratively, before forming the high k dielectric layer, interfacial TCO layer is formed in the channel bottom.The interface
Layer can be silica, the material of any suitable well-known to those skilled in the art such as silicon oxynitride.Form the boundary layer
Technique may be used thermal oxidation method, the technique well-known to those skilled in the art such as chemical meteorology deposition technique, herein no longer
It repeats.
Illustratively, it is formed before work-function layer after forming the high k dielectric layer, in the high k dielectric layer surface
It is formed with coating, the constituent material of coating includes lanthana, aluminium oxide, gallium oxide, indium oxide, molybdenum oxide ramet, oxygen
Nitrogen ramet, tantalum nitride, titanium nitride, molybdenum nitride, tungsten nitride, platinum, ruthenium, iridium etc. can pass through chemical vapor deposition, atomic layer deposition
The suitable substance that product or physical gas-phase deposition are formed.Illustratively, using physical gas-phase deposition, at 275 DEG C
For lower formation TaN as coating, thickness is 5 angstroms -20 angstroms.
Illustratively, further include being formed in the work-function layer before filling metal material layer 506 in the trench
The step of barrier layer, the barrier layer prevent the phase counterdiffusion between metal material layer and work-function layer, and the barrier layer can
To be the common various barrier materials of the those skilled in the art such as tantalum, tantalum nitride or titanium nitride institute.The formation barrier layer
The method that method is well known to those skilled in the art, details are not described herein.
Illustratively, soakage layer can also be formed between the barrier layer and metal gate material layer, the soakage layer can
Think that the various adaptation materials including titanium or titanium-aluminium alloy, the effect for forming soakage layer are to improve barrier layer and metal gates
Interfacial characteristics between material layer.Illustratively, TiAl is formed in PMOS work-function layers as soakage layer, the TiAl infiltrations
Layer is formed using physical gas-phase deposition, and the TiAl is 60 angstroms~150 angstroms as infiltration layer thickness.
It is to be appreciated that being not intended to this hair as embodiment using the technique for forming barrier layer and soakage layer in the present invention
Bright to be limited, selection is formed with or without boundary layer and coating to those skilled in the art as needed, and forms interface
Layer and any one or more in coating.
Then, step S304 is executed：PMOS metal gates described in nitrogen treatment, the nitrogen treatment is by the PMOS work contents
Several layers are converted into nitrogen-enriched layer.
As depicted in fig. 5g, PMOS metal gates 507 described in nitrogen treatment convert PMOS work-function layers 505 to rich nitrogen
Layer.Nitrogenation treatment technology introduces N element in work-function layer, to which work-function layer to be modified, forms richness N work-function layers,
On the one hand this richness N work-function layers reduce work-function layer leakage current caused by lapping liquid in chemical mechanical planarization process, subtract
The microcell circuit formed in small chemical mechanical planarization process causes corrosion and damage to PMOS work-function layers, on the other hand, wherein richness N
Work-function layer changes separation layer crystal crystal boundary, and then destroys the metal material layer in metal gates to work-function layer and high dielectric
The diffusion path of constant gate dielectric layer, it is therefore prevented that the diffusion of Al electrodes is further reduced in chemical mechanical planarization process and corruption occurs
The possibility of erosion improves the performance of semiconductor devices.Illustratively, the PMOS work-function layers TiN layer, by n 2 annealing
Technique, the TiN layer are converted into rich nitrogen film, to reduce microcell electric current in chemical mechanical grinding, reduce PMOS work functions
Loss；Rich nitrogen film can reduce metal material layer, such as Al simultaneously, and the diffusion to work-function layer is further reduced chemical machinery
Loss in grinding.Illustratively, in the metal gates for being formed with soakage layer, the nitrogenation treatment technology can be further by leaching
Profit layer is converted into nitrogen-enriched layer, illustratively, when being used as soakage layer using TiAl layers, can be turned TiAl layers using nitrogenation treatment technology
TiAlN layers are turned to, to further decrease leakage current of the work-function layer in chemical mechanical planarization process caused by lapping liquid
And diffusion path of the metal material layer to work-function layer and high-dielectric-coefficient grid medium layer is reduced, reduce chemical mechanical grinding mistake
The possibility corroded in journey.
Illustratively, the nitrogenation treatment technology using annealing process is carried out in a nitrogen atmosphere, illustratively, the nitrogen
Annealing process under gas atmosphere is used at 200~1000w of radio-frequency power, using the gas containing N2O, and/or N2, and/or NH3
50~100s annealing is carried out under atmosphere.Illustratively, under 900w power, 90s or 400w power is handled using 200sccmN2O
Under, 60s is handled using the mixed gas of 100sccmN2 and 100sccmNH3.
So far, the exemplary introduction of the method for the semiconductor devices of the present invention is completed.It will be appreciated that packet of the present invention
It includes but is not limited to the above embodiments the semiconductor devices to be formed.Illustratively, further include after the semiconductor devices is formed
The step of forming NMOS metal gates.
Illustratively, the step of formation NMOS metal gates include：The dummy grid material layer of the NMOS area is removed,
To form NMOS grooves；
Sequentially form high k dielectric layer, NMOS work-function layers and metal material layer from top to bottom in the NMOS grooves；
Chemical mechanical grinding is executed, to remove the NMOS work-function layers and metal material layer outside the NMOS grooves.
Referring now to Fig. 5 H to 5J, to describe the forming process of the NMOS metal gates in the present embodiment.
First, the dummy grid material for removing the NMOS area, to form NMOS grooves.
As illustrated in fig. 5h, the dummy grid material layer 501 for removing the NMOS area is formed on 500 surface of semiconductor substrate
PMOS grooves 508.The method for removing the dummy grid material layer 501 can be familiar with various by those skilled in the art
Suitable process.As an example, in the present embodiment, by implementing dry etching, removing dummy grid material layers successively
With dummy grid dielectric layer.The technological parameter of the dry etching includes：The flow of etching gas HBr is 20-500sccm, pressure
Milli millimetres of mercury is represented for 2-40mTorr, power 100-2000W, wherein mTorr, sccm represents cc/min.
After implementing the dry etching, the etch residues and impurity that the dry etching generates are removed using wet etching process.
Then, NMOS metal gates are formed in the NMOS grooves, the NMOS metal gates include NMOS work functions
Layer and metal material layer.
The step of formation NMOS gate structure includes:First, high k dielectric is sequentially formed in the NMOS grooves
Layer, work-function layer and metal material layer；Then, chemical mechanical grinding is executed, to remove the groove outerwork function layer and metal
Material layer.
As shown in Fig. 5 I~5J, first, high k dielectric layer 509, work-function layer are sequentially depositing in the PMOS grooves 508
510 and metal material layer 511, then, chemical mechanical grinding is executed, the work-function layer 510 and gold outside the PMOS grooves are removed
Belong to material layer 511, to form NMOS metal gates 512.The constituent material of the work-function layer 510 is suitable for NMOS device
Metal material, including titanium, tantalum, aluminium, zirconium, hafnium and its alloy further include carbide, nitride of above-mentioned metallic element etc..Shape
Method at the work-function layer can be any technique well-known to those skilled in the art, including pass through chemical vapor deposition
The suitable substance that product, atomic layer deposition or physical gas-phase deposition are formed, illustratively, the NMOS work-function layers are
TiAl layers, the lamination of TiN layer.Illustratively, formed using physical gas-phase deposite method for described TiAl layers, thickness be 40 angstroms~
80 angstroms；The TiN layer is formed using physical gas-phase deposition at 350 DEG C, and thickness is 40 angstroms~80 angstroms.The metal structure
At metal gate material, the metal gate material includes the common various metal materials of the those skilled in the art such as tungsten, aluminium institute,
The method for forming the metal material layer includes that chemical vapor deposition, physical vapour deposition (PVD) etc. are well-known to those skilled in the art
The technique of various matters, details are not described herein.Illustratively using aluminium as metal material layer.Further, described to be used as metal
The aluminium of material layer includes cold aluminium and hot aluminium, and the cold aluminium thickness is 300 angstroms~700 angstroms, and the hot al deposition temperature is at 400 DEG C
More than.
Illustratively, before forming the high k dielectric layer, interfacial TCO layer is formed in the channel bottom.The interface
Layer can be silica, the material of any suitable well-known to those skilled in the art such as silicon oxynitride.Form the boundary layer
Technique may be used thermal oxidation method, the technique well-known to those skilled in the art such as chemical meteorology deposition technique, herein no longer
It repeats.
Illustratively, it is formed before work-function layer after forming the high k dielectric layer, in the high k dielectric layer surface
It is formed with coating, the constituent material of coating includes lanthana, aluminium oxide, gallium oxide, indium oxide, molybdenum oxide ramet, oxygen
Nitrogen ramet, tantalum nitride, titanium nitride, molybdenum nitride, tungsten nitride, platinum, ruthenium, iridium etc. can pass through chemical vapor deposition, atomic layer deposition
The suitable substance that product or physical gas-phase deposition are formed, thickness are 5 angstroms -20 angstroms.
Illustratively, further include being formed in the work-function layer before filling metal material layer 511 in the trench
The step of barrier layer, the barrier layer prevent the phase counterdiffusion between metal material layer and work-function layer, and the barrier layer can
To be the common various barrier materials of the those skilled in the art such as tantalum, tantalum nitride or titanium nitride institute.The formation barrier layer
The method that method is well known to those skilled in the art, details are not described herein.
Illustratively, soakage layer can also be formed between the barrier layer and metal gate material layer, the soakage layer can
Think that the various adaptation materials including titanium or titanium-aluminium alloy, the effect for forming soakage layer are to improve barrier layer and metal gates
Interfacial characteristics between material layer, the technique that the formation process and process of the soakage layer are well known to those skilled in the art,
This will not be repeated here.
So far, the exemplary introduction to the present invention is completed in above-described embodiment, it will be appreciated herein that being adopted in the application
Exemplary Jie is carried out to the present invention with metal gate process after metal gate process after first high k dielectric layer and rear high k dielectric layer
It continues and does not really want to limit the invention, wherein PMOS metal gates and the forming step of NMOS metal gates are also not limited to
Step described herein, it is to be understood that any be initially formed after PMOS work functions completes NMOS chemical mechanical grindings again
Semiconductor devices forming process be suitable for the present invention.
In conclusion the manufacturing method of semiconductor device according to the invention, executes after forming PMOS gate structures
N 2 annealing technique so that PMOS work-function layers are converted into nitrogen-enriched layer, on the one hand, reduce in the chemistry for forming NMOS metal gates
In mechanical milling tech, the leakage current at PMOS work-function layers interface caused by lapping liquid causes corrosion to damage PMOS work-function layers
It is bad, on the other hand, diffusion of the metal material layer to the other materials layer of metal gates is prevented, chemical mechanical grinding is further reduced
The possibility corroded in the process improves the performance of semiconductor devices, reduces metal gates defect, promotes device performance.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (10)
1. a kind of manufacturing method of semiconductor devices, which is characterized in that the method includes：
Semiconductor substrate with NMOS area and the areas PMOS is provided, is formed with dielectric layer and difference on the semiconductor substrate
Dummy gate structure in the dielectric layer in the NMOS area and the areas PMOS, the dummy gate structure includes dummy grid
Material layer；
The dummy grid material layer for removing the areas PMOS, to form PMOS grooves；
PMOS metal gates are formed in the PMOS grooves, the PMOS metal gates include PMOS work-function layers；
PMOS metal gates described in nitrogen treatment, the nitrogen treatment convert the PMOS work-function layers to nitrogen-enriched layer.
2. the method as described in claim 1, which is characterized in that the nitrogen treatment is included in the lehr attendant under nitrogen containing atmosphere
Skill.
3. method as claimed in claim 2, which is characterized in that the annealing process under nitrogen containing atmosphere is in radio-frequency power
Under 200~1000w, using N2O, and/or N2, and/or NH3Gas carries out 50~100s annealing.
4. the method as described in claim 1, which is characterized in that the PMOS metal gates further include PMOS soakage layers, described
Nitrogen treatment further includes converting the soakage layer to nitrogen-enriched layer.
5. the method as described in claim 1, which is characterized in that the PMOS work-function layers include TiN.
6. method as claimed in claim 4, which is characterized in that the PMOS soakage layers include TiAl.
7. the method as described in claim 1, which is characterized in that further include carrying out PMOS metal gates described in nitrogen treatment
The step of NMOS metal gates are formed after step.
8. the method as described in claim 1, which is characterized in that described the step of forming PMOS grids in the PMOS grooves
Including:
PMOS work-function layers and metal material layer are sequentially formed from top to bottom in the PMOS grooves；
Chemical mechanical grinding is executed, to remove the PMOS work-function layers and metal material layer outside the PMOS grooves.
9. the method for claim 7, which is characterized in that described to form NMOS metal gates in the NMOS grooves
Step includes:
The dummy grid material layer for removing the NMOS area, to form NMOS grooves；
NMOS work-function layers and metal material layer are sequentially formed from top to bottom in the NMOS grooves；
Chemical mechanical grinding is executed, to remove the NMOS work-function layers and metal material layer outside the NMOS grooves.
10. the method as described in claim 1, which is characterized in that the dummy gate structure further includes being located at the dummy grid material
High k dielectric layer below the bed of material, and/or the boundary layer that is formed between the semiconductor substrate and the high k dielectric layer.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102956455A (en) * | 2011-08-19 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor devices |
| CN104979290A (en) * | 2014-04-04 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Complementary metal oxide semiconductor (CMOS) device structure and manufacturing method thereof |
| CN105990118A (en) * | 2015-02-17 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, fabrication method thereof and electronic apparatus |
| CN105990237A (en) * | 2015-02-04 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof, and electronic device |
| CN106257620A (en) * | 2015-06-18 | 2016-12-28 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor device and manufacture method, electronic installation |
-
2017
- 2017-03-17 CN CN201710161584.4A patent/CN108630608A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102956455A (en) * | 2011-08-19 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor devices |
| CN104979290A (en) * | 2014-04-04 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Complementary metal oxide semiconductor (CMOS) device structure and manufacturing method thereof |
| CN105990237A (en) * | 2015-02-04 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof, and electronic device |
| CN105990118A (en) * | 2015-02-17 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, fabrication method thereof and electronic apparatus |
| CN106257620A (en) * | 2015-06-18 | 2016-12-28 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor device and manufacture method, electronic installation |
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Application publication date: 20181009 |