CN108628774A - Memorizer control circuit unit, memory storage apparatus and signal acceptance method - Google Patents
Memorizer control circuit unit, memory storage apparatus and signal acceptance method Download PDFInfo
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- CN108628774A CN108628774A CN201710161613.7A CN201710161613A CN108628774A CN 108628774 A CN108628774 A CN 108628774A CN 201710161613 A CN201710161613 A CN 201710161613A CN 108628774 A CN108628774 A CN 108628774A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
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- G06F13/1668—Details of memory controller
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Abstract
A kind of memorizer control circuit unit of present invention offer, memory storage apparatus and signal acceptance method.In an exemplary embodiment, the memory interface circuit of memorizer control circuit unit receives the first signal from volatile memory and adjusts the voltage value of the first signal to a voltage range in response to the internal driving of memory interface circuit, wherein the median of this voltage range is not equal to a preset voltage value, and the half of the voltage value and the summation of the voltage value with reference to ground voltage for the supply voltage that this preset voltage value is memory interface circuit.In addition, memory interface circuit generates input signal also according to the voltage relativeness between the first signal and internal reference voltage.
Description
Technical field
The present invention relates to a kind of signal reception technique more particularly to a kind of memorizer control circuit unit, memory storages
Device and signal acceptance method.
Background technology
Digital camera, mobile phone and MP3 player are very rapid in growth over the years so that consumer is to storage
The demand of media also rapidly increases.Due to reproducible nonvolatile memorizer module (rewritable non-volatile
Memory module) (for example, flash memory) have data non-volatile, power saving, small, and without mechanical structure etc.
Characteristic, so being very suitable for being built into above-mentioned illustrated various portable multimedia devices.
The storage device of some types is configured with reproducible nonvolatile memorizer module and dynamic randon access simultaneously
The volatile memory such as memory (Dynamic random access memory, DRAM), to provide the long-term storage of data
With temporary buffer.In the storage device configured with volatile memory, signal receiving end as volatile memory is deposited
It is generally provided with termination resistance in memory interface circuit, to maintain the signal quality of the high speed signal from volatile memory.
But the setting of termination resistance but also improve signal receiving end power consumption.
Invention content
A kind of memorizer control circuit unit of present invention offer, memory storage apparatus and signal acceptance method, can reduce
Power consumption when memory interface circuit receives signal from volatile memory.
One example of the present invention embodiment provides a kind of memorizer control circuit unit, to control volatile storage
Device, the memorizer control circuit unit includes Memory Controller and memory interface circuit.The memory interface circuit
It is connected to the Memory Controller.The memory interface circuit to receive from the volatile memory first letter
Number.The memory interface circuit is also to the internal driving in response to the memory interface circuit and by first signal
Voltage value adjust to a voltage range.The median of the voltage range is not equal to preset voltage value.The preset voltage value
For the half of the voltage value and the summation of the voltage value with reference to ground voltage of the supply voltage of the memory interface circuit.It is described
Memory interface circuit also inputs to be generated according to the voltage relativeness between first signal and internal reference voltage
Signal.
In one example of the present invention embodiment, the memory interface circuit includes impedor, to provide
Internal driving is stated, wherein the first end of the impedor is connected to the RX path of first signal, and the impedance element
The second end of part be connected to the supply voltage or it is described refer to ground voltage.
In one example of the present invention embodiment, before receiving first signal, the memory interface circuit is also
To receive the second signal from the volatile memory.The memory interface circuit is also to the second signal
Partial pressure operation is executed to generate the internal reference voltage.
In one example of the present invention embodiment, the memory interface circuit also reads instruction sequence to send to preset
The preset data of the volatile memory is read with instruction.The volatile memory is to according to the default reading instruction
Sequence generates the second signal.
In one example of the present invention embodiment, the memory interface circuit includes comparison circuit.The comparison circuit
To the voltage value of the internal reference voltage and first signal to generate the input signal.
In one example of the present invention embodiment, the memory interface circuit includes the first connecting interface, the second connection
Interface and reference voltage generator.First connecting interface is being connected to the Memory Controller.Second connection
Interface is being connected to the volatile memory.The reference voltage generator be connected to first connecting interface with it is described
Second connecting interface.The reference voltage generator to via first connecting interface detect the internal driving, via
Second connecting interface detects the external impedance of the volatile memory and generates the inside according to the testing result
Reference voltage.
In one example of the present invention embodiment, the reference voltage generator includes voltage detecting circuit, to sound
Internal driving described in Ying Yu and the external impedance and the first voltage for detecting the impedor in the memory interface circuit.
The voltage value of the first voltage is positively correlated with the voltage value of the supply voltage.
In one example of the present invention embodiment, the reference voltage generator further includes bleeder circuit and voltage output electricity
Road.The bleeder circuit is connected to the voltage detecting circuit and to second of the output end to the voltage detecting circuit
Voltage executes partial pressure operation.The voltage follower circuit is connected to the bleeder circuit and in response to the bleeder circuit
Output end tertiary voltage and generate the internal reference voltage.
Another example of the present invention embodiment provides a kind of memory storage apparatus comprising connecting interface unit can answer
Write formula non-volatile memory module, volatile memory and memorizer control circuit unit.The connecting interface unit to
It is connected to host system.It is non-easily that the memorizer control circuit unit is connected to the connecting interface unit, the duplicative
The property lost memory module and the volatile memory.The memorizer control circuit unit comes from the volatibility to receive
First signal of memory.The memorizer control circuit unit is also in response in the memorizer control circuit unit
Portion's impedance and the voltage value of first signal is adjusted to a voltage range.The median of the voltage range is not equal to default
Voltage value.The preset voltage value is the electricity of the voltage value and reference ground voltage of the supply voltage of the memory interface circuit
The half of the summation of pressure value.The memorizer control circuit unit also to according to first signal and internal reference voltage it
Between voltage relativeness generate input signal.
In one example of the present invention embodiment, the memorizer control circuit unit includes impedor, to carry
For the internal driving.The first end of the impedor is connected to the RX path of first signal, and the impedance element
The second end of part be connected to the supply voltage or it is described refer to ground voltage.
In one example of the present invention embodiment, the third end of the impedor is to receive enable signal, wherein institute
It states impedor and provides the internal driving in response to the enable signal.
In one example of the present invention embodiment, the enable time of the enable signal is positively correlated with believes via described first
The sum of number multiple binary digits continuously transmitted.
In one example of the present invention embodiment, before receiving first signal, the memorizer control circuit list
Member is also receiving the second signal from the volatile memory.The memorizer control circuit unit is also to described
Second signal executes partial pressure operation to generate the internal reference voltage.
In one example of the present invention embodiment, the memorizer control circuit unit also instructs to send default read
Sequence is to indicate to read the preset data of the volatile memory.The volatile memory is to according to the default reading
Instruction sequence generates the second signal.
In one example of the present invention embodiment, the memorizer control circuit unit includes comparison circuit.The comparison
Circuit is to the voltage value of the internal reference voltage and first signal to generate the input signal.
In one example of the present invention embodiment, the volatile memory is providing external impedance.First letter
Number the voltage value be additionally in response to the external impedance and be adjusted to the voltage range.
Another example of the present invention embodiment provides a kind of signal acceptance method, is used to include depositing for volatile memory
Reservoir storage device, the signal acceptance method include：It is received from the volatile memory by memory interface circuit
First signal；The voltage value of first signal is adjusted to a voltage in response to the internal driving of the memory interface circuit
Range, wherein the median of the voltage range is not equal to preset voltage value, and the preset voltage value is that the memory connects
The half of the voltage value and the summation of the voltage value with reference to ground voltage of the supply voltage of mouth circuit；And believe according to described first
Voltage relativeness number between internal reference voltage generates input signal.
In one example of the present invention embodiment, the signal acceptance method further includes：By memory interface electricity
The impedor on road provides the internal driving, wherein the first end of the impedor is connected to the reception of first signal
Path, and the second end of the impedor be connected to the supply voltage or it is described refer to ground voltage.
In one example of the present invention embodiment, the signal acceptance method further includes：By the of the impedor
Three ends receive enable signal；And the internal driving is provided in response to the enable signal by the impedor.
In one example of the present invention embodiment, the signal acceptance method further includes：Control the enable signal
The enable time so that the enable time is positively correlated with the total of the multiple binary digits continuously transmitted via first signal
Number.
In one example of the present invention embodiment, the signal acceptance method further includes：Receiving first signal
Before, the second signal from the volatile memory is received by the memory interface circuit；And to second letter
Number execute partial pressure operation to generate the internal reference voltage.
In one example of the present invention embodiment, the signal acceptance method further includes：Send default reading sequence of instructions
Row are to indicate to read the preset data of the volatile memory；And by the volatile memory according to the default reading
Instruction sequence generates the second signal.
In one example of the present invention embodiment, according between first signal and the internal reference voltage
Voltage relativeness generate the input signal the step of include：Compare the institute of the internal reference voltage and first signal
State voltage value；And the input signal is generated according to comparison result.
In one example of the present invention embodiment, the signal acceptance method further includes：By the volatile memory
External impedance is provided；And the voltage value of first signal is adjusted to the voltage model in response to the external impedance
It encloses.
In one example of the present invention embodiment, the volatile memory includes forth generation double data rate synchronous dynamic
Random access memory.
Based on above-mentioned, specific receiving terminal circuit, which is arranged, in present invention proposition in memory interface circuit will come from easily
The voltage value of first signal of the property lost memory is adjusted to the voltage range and is analyzed using suitable internal reference voltage
First signal.Thereby, the correctness of input signal caused by can maintaining, and the power that can be reduced when receiving the first signal disappears
Consumption.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to coordinate attached drawing to make
Carefully it is described as follows.
Description of the drawings
Fig. 1 is the schematic diagram of the memory storage apparatus shown by an exemplary embodiment according to the present invention.
Fig. 2 is the schematic diagram of the memory interface circuit shown by an exemplary embodiment according to the present invention.
Fig. 3 is the schematic diagram of the first signal shown by an exemplary embodiment according to the present invention.
Fig. 4 is the schematic diagram of the generating circuit from reference voltage shown by an exemplary embodiment according to the present invention.
Fig. 5 is the schematic diagram of the memory interface circuit shown by another exemplary embodiment according to the present invention.
Fig. 6 is the schematic diagram of the first signal shown by another exemplary embodiment according to the present invention.
Fig. 7 is the schematic diagram of the memory interface circuit shown by another exemplary embodiment according to the present invention.
Fig. 8 is the schematic diagram of the first signal shown by another exemplary embodiment according to the present invention.
Fig. 9 is the schematic diagram of the memory storage apparatus shown by another exemplary embodiment according to the present invention.
Figure 10 is the flow chart of the signal acceptance method shown by an exemplary embodiment according to the present invention.
Reference sign
10、90：Memory storage apparatus
11、904：Memorizer control circuit unit
111：Memory Controller
112：Memory interface circuit
12、908：Volatile memory
21、22、R1、R2、R3、R4：Impedor
23：Comparison circuit
ENA、ENB、SRX、SIN、VREF、V1、V2、V3：Signal
TA、TB：Transistor
OPA：Operational amplifier
VDD：Supply voltage
GND：With reference to ground voltage
40：Generating circuit from reference voltage
41：Voltage detecting circuit
42：Bleeder circuit
43：Voltage follower circuit
VCEN：Predeterminated voltage
VIH：Upper critical voltage
VIL：Lower critical voltage
902：Connecting interface unit
906：Reproducible nonvolatile memorizer module
S1001：Step (receives the first signal from volatile memory) by memory interface circuit
S1002：Step (adjusts the voltage value of the first signal to an electricity in response to the internal driving of memory interface circuit
Press range)
S1003：Step (being to generate input signal according to opposite close of the voltage between the first signal and internal reference voltage)
Specific implementation mode
Multiple exemplary embodiments set forth below illustrate the present invention, however the present invention be not limited only to illustrated by multiple examples
Embodiment.Again combination appropriate is also still allowed between exemplary embodiment.In this case specification full text (including claims)
Used " connection " word can refer to any direct or indirect connection means.For example, if it is described herein that first device connects
It is connected to second device, then should be construed as the first device and can be directly connected to the second device or the first device
It can be coupled indirectly to the second device by other devices or certain connection means.In addition, " signal " word can refer to
A few electric current, voltage, charge, temperature, data or any other one or more signal.
Fig. 1 is the schematic diagram of the memory storage apparatus shown by an exemplary embodiment according to the present invention.Please refer to figure
1, memory storage apparatus 10 includes memorizer control circuit unit 11 and volatile memory 12.Memorizer control circuit unit
11 can be encapsulated as a chip or the electronic circuit by being laid on an at least circuit board forms.In this exemplary embodiment
In, volatile memory 12 is forth generation double data rate Synchronous Dynamic Random Access Memory (Double Data Rate
4Synchronous Dynamic Random Access Memory,DDR 4SDRAM).It is volatile in another exemplary embodiment
Property memory 12 can also include other kinds of volatile memory, for example, third generation double data rate synchronous dynamic random
Access memory (DDR 3SDRAM) etc..In addition, the sum of volatile memory 12 can be one or more.
Memorizer control circuit unit 11 and volatile memory 12 be installed in memory storage apparatus 10 one or
On multiple circuit boards.Memorizer control circuit unit 11 supports the data access operation for volatile memory 12.In a model
In example embodiment, memorizer control circuit unit 11 is considered as the control chip of volatile memory 12, and volatile memory
12 are considered as cache (cache) memory or buffer storage (buffer) of memorizer control circuit unit 11.
Memorizer control circuit unit 11 includes Memory Controller 111 and memory interface circuit 112.Memory controls
Device 111 is connected to memory interface circuit 112.Memory Controller 112 is for controlling volatile memory 12.In example reality
It applies in example, Memory Controller 112 is also referred to as dynamic RAM Controller (DRAM controller).
Memory interface circuit 112 by Memory Controller 111 being connected to volatile memory 12.When being intended to from volatile
Property memory 12 in when reading in data or storage data to volatile memory 12, Memory Controller 111 can via storage
Device interface circuit 112 sends an instruction sequence to volatile memory 12.When volatile memory 12 receives this instruction sequence
When, volatile memory 12 can be stored corresponding to the write-in data of this instruction sequence or be returned via memory interface circuit 112
The reading data corresponding to this instruction sequence are passed to Memory Controller 111.In addition, in memory interface circuit 112, write-in
Data or reading data are transmitted in the form of data-signal.For example, data-signal can be used to transmit including binary digit " 1 " with
The binary digit data of binary digit " 0 ".
In this exemplary embodiment, volatile memory 12 is double data rate Synchronous Dynamic Random Access Memory, because
The rising edge (rising edges) and falling edge (falling edges) of the clock signal of this memory interface circuit 112 are all
The data-signal of (for example, sampling) from volatile memory 12 can be used for parsing.In other words, in a clock cycle
In (clock cycle), the data that memory interface circuit 112 can execute volatile memory 12 twice are written or read
It takes.
In this exemplary embodiment, memory interface circuit 112 meets stub series termination logic (Stub Series
Terminated Logic, SSTL) I/O standards, such as SSTL-2, SSTL-3, SSTL-15 or SSTL-18 etc..In this example reality
Apply in example, memory interface circuit 112 include connecting interface 1311 (also referred to as the first connecting interface) with connecting interface 1312 (
Referred to as the second connecting interface).Connecting interface 1311 to connect Memory Controller 111 and memory interface circuit 112, and
Connecting interface 1312 is connecting memory interface circuit 112 and volatile memory 12.In this exemplary embodiment, connection connects
Mouth 1312 includes multiple conductive connecting pins (pin).Memory interface circuit 112 is connected to volatile storage via these conductive connecting pins
Device 12.In this exemplary embodiment, these conductive connecting pins include at least a pin for being used for transmission data-signal and (also referred to as count
According to pin).For example, data pins can be DQ pins.Thereby, data-signal can be through thus data pins in memory interface electricity
It is transmitted between road 112 and volatile memory 12.In another exemplary embodiment, these conductive connecting pins can also include other work(
Energy property pin, as long as connection standard used by meeting.In addition, in an exemplary embodiment, connecting interface 1311 also may be used
Including at least one conductive connecting pin.The sum of conductive connecting pin in connecting interface 1311 may be the same or different in connecting interface 1312
In conductive connecting pin sum.
Fig. 2 is the schematic diagram of the memory interface circuit shown by an exemplary embodiment according to the present invention.Please refer to Fig. 1
With Fig. 2, memory interface circuit 112 can receive the signal SRX (also referred to as the first signal) from volatile memory 12.So
Afterwards, memory interface circuit 112 understands signal Analysis SRX and generates signal SIN (also referred to as input signal).For example, according to signal
The pattern of SIN, Memory Controller 111 can be with the binary digit data representated by identification signal SRX binary digit " 0 " or
“1”。
In this exemplary embodiment, memory interface circuit 112 includes impedor 21, impedor 22 and comparison circuit
23.Comparison circuit 23 is connected to impedor 21 and impedor 22.The first end of impedor 21 is connected to connecing for signal SRX
Path is received, and the second end of impedor 21 is connected to the supply voltage VDD of memory interface circuit 112.In addition, impedor
22 first end is also connected to the RX path of signal SRX, and the second end of impedor 22 is then connected to memory interface electricity
The reference ground voltage GND on road 112.From the point of view of another angle, impedor 21 and 22 is to be serially connected in memory interface circuit 112
Supply voltage VDD and with reference between ground voltage GND.
Impedor 21 and 22 is providing impedance to the RX path of signal SRX.In this exemplary embodiment, impedance element
The impedance that part 21 and 22 provides is also referred to as the internal driving of memory interface circuit 112.For example, this internal driving can have one
A resistance value or reactance value.In this exemplary embodiment, impedor 21 has identical (or close) with the impedance that 22 provide
Resistance value or reactance value.In another exemplary embodiment, the impedance of impedance and 22 offers that impedor 21 provides then has not
Same resistance value or reactance value.In an exemplary embodiment, impedor 21 and at least one of 22 are also referred to as memory
Core on-die termination (on-die termination, ODT) impedor of interface circuit 112.
In this exemplary embodiment, impedor 21 includes an at least transistor TA, and impedor 22 includes at least one
Transistor TB.Transistor TA and TB can provide the equiva lent impedance of this internal driving jointly or respectively.However, implementing in another example
In example, impedor 21 and 22 can also respectively include the electronics that at least one resistance etc. can be used to provide resistance value or reactance value
Element.
In this exemplary embodiment, the third end of impedor 21 is receiving signal ENA, and the of impedor 22
Three ends are receiving signal ENB.Signal ENA is to start the enable signal of impedor 21, and signal ENB is to open
The enable signal of impedance,motional element 22.When receiving signal ENA, impedor 21 can be activated.If impedor 21 is opened
Dynamic, then the path between the RX path of signal SRX and supply voltage VDD (also referred to as the first impedance path) can be switched on, and
And the impedance that signal SRX can be provided by impedor 21 is influenced.If conversely, not receiving signal ENA, impedor
21 are not activated, and the impedance that signal SRX will not be provided by impedor 21 is influenced.In other words, impedor 21 can
Internal driving is provided to the RX path of signal SRX in response to signal ENA.
On the other hand, when receiving signal ENB, impedor 22 can be activated.If impedor 22 is activated, believe
It the RX path of number SRX and can be switched on, and believe with reference to the path (also referred to as the second impedance path) between ground voltage GND
The impedance that number SRX can be provided by impedor 22 is influenced.If conversely, not receiving signal ENB, impedor 22 is not
It is activated, and the impedance that signal SRX will not be provided by impedor 22 is influenced.In other words, impedor 22 can respond
Internal driving is provided to the RX path of signal SRX in signal ENB.
Fig. 3 is the schematic diagram of the first signal shown by an exemplary embodiment according to the present invention.Fig. 2 and Fig. 3 are please referred to,
In sometime range, if impedor 21 and 22 is in starting state (that is, signal ENA and ENB is existed simultaneously) simultaneously,
In response to the impedance that impedor 21 and 22 provides jointly, the voltage value of signal SRX can be adjusted to a voltage range (
Referred to as predetermined voltage range).The upper critical voltage of this predetermined voltage range can supply the voltage of voltage VDD close to (or being equal to)
Value, and the lower critical voltage of this predetermined voltage range can refer to the voltage value of ground voltage GND, such as Fig. 3 close to (or being equal to)
It is shown.In other words, it is influenced by impedor 21 and the impedance that 22 provide jointly, the voltage value of signal SRX can supplied
It rises and falls between the voltage value and the voltage value of reference ground voltage GND of voltage VDD.But the it is noted that electricity of signal SRX
Pressure value is not above the voltage value of supply voltage VDD, will not be less than the voltage value with reference to ground voltage GND.
On the other hand, a signal VREF (also referred to as internal reference voltage) can be used to determine that current demand signal SRX is to use
To transmit binary digit " 1 " or " 0 ".For example, in the exemplary embodiment of Fig. 3, the voltage value (about) of signal VREF is equal to supply
A median (also referred to as preset voltage value) between the voltage value and the voltage value of reference ground voltage GND of voltage VDD.Example
Such as, this preset voltage value (about) is equal to the voltage value and the one of the summation of the voltage value with reference to ground voltage GND of supply voltage VDD
Half.If the voltage value of current demand signal SRX is higher than the voltage value of signal VREF, indicate that current demand signal SRX is for transmitting binary system
Position " 1 ".If the voltage value of current demand signal SRX be less than signal VREF voltage value, indicate current demand signal SRX be for transmit two into
Position " 0 " processed.
It is noted that in another exemplary embodiment of Fig. 3, if the voltage value of current demand signal SRX is higher than signal VREF
Voltage value, also can be considered that current demand signal SRX is for transmitting binary digit " 0 ".If the voltage value of current demand signal SRX is less than letter
The voltage value of number VREF, also can be considered that current demand signal SRX is for transmitting binary digit " 1 ".
From the point of view of specific, memory interface circuit 112 can according to the voltage relativeness between signal SRX and signal VREF come
Generate signal SIN.For example, comparison circuit 23 may include an operational amplifier (operational amplifier, OPA).Compare
Circuit 23 can receive the voltage value of signal SRX and signal VREF and comparison signal SRX and signal VREF.By comparing signal SRX
With the voltage value of signal VREF, the voltage relativeness between signal SRX and signal VREF can be obtained.If signal SRX and letter
Voltage relativeness between number VREF is that the voltage value of signal SRX is higher than the voltage value of signal VREF, then corresponds to a certain two
The signal SIN of system position data (for example, binary digit " 1 ") can be exported.If the voltage phase between signal SRX and signal VREF
It is less than the voltage value of signal VREF to the voltage value that relationship is signal SRX, then corresponds to another binary digit data (for example, two
System position " 0 ") signal SIN can be exported.In other words, according to the voltage relativeness between signal SRX and signal VREF, letter
The binary digit data that number SRX is transmitted can be obtained.
In this exemplary embodiment, memory interface circuit 112 can also be provided according to current memory interfaces circuit 112
Impedance (also referred to as external impedance) that impedance (that is, internal driving) and volatile memory 12 provide and dynamic generates signal
VREF.For example, at least one impedor is also equipped in volatile memory 12, to provide this external impedance.One
In exemplary embodiment, offline chip drives are also referred to as to provide the impedor of this external impedance in volatile memory 12
(off-chip driver, OCD) impedor.From the point of view of more specific, in the exemplary embodiment of Fig. 3, volatile memory is come from
12 signal SRX is actually the outside of the internal driving and volatile memory 12 by memory interface circuit 112 simultaneously
The influence of impedance so that the voltage value of signal SRX is adjusted to the predetermined voltage range of Fig. 3.
In an exemplary embodiment, as signal VREF to be generated, volatile memory 12, which can transmit, meets a specific item
The signal (also referred to as second signal) of part is to memory interface circuit 112.Memory interface circuit 112 can connecing in signal SRX
It receives path and receives second signal.In other words, second signal also can be by the internal driving and volatibility of memory interface circuit 112
The influence of the external impedance of memory 12.Then, memory interface circuit 112 can execute second signal partial pressure operation, to
Generate signal VREF.
In an exemplary embodiment, second signal refers to the signal for transmitting at least one specific binary digit.For example,
In an exemplary embodiment, this specific binary digit is binary digit " 0 ", therefore the voltage value of second signal can be identical (or close)
The lower critical voltage of predetermined voltage range in figure 3.Then, according to the supply voltage VDD detected immediately come to second signal
Partial pressure operation is executed, signal VREF can be given birth to by dynamic real estate.
Fig. 4 is the schematic diagram of the generating circuit from reference voltage shown by an exemplary embodiment according to the present invention.It please refers to
Fig. 1 to Fig. 4, in an exemplary embodiment, memory interface circuit 112 further includes generating circuit from reference voltage 40, is connected to
Connecting interface 1311 and 1312.For example, the input terminal of generating circuit from reference voltage 40 is connected to the RX path of signal SRX, and
And the output end of generating circuit from reference voltage 40 is connected to comparison circuit 23.Thereby, generating circuit from reference voltage 40 can be via even
Connection interface 1311 detects the internal driving of memory interface circuit 112 and detects volatile memory 12 via connecting interface 1312
External impedance then generate signal VREF according to testing result.
In the exemplary embodiment of Fig. 4, generating circuit from reference voltage 40 include voltage detecting circuit 41, bleeder circuit 42 and
Voltage follower circuit 43.When memory interface circuit 112 is connected to volatile memory 12, voltage detecting circuit 41 can connect
To between impedor R1 and impedor R2.Wherein, impedor R1 indicates to provide the inside resistance of memory interface circuit 112
Anti- equivalent resistance, and impedor R2 indicates to provide the equivalent resistance of the external impedance of volatile memory 12.
When memory interface circuit 112 receives second signal, voltage detecting circuit 41 can be in response to impedor R1
External impedance that the internal driving of offer and impedor R2 are provided and detected between impedor R1 and impedor R2
Signal V1 (that is, second signal) simultaneously generates signal V2.In an exemplary embodiment, signal V1 refers to one end of impedor R1
Voltage (also referred to as first voltage), voltage value are positively correlated with the supply voltage VDD's for the other end for being connected to impedor R1
Voltage value.In addition, signal V2 is also referred to as second voltage.For example, the voltage value of signal V2 can be locked in the voltage value of signal V1.
For example, the voltage value of signal V2 can identical (or close) signal V1 voltage value.By taking Fig. 3 as an example, the voltage value of signal V2 can phase
With (or close) in the lower critical voltage of predetermined voltage range.
Bleeder circuit 42 is connected to voltage detecting circuit 41 and to the signal of the output end to voltage detecting circuit 41
V2 executes partial pressure operation.For example, bleeder circuit 42 includes impedor R3 and R4.The first end of impedor R3 is connected to supply
The first end of voltage VDD, impedor R4 are connected to voltage detecting circuit 41 to receive signal V2, and the of impedor R3
Two ends are connected to the second end of impedor R4.In addition, the impedance value of impedor R3 (or close) identical as R4 offers.Partial pressure
Circuit 42 can execute partial pressure according to supply voltage VDD and signal V2 and operate and generate signal V3 (also referred to as tertiary voltage).Signal
The voltage value meeting (about) of V3 is equal to the half of the voltage value and the summation of the voltage value of signal V2 of supply voltage VDD.
Voltage follower circuit 43 is connected to bleeder circuit 42 and the signal V3 productions in response to the output end of bleeder circuit 42
Raw signal VREF.For example, the voltage value of signal VREF can be locked in the voltage value of signal V3.For example, the voltage of signal VREF
Value meeting identical (or close) is in the voltage value of signal V3.Then, signal VREF may be provided to the comparison circuit 23 of Fig. 2.In addition,
In an exemplary embodiment, the voltage value or generation parameter of signal VREF can be recorded in the storages such as a register (register)
Element.Thereby, after stopping receiving second signal, voltage follower circuit 43 (or, memory interface circuit 112) is still sustainable
Signal VREF is generated according to the voltage value or generation parameter that are recorded.In addition, in an exemplary embodiment, stopping receiving the
After binary signal, at least one of voltage detecting circuit 41 and bleeder circuit 42 can be disabled (disable) with power saving.
In an exemplary embodiment, an internal ginseng is also considered as to generate the operation of signal VREF according to second signal
It examines signal and generates operation.For example, this internal reference signal generate operation can actual use signal VREF come generate signal SIN it
Preceding execution and the voltage value for being used for dynamically determining signal VREF.That is, in an exemplary embodiment, the first signal is being received
Before, memory interface circuit 112 can receive second signal and determine to be subsequently used for the first signal of parsing according to second signal
Internal reference signal voltage value.
In an exemplary embodiment, it is default that Memory Controller 111 can send at least one via memory interface circuit 112
Instruction is read to volatile memory 12.This default reads instructs to indicate to read a present count of volatile memory 12
According to.This preset data includes at least one specific binary digit (for example, binary digit " 0 ").It is instructed according to this default reads, easily
The property lost memory 12 will produce above-mentioned second signal.
In an exemplary embodiment, instructed according to this default reads, this present count can be automatically stored in volatile memory 12
According to and connect execute read this preset data operation to generate above-mentioned second signal.Thereby, Memory Controller 111 will not be
Before sending default reading instruction, additional write instruction is sent to indicate preset data being stored in volatile memory 12.
In addition, in an exemplary embodiment, instructed according to this default reads, volatile memory 12 is not required to practical execution data access behaviour
Work can generate above-mentioned second signal.Alternatively, in another exemplary embodiment, this preset data can also be to be controlled by memory
Device 111 sends additional write instruction to indicate preset data being stored in volatile storage before sending default reading instruction
In device 12, the present invention does not limit.
In an exemplary embodiment, impedor 21 can select one with 22 and be activated.For example, in sometime range,
If signal ENA exists and impedor 21 is activated, signal ENB will be not present.At this point, the impedor 21 started can carry
For internal driving to the RX path of signal SRX, and the impedor 22 not being activated does not provide internal driving.Alternatively, at certain
In one time range, if signal ENB exists and impedor 22 is activated, signal ENA will be not present.At this point, start
Impedor 22 can provide internal driving to the RX path of signal SRX, and the impedor 21 not being activated does not provide inside
Impedance.By only starting one of impedor 21 and 22, memory interface circuit 112 when receiving signal SRX can be reduced
Power consumption.
In an exemplary embodiment, the enable time of signal ENA or ENB are also dynamically adjusted.For example, signal ENA
Or the enable time of ENB can be positively correlated with the sum via the signal SRX multiple binary digits continuously transmitted.It is noted that
The above-mentioned enable time refers to the existence time of signal.For example, the enable time of signal ENA can be positively correlated at impedor 21
In the time span of starting state, and the enable time of signal ENB can then be positively correlated with impedor 22 and be in starting state
Time span.
In an exemplary embodiment, it is assumed that the transmission specification of signal SRX is the binary digit of continuously n binary digit of transmission
Data.For example, n can be 4,8,16 or 32 or greater or lesser.If n is bigger, the enable time of signal ENA or ENB can get over
It is long.Thereby, it can be ensured that before completely receiving binary digit data from volatile memory 12, impedor 21 and 22
One of (at least) starting state can be continuously in.Completely receive the binary digit data from volatile memory 12 it
Afterwards, signal ENA or ENB can be stopped offer.Thereby, memory interface circuit 112 when receiving signal SRX can be further decreased
Power consumption.
In an exemplary embodiment, impedor 21 and 22 can select one and be arranged in memory interface circuit 112.By
This, can reduce the power consumption of memory interface circuit 112 when receiving signal SRX, can also be further reduced memory interface electricity
The layout area of receiving terminal circuit in road 112.
Fig. 5 is the schematic diagram of the memory interface circuit shown by another exemplary embodiment according to the present invention.Fig. 6 is root
According to the schematic diagram of the first signal shown by another example of the present invention embodiment.Fig. 5 and Fig. 6 are please referred to, is implemented in this example
In example, be provided with impedor 21, but impedor 22 is not set in memory interface circuit 112.The voltage value meeting of signal SRX
A voltage range (also referred to as first voltage range) is adjusted in response to the internal driving that impedor 21 provides.First
There are one upper critical voltage VIH (also referred to as a first critical voltage) and lower critical voltage VIL (also referred to as for voltage range tool
Two critical voltages).The voltage value of upper critical voltage VIH is higher than the voltage value of lower critical voltage VIL.In other words, in Fig. 5 and Fig. 6
Exemplary embodiment in, the voltage value of signal SRX can be influenced by the internal driving that impedor 21 provides and in first voltage
It rises and falls in range, depending on the binary digit data transmitted.In addition, in an exemplary embodiment of Fig. 5 and Fig. 6, signal SRX
Voltage value without departing from first voltage range.
It is noted that in the exemplary embodiment of Fig. 5 and Fig. 6, first voltage range is different from the predeterminated voltage in Fig. 3
Range, and a median of first voltage range is different from the voltage value of a predeterminated voltage VCEN.For example, first voltage range
Median be likely to be greater than the voltage value of predeterminated voltage VCEN.Wherein, the median of first voltage range is equal to upper critical electricity
The half of the summation of the voltage value of VIH and the voltage value of lower critical voltage VIL is pressed, and the voltage value of predeterminated voltage VCEN is (that is, pre-
If voltage value) then it is equal to the half of the voltage value and the summation of the voltage value with reference to ground voltage GND of supplying voltage VDD.In addition,
The voltage value of upper critical voltage VIH may identical (or close) in the voltage value of supply voltage VDD.Although it is noted that
Fig. 6 is to show that the voltage value of lower critical voltage VIL is higher than the voltage value of predeterminated voltage VCEN, still, real in another example of Fig. 6
It applies in example, the voltage value of lower critical voltage VIL may also be less than the voltage value of predeterminated voltage VCEN, depending on the internal driving configured
Depending on external impedance.
In the exemplary embodiment of Fig. 5 and Fig. 6, signal VREF is also dynamically to be generated by memory interface circuit 112.Example
Such as, according to the exemplary embodiment of Fig. 4, the voltage value of signal V2 (or signal V1) can identical (or close) the lower critical electricity in Fig. 6
Press the voltage value of VIL.After executing partial pressure operation with supply voltage VDD according to signal V2, signal VREF can be generated.For example,
The voltage value of signal VREF can identical (or close) in the median of first voltage range, as shown in Figure 6.About generation signal
The detail of VREF can refer to preceding description, just not repeat herein.
In addition, in another exemplary embodiment of Fig. 5, impedor 21 can also be that can be used to by least one resistance etc.
The electronic component of resistance value or reactance value is provided to implement.Thereby, the 21 sustainable offer internal driving number of writing SRX of impedor
RX path, and signal ENA can be not controlled by.
Fig. 7 is the schematic diagram of the memory interface circuit shown by another exemplary embodiment according to the present invention.Fig. 8 is root
According to the schematic diagram of the first signal shown by another example of the present invention embodiment.Fig. 7 and Fig. 8 are please referred to, is implemented in this example
In example, be provided with impedor 22, but impedor 21 is not set in memory interface circuit 112.The voltage value meeting of signal SRX
Another voltage range (also referred to as second voltage range) is adjusted in response to the internal driving that impedor 22 provides.The
Two voltage ranges also have there are one a upper critical voltage VIH and lower critical voltage VIL.The voltage value of upper critical voltage VIH is high
In the voltage value of lower critical voltage VIL.In other words, in the exemplary embodiment of Fig. 7 and Fig. 8, the voltage value of signal SRX can be obstructed
The influence for the internal driving that anti-element 22 provides and rise and fall within the scope of second voltage, depending on the binary digit data transmitted
It is fixed.In addition, in an exemplary embodiment of Fig. 7 and Fig. 8, the voltage value of signal SRX is without departing from second voltage range.
It is noted that in the exemplary embodiment of Fig. 7 and Fig. 8, second voltage range is different from the predeterminated voltage in Fig. 3
Range, and a median of second voltage range is different from the voltage value of predeterminated voltage VCEN.Wherein, in second voltage range
Between voltage value and lower critical voltage VIL of the value equal to upper critical voltage VIH voltage value summation half.For example, the second electricity
Press the median of range that may be less than the voltage value of predeterminated voltage VCEN.In addition, the voltage value of lower critical voltage VIL may
Identical (or close) refers to the voltage value of ground voltage GND.It is noted that although Fig. 8 is the electricity for showing critical voltage VIH
Pressure value is less than the voltage value of predeterminated voltage VCEN, still, in another exemplary embodiment of Fig. 8, the voltage of upper critical voltage VIH
Value may also be higher than the voltage value of predeterminated voltage VCEN, depending on the internal driving and external impedance that are configured.
In the exemplary embodiment of Fig. 7 and Fig. 8, signal VREF is also dynamically to be generated by memory interface circuit 112.Example
Such as, according to the exemplary embodiment of Fig. 4, the voltage value of signal V2 (or signal V1) can identical (or close) upper critical electricity in Fig. 8
Press the voltage value of VIH.If replacing with the supply voltage VDD that bleeder circuit 42 is connected with reference to ground voltage GND, in basis
After signal V2 executes partial pressure operation with reference ground voltage GND, signal VREF can be generated.For example, the voltage value of signal VREF
Meeting identical (or close) is in the median of second voltage range, as shown in Figure 8.
In addition, in another exemplary embodiment of Fig. 7, impedor 22 can also be that can be used to by least one resistance etc.
The electronic component of resistance value or reactance value is provided to implement.Thereby, the 22 sustainable offer internal driving number of writing SRX of impedor
RX path, and signal ENB can be not controlled by.
Fig. 9 is the schematic diagram of the memory storage apparatus shown by another exemplary embodiment according to the present invention.It please refers to
Fig. 9, memory storage apparatus 90 are, for example, that solid state disk (Solid State Drive, SSD) etc. is non-comprising duplicative simultaneously
The memory storage apparatus of volatile 906 and volatile memory 908.Memory storage apparatus 90 can be with one
Host system is used together, and host system can write data into memory storage apparatus 90 or from memory storage apparatus 90
Middle reading data.Mentioned host system is substantially to coordinate to store the arbitrary system of data with memory storage apparatus 90
System, for example, desktop computer, laptop, digital camera, video camera, communication device, audio player, video player or
Tablet computer etc..
From the point of view of specific, memory storage apparatus 90 include connecting interface unit 902, memorizer control circuit unit 904, can
Manifolding formula non-volatile memory module 906 and volatile memory 908.Connecting interface unit 902 is for storing memory
Device 90 is connected to host system.In this exemplary embodiment, connecting interface unit 902 is to be compatible to Serial Advanced Technology Attachment
(Serial Advanced Technology Attachment, SATA) standard.However, it is necessary to be appreciated that, the present invention is unlimited
In this, connecting interface unit 902 can also be to meet parallel advanced technology annex (Parallel Advanced Technology
Attachment, PATA) standard, high-speed peripheral component connecting interface (Peripheral Component Interconnect
Express, PCI Express) standard, universal serial bus (Universal Serial Bus, USB) standard or other be suitble to
Standard.Connecting interface unit 902 can be encapsulated in memorizer control circuit unit 904 in a chip or connecting interface
Unit 902 can also be to be laid in outside a chip comprising memorizer control circuit unit 904.
Memorizer control circuit unit 904 to according to the instruction of host system in type nonvolatile mould
The write-in of data is carried out in block 906, the runnings such as reads and erase.Reproducible nonvolatile memorizer module 906 is to be connected to
Memorizer control circuit unit 904 and the data being written to host system.Type nonvolatile
Module 906 can be single-order storage unit (Single Level Cell, SLC) NAND type flash memory module (that is, one
The flash memory module of 1 binary digit can be stored in storage unit), multi-level cell memory (Multi Level Cell,
MLC) NAND type flash memory module (that is, the flash memory module of 2 binary digits can be stored in a storage unit),
Complex Order storage unit (Triple Level Cell, TLC) NAND type flash memory module is (that is, can in a storage unit
Store the flash memory module of 3 binary digits), other flash memory modules or other memories with the same characteristics
Module.
In this exemplary embodiment, memorizer control circuit unit 904 also has the exemplary embodiment institute with Fig. 1 to Fig. 8
The 11 same or analogous function of memorizer control circuit unit and/or electric circuit construction referred to, and volatile memory
The 908 same or similar volatile memory 12 mentioned by the exemplary embodiment of Fig. 1.Accordingly, with respect to memorizer control circuit
The explanation of unit 904 and volatile memory 908 please refers to the exemplary embodiment of Fig. 1 to Fig. 8, does not just repeat herein.
It is noted that Fig. 2, Fig. 4, Fig. 5 and electric circuit construction illustrated in fig. 7 are only in partial example embodiment
The schematic diagram of memory interface circuit, rather than to limit the present invention.In the unmentioned application in part, more electronic components
It can be injected towards in memory interface circuit, to provide additional function.In addition, in the unmentioned application in part, storage
The circuit layout and/or element connection relation of device interface circuit can also be appropriately changed, to meet the demand in practice.
Figure 10 is the flow chart of the signal acceptance method shown by an exemplary embodiment according to the present invention.This signal receives
Method is applicable to the memory storage apparatus mentioned by the exemplary embodiment of Fig. 1 or Fig. 9.It will be deposited below with the memory of Fig. 1
Storage device 10 arranges in pairs or groups Figure 10 to illustrate.
Fig. 1 and Figure 10 are please referred to, in step S1001, is received by memory interface circuit 112 and comes from volatile memory
12 the first signal.In step S1002, the inside by memory interface circuit 112 in response to memory interface circuit 112 hinders
The anti-voltage value by the first signal is adjusted to a voltage range.For example, this voltage range can be first voltage model shown in fig. 6
It encloses or second voltage range shown in Fig. 8.In the step s 1003, by memory interface circuit 112 according to the first signal and inside
Voltage relativeness between reference voltage generates input signal.
However, each step has been described in detail as above in Figure 10, just repeat no more herein.It is worth noting that, each in Figure 10
Step can be implemented as multiple procedure codes or circuit, and the present invention does not limit.In addition, more than the method for Figure 10 can arrange in pairs or groups
Exemplary embodiment uses, and can also be used alone, the present invention does not limit.
In conclusion specific receiving terminal circuit is arranged in memory interface circuit and will come from easily for present invention proposition
The voltage value of first signal of the property lost memory is adjusted to a particular voltage range and is come using suitable internal reference voltage
Analyze the first signal.Thereby, the correctness of input signal caused by can maintaining, and power when receiving the first signal can be reduced
Consumption.
Although the present invention is disclosed as above with embodiment, however, it is not to limit the invention, any technical field
Middle technical staff, without departing from the spirit and scope of the present invention, when can make some changes and embellishment, therefore the protection of the present invention
Range is when subject to as defined in claim.
Claims (30)
1. a kind of memorizer control circuit unit, to control volatile memory, which is characterized in that the memory control electricity
Road unit includes：
Memory Controller；And
Memory interface circuit is connected to the Memory Controller,
The wherein described memory interface circuit to receive the first signal from the volatile memory,
The wherein described memory interface circuit is also to the internal driving in response to the memory interface circuit and by described
The voltage value of one signal is adjusted to voltage range,
The median of the wherein described voltage range is not equal to preset voltage value,
The wherein described preset voltage value is the voltage value and reference ground voltage of the supply voltage of the memory interface circuit
The half of the summation of voltage value,
The wherein described memory interface circuit is also to opposite according to the voltage between first signal and internal reference voltage
Relationship generates input signal.
2. memorizer control circuit unit according to claim 1, which is characterized in that the memory interface circuit includes
Impedor, to provide the internal driving,
The first end of the wherein described impedor is connected to the RX path of first signal, wherein the of the impedor
Two ends be connected to the supply voltage or it is described refer to ground voltage.
3. memorizer control circuit unit according to claim 2, which is characterized in that use at the third end of the impedor
To receive enable signal, wherein the impedor provides the internal driving in response to the enable signal.
4. memorizer control circuit unit according to claim 3, which is characterized in that the enable time of the enable signal
It is positively correlated with the sum of the multiple binary digits continuously transmitted via first signal.
5. memorizer control circuit unit according to claim 1, which is characterized in that receive first signal it
Before, the memory interface circuit also to receive the second signal from the volatile memory,
The wherein described memory interface circuit also operates to execute partial pressure to the second signal to generate the internal reference
Voltage.
6. memorizer control circuit unit according to claim 5, which is characterized in that the memory interface circuit is also used
With send it is default read instruction sequence to indicate to read the preset data of the volatile memory,
The wherein described volatile memory is to according to the default reading instruction sequence generation second signal.
7. memorizer control circuit unit according to claim 1, which is characterized in that the memory interface circuit includes
Comparison circuit,
The wherein described comparison circuit to the internal reference voltage and first signal the voltage value to generate
The input signal.
8. memorizer control circuit unit according to claim 1, which is characterized in that the volatile memory is carrying
For external impedance,
The voltage value of wherein described first signal is additionally in response to the external impedance and is adjusted to the voltage range.
9. memorizer control circuit unit according to claim 1, which is characterized in that the volatile memory includes the
Four generation double data rate Synchronous Dynamic Random Access Memories.
10. memorizer control circuit unit according to claim 1, which is characterized in that the memory interface circuit packet
It includes：
First connecting interface, to be connected to the Memory Controller；
Second connecting interface, to be connected to the volatile memory；And
Reference voltage generator is connected to first connecting interface and second connecting interface,
The wherein described reference voltage generator via first connecting interface detecting the internal driving, via described the
Two connecting interfaces detect the external impedance of the volatile memory and generate the internal reference electricity according to the testing result
Pressure.
11. memorizer control circuit unit according to claim 10, which is characterized in that the reference voltage generator packet
It includes：
Voltage detecting circuit, to detect the memory interface circuit in response to the internal driving and the external impedance
In impedor first voltage,
The voltage value of the wherein described first voltage is positively correlated with the voltage value of the supply voltage.
12. memorizer control circuit unit according to claim 11, which is characterized in that the reference voltage generator is also
Including：
Bleeder circuit is connected to the voltage detecting circuit and the second electricity to the output end to the voltage detecting circuit
Pressure executes partial pressure operation；And
Voltage follower circuit is connected to the bleeder circuit and to the third of the output end in response to bleeder circuit electricity
It presses and generates the internal reference voltage.
13. a kind of memory storage apparatus, including：
Connecting interface unit, to be connected to host system；
Reproducible nonvolatile memorizer module；
Volatile memory；And
Memorizer control circuit unit is connected to the connecting interface unit, the reproducible nonvolatile memorizer module
And the volatile memory,
The wherein described memorizer control circuit unit to receive the first signal from the volatile memory,
The wherein described memorizer control circuit unit also to the internal driving in response to the memorizer control circuit unit and
The voltage value of first signal is adjusted to voltage range,
The median of the wherein described voltage range is not equal to preset voltage value,
The wherein described preset voltage value is the voltage value and reference ground voltage of the supply voltage of the memory interface circuit
The half of the summation of voltage value,
The wherein described memorizer control circuit unit is also to according to the voltage between first signal and internal reference voltage
Relativeness generates input signal.
14. memory storage apparatus according to claim 13, which is characterized in that the memorizer control circuit unit packet
Impedor is included, to provide the internal driving,
The first end of the wherein described impedor is connected to the RX path of first signal, wherein the of the impedor
Two ends be connected to the supply voltage or it is described refer to ground voltage.
15. memory storage apparatus according to claim 14, which is characterized in that the third end of the impedor to
Enable signal is received, wherein the impedor provides the internal driving in response to the enable signal.
16. memory storage apparatus according to claim 15, which is characterized in that the enable time of the enable signal is just
It is relevant to the sum of the multiple binary digits continuously transmitted via first signal.
17. memory storage apparatus according to claim 13, which is characterized in that before receiving first signal,
The memorizer control circuit unit also to receive the second signal from the volatile memory,
The wherein described memorizer control circuit unit also operates to execute partial pressure to the second signal to generate the inside
Reference voltage.
18. memory storage apparatus according to claim 17, which is characterized in that the memorizer control circuit unit is also
To send it is default read instruction sequence to indicate to read the preset data of the volatile memory,
The wherein described volatile memory is to according to the default reading instruction sequence generation second signal.
19. memory storage apparatus according to claim 13, which is characterized in that the memorizer control circuit unit packet
Comparison circuit is included,
The wherein described comparison circuit to the internal reference voltage and first signal the voltage value to generate
The input signal.
20. memory storage apparatus according to claim 13, which is characterized in that the volatile memory is providing
External impedance,
The voltage value of wherein described first signal is additionally in response to the external impedance and is adjusted to the voltage range.
21. memory storage apparatus according to claim 13, which is characterized in that the volatile memory includes the 4th
For double data rate Synchronous Dynamic Random Access Memory.
22. a kind of signal acceptance method, for including the memory storage apparatus of volatile memory, which is characterized in that described
Signal acceptance method includes：
The first signal from the volatile memory is received by memory interface circuit；
The voltage value of first signal is adjusted to voltage range in response to the internal driving of the memory interface circuit,
Described in voltage range median be not equal to preset voltage value, wherein the preset voltage value be the memory interface circuit
Supply voltage voltage value with reference to ground voltage voltage value summation half；And
Input signal is generated according to the voltage relativeness between first signal and internal reference voltage.
23. signal acceptance method according to claim 22, further includes：
The internal driving is provided by the impedor of the memory interface circuit,
The first end of the wherein described impedor is connected to the RX path of first signal, wherein the of the impedor
Two ends be connected to the supply voltage or it is described refer to ground voltage.
24. signal acceptance method according to claim 23, further includes：
Enable signal is received by the third end of the impedor；And
By the impedor internal driving is provided in response to the enable signal.
25. signal acceptance method according to claim 24, further includes：
Control the enable time of the enable signal so that the enable time is positively correlated with continuously to be passed via first signal
The sum of defeated multiple binary digits.
26. signal acceptance method according to claim 22, further includes：
Before receiving first signal, second from the volatile memory is received by the memory interface circuit
Signal；And
Partial pressure operation is executed to generate the internal reference voltage to the second signal.
27. signal acceptance method according to claim 26, further includes：
It sends and default reads instruction sequence to indicate to read the preset data of the volatile memory；And
The second signal is generated according to the default reading instruction sequence by the volatile memory.
28. signal acceptance method according to claim 22, which is characterized in that according to first signal and the inside
The voltage relativeness between reference voltage generates the step of input signal and includes：
Compare the voltage value of the internal reference voltage and first signal；And
The input signal is generated according to comparison result.
29. signal acceptance method according to claim 22, further includes：
External impedance is provided by the volatile memory；And
The voltage value of first signal is adjusted to the voltage range in response to the external impedance.
30. signal acceptance method according to claim 22, which is characterized in that the volatile memory includes forth generation
Double data rate Synchronous Dynamic Random Access Memory.
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| Publication number | Priority date | Publication date | Assignee | Title |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100202227A1 (en) * | 2007-07-19 | 2010-08-12 | Rambus Inc. | Reference voltage and impedance calibration in a multi-mode interface |
| CN103129151A (en) * | 2011-11-30 | 2013-06-05 | 珠海天威技术开发有限公司 | Storage chip, data communication method thereof, consumable container and imaging equipment thereof |
| US20140185374A1 (en) * | 2012-12-31 | 2014-07-03 | Sandisk Technologies Inc. | Nonvolatile memory and method with improved i/o interface |
| US20150205751A1 (en) * | 2012-07-20 | 2015-07-23 | Rambus Inc. | Reducing Unwanted Reflections in Source-Terminated Channels |
| CN107293320A (en) * | 2016-03-31 | 2017-10-24 | 三星电子株式会社 | Support the receiving interface circuit of a variety of communication standards and the storage system including it |
-
2017
- 2017-03-17 CN CN201710161613.7A patent/CN108628774B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100202227A1 (en) * | 2007-07-19 | 2010-08-12 | Rambus Inc. | Reference voltage and impedance calibration in a multi-mode interface |
| CN103129151A (en) * | 2011-11-30 | 2013-06-05 | 珠海天威技术开发有限公司 | Storage chip, data communication method thereof, consumable container and imaging equipment thereof |
| US20150205751A1 (en) * | 2012-07-20 | 2015-07-23 | Rambus Inc. | Reducing Unwanted Reflections in Source-Terminated Channels |
| US20140185374A1 (en) * | 2012-12-31 | 2014-07-03 | Sandisk Technologies Inc. | Nonvolatile memory and method with improved i/o interface |
| CN107293320A (en) * | 2016-03-31 | 2017-10-24 | 三星电子株式会社 | Support the receiving interface circuit of a variety of communication standards and the storage system including it |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112309444A (en) * | 2019-07-30 | 2021-02-02 | 群联电子股份有限公司 | Memory interface circuit, memory storage device and setting state detection method |
| CN112309444B (en) * | 2019-07-30 | 2023-10-13 | 群联电子股份有限公司 | Memory interface circuit, memory storage device and setting state detection method |
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