CN108614793A - A kind of device and equipment of change data - Google Patents
A kind of device and equipment of change data Download PDFInfo
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- CN108614793A CN108614793A CN201611142308.5A CN201611142308A CN108614793A CN 108614793 A CN108614793 A CN 108614793A CN 201611142308 A CN201611142308 A CN 201611142308A CN 108614793 A CN108614793 A CN 108614793A
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- 238000006243 chemical reaction Methods 0.000 claims abstract description 20
- 238000004891 communication Methods 0.000 claims description 6
- 238000013501 data transformation Methods 0.000 claims description 4
- 238000000605 extraction Methods 0.000 claims description 2
- 238000013500 data storage Methods 0.000 claims 1
- 230000006870 function Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000008707 rearrangement Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4009—Coupling between buses with data restructuring
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Abstract
A kind of device and equipment of change data, including：First quantity input port, the data packet for inputting the first kind；At least one output port, the data packet for exporting Second Type；And conversion module, the data for the data packet of the first kind to be converted to the Second Type.
Description
Technical field
The present invention relates to wireless communication technology field more particularly to data transfer devices.
Background technology
In wireless communication field, a recent hot research direction is gradually replaced using the base station of C-RAN structures
The base station of original relatively early stage.The base station of C-RAN structures may be implemented distributed architecture, therefore C-RAN structure
Base station can carry out the base station of multiple relatively early stages centralized management to realize that large capacity covers, to which operator be greatly saved
Cost, therefore be just widely used in Communications Market.
Due to the feature of the centralization of C-RAN, it is more to determine that it must be handled using the data link channel of high speed
Base band data, could effectively play its performance in this way, typically, the existing base stations C-RAN generally use general public nothing
(its corresponding bandwidth is about for rate 7 (rate-7) standard for line interface (common public radio interface abbreviation CPRI)
For 9830.4Mbit/s) or using 10G Ethernets (Ethernet) interface handle a large amount of base band data.On the other hand,
Interface rate is relatively low used in a large amount of existing base stations compared with early stage now netted, for example, existing net equipment master is to be used
It is CPRI-rate-2 interfaces (its corresponding bandwidth is about 1228.8Mbit/s), it is clear that need the low speed data of existing net base station
It could be used for the high-speed interface of C-RAN after being converged.
About this problem, existing conventional solution is through-rate converter (speed first
Translator) by CPRI-rate-2 data conversions at CPRI-rate-7 data；Then by supporting rate-7 rates
CPRI interchangers are by the transformed data transmission from multiple base stations to C-RAN.Obviously, this mode is required to each now net
Base station configures individual speed translator, this certainly will increase the cost of operator；It also requires to configure additionally simultaneously
CPRI interchangers also increase the complexity of network operation.
Therefore we need a kind of new data conversion equipment, can replace the speed of above-mentioned separate configurations
Translator and CPRI interchangers realize conversion and convergence of the low speed data to high-speed data at lower cost, and can
With lower complexity and existing hardware compatibility, lower the change to existing net as possible.
Invention content
To solve the above problem in the prior art, the present invention proposes a kind of new data conversion equipment, by with one
Field programmable gate array (Field-Programmable Gate Array abbreviation FPGA) device come realize data conversion with converge
Poly- function is realized to which original speed translator and CPRI interchangers to be integrated into an equipment.
Specifically, according to the first aspect of the invention, it is proposed that a kind of Field Programmable Gate Array Devices, including：First
Quantity input port, the data packet for inputting the first kind；At least one output port, the number for exporting Second Type
According to packet；And conversion module, the data for the data packet of the first kind to be converted to the Second Type.
Preferably, wherein the conversion module includes：Data extracting unit, the data for extracting the first kind
Data in packet；Storage unit, the data for extracting the data extracting unit according to the first pre-defined rule are stored in
In reservoir；Decision unit, for being inputted corresponding to first quantity according in the second pre-defined rule selection institute number memory
The data of an input port in port；Converting unit, being used for will be selected by the decision unit according to third pre-defined rule
Data conversion at Second Type data.
Preferably, wherein first pre-defined rule includes：The memory is divided at least one by the storage unit
A memory block, wherein using the maximum data length handled by the converting unit as the length of the memory block；The storage
The length of the data of the extraction is compared by unit with the length of the memory block：If the length of the data be less than or
Equal to the length of the memory block, the data are stored in a memory block by the storage unit, and by the number
According to length be written in the address 0 of the memory block；Otherwise the data are stored in several continuously by the storage unit
In the memory block, and in the address 0 of other memory blocks by 0 write-in in addition to the last one described memory block, by last
In the address 0 of a memory data length write-in the last one memory block in the block.
More preferably, wherein the storage unit indicates originally after completing the storage operation to the instruction decision unit
Secondary storage operation is completed.
More preferably, wherein second pre-defined rule includes：The decision unit selects the input port in turn
The memory block corresponding to selected data is indicated to the converting unit by data.
Preferably, wherein second pre-defined rule includes：The decision unit selects indicated by the storage unit
Completed storage operates stored data, and it is single that the memory block corresponding to selected data is indicated to the conversion
Member.
More preferably, wherein the third pre-defined rule includes：The converting unit reads the decision unit instruction
The data length in the address 0 of the memory block：If the data length read in the address 0 of the memory block is
0, the converting unit reads the total data stored in the memory block, and continues to read continuous next memory block
Address 0 in the data length；Otherwise the converting unit is read according to the data length read in described address 0
The data of corresponding length and the total data that this data transformation operations is read is converted into the second class in the memory block
The data packet of type；And described this data transformation operations of decision unit of instruction are completed.
Preferably, wherein the data of the first kind are the data of 2 type of common public radio interface rate.
More preferably, wherein the data of the Second Type are the data of 7 type of common public radio interface rate.
More preferably, wherein the data of the Second Type are the data of ethernet type.
According to the second aspect of the invention, it is proposed that a kind of equipment for wireless communication system, including appeal first party
Field Programmable Gate Array Devices described in any one of face.
In the present invention, by realizing data conversion and convergence with FPGA device, a kind of CPRI- of low cost is realized
The conversion plan of rate-2 to CPRI-rate-2/10GEtherent has simultaneously so as to the cost in effectively save operation
Can be compatible with existing net equipment realization to the greatest extent, therefore reached the purpose of the present invention.
Description of the drawings
The following detailed description to non-limiting embodiment, other spies of the invention are read by referring to accompanying drawing
Sign, purpose and advantage will will become more apparent.
Fig. 1 shows a kind of FPGA device schematic diagram according to the present invention；
Fig. 2 shows a kind of FPGA device internal element schematic diagrames according to the present invention.
Wherein, same or analogous reference numeral indicates same or analogous steps characteristic or device/module.
Specific implementation mode
It, will be with reference to the appended attached drawing for constituting a present invention part in the specific descriptions of following preferred embodiment.Institute
Attached attached drawing, which has been illustrated by way of example, can realize specific embodiment.Exemplary embodiment is not intended to
Limit all embodiments according to the present invention.It is appreciated that without departing from the scope of the present invention, other can be utilized
Embodiment can also carry out structural or logicality modification.Therefore, it is below specific descriptions and it is unrestricted, and this
The range of invention is defined by the claims appended hereto.
First, with reference to the accompanying drawings shown in 1, the present invention proposes a kind of FPGA device, and the input terminal of the device has the first number
Amount input port, has n input port to correspond to the low speed number of the first kind from n LTE base station equipment as shown in the figure
According to input；Such as, it is illustrated that CPRI-rate-2 data.There is at least one output port in output end, there is 1 as shown in the figure
High-speed data output of the output port corresponding to the Second Type of C-RAN；Such as, it is illustrated that CPRI-rate-7 or 10G
Ethernet data.Between input port and output port is conversion module, and the conversion module is for realizing above-mentioned
Conversion of the low speed data of one type to the high-speed data of Second Type.As can be seen that the FPGA device is functionally complete simultaneously
It is more by C-RAN processing so as to meet at the function of both existing speed translator and CPRI interchangers
The requirement of a base station data reduces the hardware cost of the realization of data rate transition, to realize the target of the present invention.
Further, according to one embodiment of present invention, it is proposed that a kind of internal element of above-mentioned conversion module designs,
As shown in Fig. 2.Corresponding to n input port, (data packet that input port 1 is inputted to input port n), is carried by data first
Unit is taken to extract valid data therein according to protocol type, i.e., the data extracting unit is by parsing CPRI-rate-2 formats
Data packet, extract valid data therein for subsequent step use.These data extracted by storage unit according to
First pre-defined rule stores in memory.Then it is chosen from memory according to the second pre-defined rule by decision unit and is deposited
The data of some port of storage.The second class is finally converted into according to third pre-defined rule according to protocol type by converting unit
The data of type export.It is exactly a kind of specific implementation of the FPGA device above.
Preferably, the first rule executed in storage unit can be：
Storage space is divided into multiple memory blocks first, the principle for drawing block is according to the maximum handled by converting unit
The length that data length is divided as memory block, such as storage space can be divided into 4 memory blocks.Wherein, in each
The address 0 of counterfoil is for storing data length, and remaining space is for storing above-mentioned valid data.
Value principle for address 0 is that the length for the valid data that will be stored is compared with the length of memory block,
If data length is less than or equal to the length of memory block, illustrate that a memory block can store whole valid data, then
Directly by the length writing address 0 of the valid data, data are then stored in remaining space；
Else if data length is more than the length of memory block, illustrate to need multiple memory blocks that could store whole significant figures
According to then the valid data are stored in continuous multiple memory blocks until the data length in the last one memory block is less than or equal to
Until the length of memory block.At this moment, for other memory blocks other than the last one memory block, the whole values in address 0
It is 0, indicates also there is remaining data in subsequent memory block, and the address 0 of the last one memory block is then written in the last one
Data length in counterfoil, to show that this is continuous the last one memory block.
Further, storage unit can also include state control function, be come from for example, being stored with memory block in completion
After the data of some port, instruction can be sent out to decision unit, show the data that some port has been stored in memory block,
Require signals notice decision unit is sent out as shown in Fig. 2；It can also be sent out in the case of available free memory block
Ready signals, instruction can start to store the operation of data.
Equally preferably, the second pre-defined rule executed on decision unit can be：
Decision unit selects input port by the way of poll.I.e. decision unit selects above-mentioned n input port in turn,
The memory block corresponding to data to the port chosen sends out hit signals, and notifies the address of the converting unit memory block.Judgement
Unit will select converting unit when converting unit carries out change data operation by trig signals, until converting unit is completed
Finish signals, which are sent out, after change data operation just discharges converting unit.
Likewise, above-mentioned decision unit using the second pre-defined rule can also be using competition by the way of carry out port choosing
It selects, i.e., after decision unit receives the Require signals that storage unit is sent every time, selects the port immediately, accomplish data with entering
With going out.Follow-up step is consistent with polling mode, is not repeated.
According to another embodiment of the invention, the third pre-defined rule executed in converting unit can be：
Converting unit finds corresponding memory block, is read from the address of the memory block 0 first according to the instruction of decision unit
The length of valid data is taken, if the length of the valid data is not 0, illustrates all valid data all in this memory block,
Converting unit directly reads corresponding bit according to the length from this memory block, as needs the valid data converted, then
Bit rearrangement is carried out according to the type of target protocol and obtains the data packet of target type, so that it may defeated to be carried out by output port
Go out；
If the length of the valid data read is 0, illustrates that the length of the valid data is more than current memory block, then convert
Unit directly reads the total data of current memory block, then proceedes to read next continuous memory block, equally read first
The address 0 of next memory block；
Then it repeats above-mentioned to judge that this illustrates the memory block until the length of valid data of some memory block is not 0
There to be the last one memory block of above-mentioned valid data, thus converting unit merge the total data that is read in this operation from
And obtained this operation and needed the valid data converted, then obtained by bit rearrangement target type data packet be subject to it is defeated
Go out.
According to one embodiment of present invention, it is proposed that a kind of equipment for wireless communication system, before which includes
Any FPGA device stated can be used to implement conversion of the low speed data to high-speed data.
The embodiment of the present invention is described above, but the invention is not limited in specific system, equipment and
Specific agreement, those skilled in that art can make various deformations or amendments within the scope of the appended claims.
The those skilled in the art of those the art can be by studying specification, disclosure and attached drawing and appended
Claims, understand and implement other changes to the embodiment of disclosure.In the claims, word " comprising " is not arranged
Except other elements and step, and wording "one" be not excluded for plural number.In the present invention, " first ", " second " only indicate name
Claim, does not represent orbution.In the practical application of invention, the possible perform claim of a part multiple skills cited in requiring
The function of art feature.Any reference numeral in claim should not be construed as the limitation to range.
Claims (11)
1. a kind of Field Programmable Gate Array Devices, including：
First quantity input port, the data packet for inputting the first kind；
At least one output port, the data packet for exporting Second Type；And
Conversion module, the data for the data packet of the first kind to be converted to the Second Type.
2. device according to claim 1, wherein the conversion module includes：
Data extracting unit, the data in data packet for extracting the first kind；
Storage unit, the data storage for extracting the data extracting unit according to the first pre-defined rule is in memory；
Decision unit corresponds to the first quantity input port for being selected according to the second pre-defined rule in institute's number memory
In an input port data；
Converting unit is used for the selected data conversion of the decision unit according to third pre-defined rule into the number of Second Type
According to.
3. device according to claim 2, wherein first pre-defined rule includes：
The memory is divided at least one memory block by the storage unit, wherein handled by the converting unit
Length of the maximum data length as the memory block；
The length of the data of the extraction is compared by the storage unit with the length of the memory block：
If the length of the data is less than or equal to the length of the memory block, the data are stored in by the storage unit
In one memory block, and the length of the data is written in the address O of the memory block；Otherwise
The data are stored in several continuous described memory blocks, and O write-ins are removed the last one by the storage unit
In the address O of other memory blocks other than the memory block, described in the last one described memory data length write-in in the block
In the address O of the last one memory block.
4. device according to claim 3, wherein the storage unit is sentenced after completing the storage operation to described in instruction
Certainly unit indicates that this storage operation is completed.
5. device according to claim 4, wherein second pre-defined rule includes：
The decision unit selects the data of the input port in turn, and the memory block corresponding to selected data is referred to
Show to the converting unit.
6. device according to claim 4, wherein second pre-defined rule includes：
The decision unit selects the completed storage indicated by the storage unit to operate stored data, will be selected
Data corresponding to the memory block be indicated to the converting unit.
7. according to the device described in any one of claim 5 or 6, wherein the third pre-defined rule includes：
The converting unit reads the data length in the address O of the memory block of the decision unit instruction：
If the data length read in the address O of the memory block is O, the converting unit is read in the memory block
The total data of storage, and continue to read the data length in the address O of continuous next memory block；Otherwise
The converting unit reads the number of corresponding length in the memory block according to the data length read in described address O
It is converted into the data packet of Second Type according to and by total data that this data transformation operations is read；And
Indicate that this data transformation operations of the decision unit are completed.
8. device according to claim 2, wherein the data of the first kind are common public radio interface rate 2
The data of type.
9. device according to claim 2, wherein the data of the Second Type are common public radio interface rate 7
The data of type.
10. device according to claim 2, wherein the data of the Second Type are the data of ethernet type.
11. the field programmable gate described in a kind of any one of equipment, including claims 1 to 10 for wireless communication system
Array device.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201611142308.5A CN108614793A (en) | 2016-12-12 | 2016-12-12 | A kind of device and equipment of change data |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201611142308.5A CN108614793A (en) | 2016-12-12 | 2016-12-12 | A kind of device and equipment of change data |
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| CN108614793A true CN108614793A (en) | 2018-10-02 |
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| US20040049611A1 (en) * | 2002-09-07 | 2004-03-11 | Micrologic, Inc. | Flexible serial port configuration and method |
| US20040085954A1 (en) * | 2002-10-31 | 2004-05-06 | Giovanni Iacovino | Out-of-band signalling apparatus and method for an optical cross connect |
| CN1945522A (en) * | 2005-08-11 | 2007-04-11 | 三星电子株式会社 | Synchronizer for multi-rate input data and method thereof |
| CN105429764A (en) * | 2015-11-05 | 2016-03-23 | 山东超越数控电子有限公司 | FPGA chip, and remote transmission system and method |
| CN105550142A (en) * | 2015-12-07 | 2016-05-04 | 中国航空工业集团公司西安航空计算技术研究所 | Data integrity processing method in high and low-speed conversion interface |
-
2016
- 2016-12-12 CN CN201611142308.5A patent/CN108614793A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040049611A1 (en) * | 2002-09-07 | 2004-03-11 | Micrologic, Inc. | Flexible serial port configuration and method |
| US20040085954A1 (en) * | 2002-10-31 | 2004-05-06 | Giovanni Iacovino | Out-of-band signalling apparatus and method for an optical cross connect |
| CN1945522A (en) * | 2005-08-11 | 2007-04-11 | 三星电子株式会社 | Synchronizer for multi-rate input data and method thereof |
| CN105429764A (en) * | 2015-11-05 | 2016-03-23 | 山东超越数控电子有限公司 | FPGA chip, and remote transmission system and method |
| CN105550142A (en) * | 2015-12-07 | 2016-05-04 | 中国航空工业集团公司西安航空计算技术研究所 | Data integrity processing method in high and low-speed conversion interface |
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Effective date of registration: 20220118 Address after: 7 / F, 388 ningqiao Road, Pudong New Area pilot Free Trade Zone, Shanghai, 201206 Applicant after: Shanghai NOKIA Baer Software Co.,Ltd. Address before: 201206, Nanjing Jinqiao Export Processing Zone, Shanghai, Nanjing Road, No. 388, Pudong New Area Applicant before: NOKIA SHANGHAI BELL Co.,Ltd. |
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Application publication date: 20181002 |