CN108604904A - For supporting the TURBO of low code rate to encode - Google Patents
For supporting the TURBO of low code rate to encode Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2903—Methods and arrangements specifically for encoding, e.g. parallel encoding of a plurality of constituent codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2957—Turbo codes and decoding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
- H03M13/618—Shortening and extension of codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/635—Error control coding in combination with rate matching
- H03M13/6356—Error control coding in combination with rate matching by repetition or insertion of dummy data, i.e. rate reduction
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/3994—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using state pinning or decision forcing, i.e. the decoded sequence is forced through a particular trellis state or a particular set of trellis states or a particular decoded symbol
Abstract
Being designed as the turbo encoder operated with a kind of code rate can be operated by changing the size of each input block with lower code rate.In one implementation, size can be increased by the way that scheduled bit sequence (that is, extra order) to be inserted into original data block, to create " Virtual Agent code block " more than input block.Virtual Agent code block can be input to turbo encoder to obtain the encoded output block including components of system as directed and parity portion.Components of system as directed can be changed to remove scheduled bit sequence, and obtained output block is sent by channel (for example, noisy radio channel).
Description
Related application
This application claims the U.S. Provisional Patent Application No.62/302 submitted on March 1st, 2016,038 equity,
Content is incorporated herein by reference, as fully expounding herein.
Background technology
Turbo code is a kind of high-performance forward error correction (FEC) code, for controlling in unreliable or noisy communication channel
On data transmission in mistake.The central idea of FEC code be transmitter by using error correction coding (for example, turbo
Code) in a redundant way message is encoded.Redundancy allows receiver to detect and may have to possible in message
Limited number mistake is corrected.FEC code makes recipient have an opportunity error correction, without the reversed letter for requesting retransmission data
Road.
Amount of redundancy in coded data is referred to as " code rate " or " information rate ", can be defined as useful
The ratio of the coded data of (nonredundancy) data.That is, if code rate is 1/3, for each useful information,
Encoder can collectively generate three data bit, wherein two are redundancies.
One application of turbo codes is in the radio link of cellular communications networks.For example, in third generation affiliate
Plan in (3GPP) standardised networks, turbo codes can be used.In certain of such as narrowband (NB) Internet of Things (IoT) application etc
In a little applications, it may be desirable to use the turbo codes for having used low code rate (for example, 1/3).For example, in 3GPP long term evolutions
(LTE) in-advanced (LTE-A) framework, turbo encoder that the code rate with 1/3 can be used to be operated.However,
In some applications, it may be desirable to use even lower than 1/3 code rate.
Description of the drawings
Embodiment described herein is will readily appreciate that by the detailed description below in conjunction with attached drawing.For ease of description,
Identical reference number can indicate identical structural detail.Implementation is shown in the accompanying drawings by way of example, and not limitation
Example.
Figure 1A and 1B is the block diagram for the sample implementation for showing turbo encoder；
Fig. 2 is the exemplary block diagram for the rate-matched for conceptually illustrating the encoded data stream from turbo encoder；
Fig. 3 is the figure for showing turbo coded sequences；
Fig. 4 is to show that be used to the execute turbo that generates low code rate consistent with aspects herein described is encoded
The figure of system；
Fig. 5 is the exemplary figure for the turbo codings for graphically illustrating input block；
Fig. 6 is to graphically illustrate the exemplary figure being decoded to encoded piece from Fig. 5；
Fig. 7 is the flow chart for showing the instantiation procedure for being encoded to data stream at sending device；
Fig. 8 is the flow chart shown for carrying out decoded instantiation procedure to data stream at receiving device；
Fig. 9 A-9D are to show to implement with the example for obtaining Virtual Agent code block for additional data to be added to input block
The figure of example；And
Figure 10 is the block diagram of the exemplary components of another electronic equipment.
Specific implementation mode
Refer to the attached drawing described in detail below.Same reference numbers in different attached drawings can identify same or analogous member
Part.It should be understood that without departing from the scope of the disclosure, using other embodiment and structure can be carried out
Or change in logic.Therefore, described in detail below to be not be considered in a limiting sense, and the range of embodiment is by appended
Claim and its equivalent limit.
Techniques described herein is related to using being designed to be operated with higher code rate (for example, 1/3)
Turbo encoding packs support low code rate (for example, 1/6 code rate).Techniques described herein is for by having
The low bandwidth application that the channel of noise is communicated is particularly useful.For example, techniques described herein is used for wirelessly
The NB IoT equipment that cellular network is communicated.
Techniques described herein can be encoded by using turbo and improve performance with low code rate.Relative to for
Realize that the prior art of low code rate turbo codes, techniques described herein can be more effective.More effectively coding can be led
The lower radio uplink transmissions time is caused, this thus can lead to less power consumption and to increase IoT/ machine types logical
Believe the battery life of (MTC) equipment.The performance improvement that low rate channel is provided is particularly useful under certain network modes,
Such as 3GPP spreads over pattern.In some implementations, techniques described herein can also in downlink transmission
It is beneficial (for example, to improve spectrum efficiency).
As described herein, the input block to be encoded can be changed to increase the size of data block.It can be by following
It operates to execute the increase to size：Predetermined bit sequence (that is, extra order) is inserted into original data block to create more than defeated
Enter " the Virtual Agent code block " of data block.Virtual Agent code block can be input to turbo encoder to obtain encoded output block.
In turbo codings, output block may include three parts, and it is strange to be referred to as components of system as directed, the first parity portion and second
Even parity check part.Components of system as directed can be changed to remove predetermined bit sequence, and can be in channel (for example, noisy wireless
Radio channel) on the output block that sends.
At receiver, the components of system as directed of received data can be changed again to reinsert predetermined bit sequence.It can
To be decoded the coded data with the predetermined bit sequence reinserted to obtain original data block.
Figure 1A is the block diagram for the sample implementation for showing turbo encoder 100.Turbo encoder 100 can receive with
The corresponding input bit of the data to be encoded (" input bit ").Input bit can be received as the block with predetermined length.Also
It is to say, data flow can be resolved into the block of regular length.Turbo encoder 100 exports there are three can having：System output and
Two even-odd check outputs.
As shown, turbo encoder 100 includes two the 110 (" system volumes of component coder separated by interleaver 130
Product encoder 1 ") and 120 (" systematic convolutional coders 2 ").As shown, in the system output from two component coders only
There are one system outputs can be used (that is, " system position " output for systematic convolutional coders 2 is not shown).Such as Figure 1A institutes
Show, therefore the output of turbo encoder 100 may include three parts：System position, parity check bit 1 and parity check bit 2.
These three parts can be serialized and be sent eventually by channel (for example, noisy radio channel).Turbo is encoded
The code rate of device 100 can be 1/3.
Figure 1B is the block diagram for a specific embodiment for showing turbo encoder 100.As shown in Figure 1B, turbo encoder
100 can be system convolution turbo encoder, such as the 5.1.3.2.1 sections of 3GPP technical specifications (TS) 36.212v.12.5.0
Described in turbo encoder.As shown in Figure 1B, turbo encoder 100 can be tool there are two 8 state component encoders and
The system in parallel concatenated convolutional coding device of one turbo code inner interleaver.Each component coder is independently terminated by tail position.
Dotted line (line 125) in Figure 1B can indicate to may not be grid (trellis) end normally exported from turbo encoder 100
Only information.In turbo encoder 100, as shown in Figure 1B, ckIt can correspond to input bit (as shown in Figure 1A), and can be with
Indicate that length is the input block of k.xkIt can correspond to the system position (as shown in Figure 1A) that length is k.Similarly, zkAnd zk’It can
To correspond respectively to parity check bit 1 and parity check bit 2 (as shown in Figure 1A), each length is k.xk'It can correspond to net
Lattice termination message.Each in encoder 110 and 120 may include multiple delay elements (" D ") and adder ("+").
The output of Turbo encoder 100 can correspond to system position and two groups of parity check bits, and be led by gridding information
The 12 tail positions caused.Code rate matches after being executed to carry-out bit based on each code block, and rear code rate matching
It may include that three information bit streams (that is, system position, parity check bit 1 and parity check bit 2) are interleaved, then collect
Bit stream is simultaneously exported using circular buffer.
Fig. 2 is the exemplary block diagram for the rate-matched for conceptually illustrating encoded data stream.As shown, turbo is encoded
Device 100 can generate three output streams：System position, parity check bit 1 and parity check bit 2.Parity check bit can be by
Interleaver 210 is handled.Interleaver 210 can be operated to execute intertexture and multiplex operation.Intertexture and multiplex operation
It can for example include the sub-block intertexture as described in the 5.1.4.2.1 sections of 36.212 v 12.5.0 of 3GPP TS.System position and warp
The parity check bit of intertexture can be entered collects and selects component 220 in place, operable to buffer and export single warp knit
The output stream of code parallel series.
In one implementation, position is collected and circular buffer may be implemented in selection component 220.Circular buffer can be with
It is realized as described in the 5.1.4.2.2 of 36.212 v 12.5.0 of 3GPP TS sections.With system position, parity check bit
1 and 2 corresponding inlet flow of parity check bit can be received and stored in the preassigned position in circular buffer
(for example, as described in the 5.1.4.2.2 sections of 3GPP TS 36.212 v.12.5.0).When reading is in channel
On be transmitted output sequence when, can sequentially read circular buffer, and may by from the end of buffer around
It is carried out " re-reading " to the beginning of circular buffer.
In order to use turbo encoder 100 to realize, the code rate less than 1/3, the prior art can be read by a manner of
Circular buffer is taken, repeated encoding position in the output bit stream to transmit on transport channels.For example, in order to realize 1/6 volume
Bit rate can read circular buffer twice.
Fig. 3 is the figure for showing the turbo coded sequences using turbo encoder 100, wherein by collecting and selecting from position
Component 220, which reads iteration twice, can obtain 1/6 code rate (for example, twice by circular buffer iteration).As schemed
Show, frame 305 can indicate input block.Frame 310 can be equal to 1/3 encoded output stream with presentation code rate.That is,
Frame 310 can indicate the output of turbo encoder 100.Bit stream 320 can be indicated based on by position collection and selection component 220
Turbo encoded output streams after the repetition carried out to surrounding for circular buffer realized.In this case, coding speed
Rate can be reduced to 1/6.However, as shown in figure 3, the coding based on repetition for reducing code rate may be relative inefficiencies
's.Specifically, it is desired that realizing the encoding scheme of identical code rate using less bits are needed.
Fig. 4 is the figure for showing the system 400 consistent with aspects herein described, system 400 for execute generate compared with
The turbo of low code rate (for example, 1/6) is encoded.The virtual input code for actually entering code block can be more than based on generating
Block obtains relatively low code rate.Coding techniques discussed in this article can be than using about repeated encoding described in Fig. 3 more
Effectively obtain relatively low code rate.
As shown in figure 4, system 400 may include coded portion 410 and decoded portion 450.Code and decode 410 He of part
450 can correspond respectively in the base station (for example, evolved node B) in user equipment (UE) and/or cellular network realize
Software and/or hardware.UE and base station can be communicated by noisy channel (for example, via radio link).
In other realization methods, coded portion 410 and decoded portion 450 can be realized in other environments, such as via there is noise
Any two equipment that is communicated of channel (including radio and non-radio link) between.In addition, though coded portion
410 can be described as being realized by UE, and decoded portion 450 can be primarily described as being realized by base station in this paper, but
In some realization methods, decoded portion 450 may be implemented in UE and coded portion 410 may be implemented in base station.In addition, in some realities
In existing mode, two communication equipments (for example, both UE and base station) can respectively realize coded portion 410 and decoded portion 450
The two.
As shown in figure 4, coded portion 410 may include block extension element 415, encoder 420, encoding block compression assembly
425 and position collect and selection component 430.Decoded portion 450 may include block extension element 455 and decoder 460.Channel
470 (for example, wireless (for example, radio) links) are also shown in FIG. 4.As previously mentioned, such as FEC code of turbo codes etc
It may be particularly useful in the environment for damaging (for example, noisy) communication media.
Block extension element 415 can be operated to extend input block (that is, input traffic will be sent out by channel 470
The part sent).The extended version (may be referred to herein as " virtual input code block ") of input block can be more than original
Input block.For example, virtually input block size can be selected as：
B=a* (1/R-1)/2 (equation 1)；
Wherein R is desired code rate, and a is the size (length) of original input data block, and b is virtual input code block
Size.Therefore, to be added to input block to obtain the length of the additional digit of virtual input code block as b-a.One
It, can deterministically determination will be added in such a way that both coded portion 410 and decoded portion 450 are both known about in a realization method
To input block extra order and additional phase for original input data block interval.For example, extra order can be added
It is added to the beginning of input block, is added to the ending of input block, or interweave in input block.Below with reference to figure
9A-9D descriptions by extra order for being combined to input block to obtain the additional possible embodiment of virtual input code block.
Referring back to Fig. 4, encoder 420 may include turbo encoder, such as above about 100 institute of turbo encoder
The turbo encoder realized like that is described.Therefore the output of encoder 420 may include system position and two groups of parity check bits.
Encoding block compression assembly 425 can receive the output of encoder 420 (for example, system position, parity check bit 1 and parity check bit
2), and system position can be operated to remove extra order from system position.Alternatively, encoding block compression assembly 425 can
With with input block replacement system position.In either case, the system position obtained can will be obtained with when being extended without using block
The system position obtained is identical.However, the length of parity check bit 1 and parity check bit 2 is longer when can be than not using block extension.
Position is collected and selection component 430 can be collected with position and component 220 is selected analogously to be operated.However,
In realization method shown in Fig. 4, circular buffer need not be carried out to repeat reading, this repeats reading can be in conventional systems
Using to obtain lower code rate.
Decoded portion 450 may include block extension element 455 and decoder 460.Block extension element 455 can be operated to know
The system data of other received input block simultaneously reinserts extra order.Therefore, block extension element 455 can be with block extension element
415 are analogously operated.Decoder 460 can execute the operation of turbo coding and decodings, and supplement is executed by encoder 420
Coding.Therefore the output of decoder 460 will be o piginal input block during Successful Operation.
Fig. 5 is the exemplary figure for graphically illustrating coded portion 410 and carrying out turbo codings to input block.Length is a
The input block 510 of position (for example, four) can be input to block extension element 415.Block extension element 415 operation it
Afterwards, the virtual input code block 520 that length is b can be obtained.Virtual input code block 520 may include coming from input code
The position of block 510, and can also include extra order.In this example, extra order is added with predetermined sequence, wherein in initial data
Two are added after each position in block 510.Extra order can be for example complete " zero " position, complete " one " position or known zero-bit
With one combination (for example, alternate zero-bit and one).
Virtual input code block 520 can be by the processing of encoder 420 to obtain encoded piece 530.As previously mentioned, by compiling
The processing that code device 420 carries out may include carrying out turbo codings using systematic convolutional coders.As shown, encoded piece
530 may include system position and two groups of parity check bits.It system position can be constant from virtual input code block 520.It is encoded
Block 530 can be encoded the processing of block compression assembly 425 to remove extra order from system position, to obtain original input data
Block.It may be shown as encoded piece 540 in the final coded sequence after being collected by position and component 430 is selected to handle.It is right
The case where code rate is 1/3 turbo encoder is realized in encoder 420, and encoded piece 540 of final code rate can
With lower, for example, 1/6.Can without using the circular reading of circular buffer is executed realized in the case that output repeats compared with
Low code rate.
Fig. 6 graphically illustrates the exemplary figure being decoded to encoded piece from Fig. 5.It is received by channel
After encoded piece, decoded portion 450 can execute decoding.As shown, can be received at decoded portion 450
Block 610.Block extension element 455 can identify the system position (at 620) of received bit sequence 610, and use and block
Extra order is added go back to system position by the identical pattern of pattern used in extension element 415, to obtain block 630.Then, block 630
It can be decoded by decoder 460 to obtain essence (output) data block 640.If coding/decoding operates successfully, data block
640 will match input block 510.
Fig. 7 is the flow chart shown for the instantiation procedure 700 of coding and transmission data stream at sending device.Process
700 can be executed by such as UE or base station.
First, process 700 may include segmentation input traffic (for example, the data to be sent by noisy channel) with
Obtain input block (frame 710).Each input block can have regular length.
Process 700 can also include scheduled additional data sequence being inserted into block to obtain Virtual Agent code block (frame
720).As previously mentioned, scheduled additional data sequence can be added to the beginning of input block, it is added to input block
Ending, or interweave in input block.Additional data relative to the size of input block amount (that is, predetermined sequence
Length) can determine the code rate of coded data.In one implementation, the length, code rate of input block,
Relationship between additional amount of data can be defined by equation (1).
Process 700 can also include being encoded (frame 730) to Virtual Agent code block using turbo encoder.For example, virtual
Code block can be input to turbo encoder 100, and turbo encoder 100 can be strange with output system position and first and second
Even parity bit.The output of turbo encoder 100 can be referred to as encoded code block.
Process 700 can also include that scheduled additional data sequence is removed from the system position of the output of turbo encoder
(frame 740)." removal " used herein can also refer to o piginal input block come replacement system position or using not including predetermined
Additional data sequence system position.However, the first and second parity check bits can be based on Virtual Agent code block.It eliminates predetermined
Additional data sequence system position and the first and second parity check bits with will by channel send output data it is opposite
It answers.
Process 700 can also include sending encoded data (frame 750).Encoded data can be in noisy letter
It is sent on road (for example, radio link).
Fig. 8 is the flow chart shown for the instantiation procedure 800 of decoding data stream at receiving device.Process 800 can be with
It is executed by such as UE or base station.
Process 800 may include reception/processing encoded piece (frame 810).Process 800 can also include by predetermined sequence
It is added to encoded piece (frame 820).In one implementation, it may include knowing predetermined sequence to be added to encoded piece
Predetermined sequence is simultaneously added to system position by other system position, and mode is identical as the mode of predetermined sequence is added at sending device.
Process 800 can also include decoded data block (frame 830).Decoding process can be based on to turbo coding and decoding mistakes
The use of journey (for example, decoding process of turbo encoder 100).
Fig. 9 A-9D are to show to implement with the example for obtaining Virtual Agent code block for additional data to be added to input block
The figure of example.In Fig. 9 A-9D, the value of additional data can be set to any specific value, value pattern or pseudorandom certainty
Sequence.For example, can be added according to Quan Yiwei, full zero-bit, preassigned pattern, predetermined circulation pattern, and/or based on pseudo-random sequence
Add additional data.
As shown in Figure 9 A, can by additional phase for input block position by spaced at equal intervals in a manner of by extra order
It is added to input block to obtain Virtual Agent code block 910.In the example shown, add after each position of input block
Add two extra orders.
As shown in Figure 9 B, extra order can be inserted at the beginning of data block to obtain Virtual Agent code block 920.Similarly,
As shown in Figure 9 C, extra order can be inserted at the ending of data block to obtain Virtual Agent code block 930.
As shown in fig. 9d, extra order can be inserted into pseudo random pattern or based on scheduled intercalation model.For example, as schemed
It is first of input block in example shown in 9D, after two extra orders, is followed by an extra order, is followed by input
The second of data block is followed by three extra orders, is followed by third position of data block etc..It in one implementation, can be with
Using pseudorandom intercalation model, wherein the seed of pseudo random pattern or initial value can be based on such as current based on frame or subframe
The value of the value of index etc.
Embodiment described herein can be implemented in the system using any appropriately configured hardware and/or software
In.Figure 10 shows the exemplary components of the electronic equipment 1000 for one embodiment.In embodiment, electronic equipment 1000 can
To be mobile device or RAN node (for example, eNodeB).In some embodiments, electronic equipment 1000 may include at least such as
Application circuit 1002, baseband circuit 1004, radio frequency (RF) circuit 1006, the front-end module being coupled shown in figure
(FEM) circuit 1008 and one or more antennas 1060.In other embodiments, any circuit can be included in difference
Equipment in.In one implementation, previously described realization method can be realized by baseband circuit 1004.
Application circuit 1002 may include one or more application processor.For example, application circuit 1002 may include electricity
Road, such as, but not limited to：One or more single or multiple core processors.(one or more) processor may include general procedure
The arbitrary combination of device and application specific processor (for example, graphics processor, application processor etc.).Processor can be with memory/deposit
Storage device is coupled and/or may include storage/memory, and can be configured as and operate in memory/storage dress
The instruction of storage is set so that various applications and/or operating system can be run in system.Storage/memory can be with
Can be non-transitory computer-readable medium including such as computer-readable medium 1003.In some embodiments, using electricity
Road 1002 may be coupled to or including one or more sensors, such as environmental sensor, camera etc..
Baseband circuit 1004 may include circuit, such as, but not limited to：One or more single or multiple core processors.Base band
Circuit 1004 may include one or more baseband processor and/or control logic, be believed from the reception of RF circuits 1006 with processing
The baseband signal that number path receives, and generate the baseband signal of the transmission signal path for RF circuits 1006.Base-Band Processing electricity
Road 1004 can be engaged with application circuit 1002, to generate and handle baseband signal and control the operation of RF circuits 1006.
For example, in some embodiments, baseband circuit 1004 may include the second generation (2G) baseband processor 1004a, the third generation (3G)
Baseband processor 1004b, forth generation (4G) baseband processor 1004c, and/or for other existing generations, in exploitation or future
One or more other baseband processor 1004d in the generation (for example, the 5th generation (5G), 10G etc.) that will be developed.Baseband circuit
1004 (for example, one or more of baseband processor 1004a-1004d) can handle support via RF circuits 1006 and one
The various radio control functions that a or multiple radio nets are communicated.Radio control functions may include but unlimited
In：Signal modulation/demodulation, coding/decoding, radio frequency displacement etc..In some implementations, the function of baseband circuit 904 can
With by being configured as executing the memory/storage for being stored in the instruction in storage/memory completely or partially in fact
It is existing.Storage/memory may include such as non-transitory computer-readable medium 1004h.
In some embodiments, the modulation/demodulation circuit of baseband circuit 1004 may include Fast Fourier Transform
(FFT), precoding, and/or constellation mapping/demapping function.In some embodiments, the coding/decoding of baseband circuit 1004
Circuit may include convolution, tail biting (tail-biting) convolution, turbo, Viterbi (Viterbi) and/or low-density parity-check
Test (LDPC) coder/decoder functionalities.The embodiment of modulating/demodulating and coder/decoder functionalities is not limited to these examples,
And may include other functions appropriate in other embodiments.In some embodiments, baseband circuit 1004 may include
The element of protocol stack, for example, the element of evolved universal terrestrial radio access network (EUTRAN) agreement, it may for example comprise：Physics
(PHY), M AC (MAC), radio link control (RLC), Packet Data Convergence Protocol (PDCP), and/or wireless
Electric resources control (RRC) element.Central processing unit (CPU) 1004e of baseband circuit 1004 can be configured as operation agreement
The element of the signaling for PHY, MAC, RLC, PDCP, and/or rrc layer of stack.In some embodiments, baseband circuit can wrap
Include one or more audio digital signal processors (DSP) 1004f.One or more audio DSP 1004f may include being used for
The element of compression/de-compression and echo cancellor, and may include other processing elements appropriate in other embodiments.
In some embodiments, baseband circuit 1004 may include the element of protocol stack, for example, evolved universal terrestrial is wireless
It is electrically accessed the element of net (EUTRAN) agreement, it may for example comprise：Physics (PHY), M AC (MAC), radio link control
Make (RLC), Packet Data Convergence Protocol (PDCP), and/or radio resource control (RRC) element.In baseband circuit 1004
Central Processing Unit (CPU) 1004e can be configured as operation protocol stack for PHY, MAC, RLC, PDCP, and/or rrc layer
The element of signaling.In some embodiments, baseband circuit may include one or more audio digital signal processors (DSP)
1004f.One or more audio DSP 1004f may include the element for compression/de-compression and echo cancellor, and at it
May include other processing elements appropriate in his embodiment.
Baseband circuit 1004 can also include storage/memory 1004g.Storage/memory 1004g can be used
In load and store the data by the operation of the processor execution of baseband circuit 1004 and/or instruction.Storage/memory
1004g can include specifically non-transient memory.The storage/memory of one embodiment may include suitable volatile
Any combinations of property memory and/or nonvolatile memory.Storage/memory 1004g may include various ranks
Any combinations of storage/memory, including but not limited to：It is deposited with embedded software instruction the read-only of (for example, firmware)
Reservoir (ROM), random access memory (for example, dynamic random access memory (DRAM)), caching, buffer etc..Memory/
Storage device 1004g can share between various processors or be exclusively used in par-ticular processor.
In some embodiments, the component of baseband circuit can be combined as suitable in one single chip, one single chip group,
Or it is disposed on same circuit board.In some embodiments, baseband circuit 1004 and application circuit 1002 some or it is complete
Portion's composition component can be for example achieved in system on chip (SOC).
In some embodiments, baseband circuit 1004 can provide the communication compatible with one or more radiotechnics.
For example, in some embodiments, baseband circuit 1004 can support with evolved universal terrestrial radio access network (EUTRAN) and/
Or the communication of other wireless MANs (WMAN), WLAN (WLAN), wireless personal-area network (WPAN).Wherein base band electricity
Road 1004 is configured as supporting the embodiment of the radio communication of multiple wireless protocols can be referred to as multimode baseband circuit.
RF circuits 1006 can be supported to be communicated with wireless network using modulated electromagnetic radiation by non-solid medium.
In various embodiments, RF circuits 1006 may include switch, filter, amplifier etc. to assist the communication with wireless network.
RF circuits 1006 may include receiving signal path, which may include to being received from FEM circuits 1008
RF signals carry out down coversion and baseband signal are supplied to the circuit of baseband circuit 1004.RF circuits 1006 can also include sending
Signal path, the transmission signal road may include that the baseband signal provided to baseband circuit 1004 carries out up-conversion, and by RF
Output signal is supplied to FEM circuits 1008 for the circuit of transmission.
In some embodiments, RF circuits 1006 may include receiving signal path and transmission signal path.RF circuits
1006 reception signal path may include mixer 1006a, amplifier circuit 1006b and filter circuit
1006c.The transmission signal path of RF circuits 1006 may include filter circuit 1006c and mixer 1006a.RF circuits
1006 can also include condensating synthesizering circuit 1006d, and the condensating synthesizering circuit is for synthesizing for receiving signal path and sending signal road
The frequency that the mixer 1006a of diameter is used.In some embodiments, the mixer 1006a for receiving signal path can
To be configured as believing the RF received from FEM circuits 1008 based on the frequency synthesis provided by condensating synthesizering circuit 1006d
Number carry out down coversion.Amplifier circuit 1006b, which can be configured as, amplifies downconverted signal and filter circuit
1006c can be configured as removing undesired signal from downconverted signal to generate the low pass filtered of output baseband signal
Wave device (LPF) or bandpass filter (BPF).
Output baseband signal is provided to baseband circuit 1004 for further processing.In some embodiments, it exports
Baseband signal can be zero frequency baseband signal, but this is not required.In some embodiments, the mixing of signal path is received
Device circuit 1006a may include passive frequency mixer, but the range of embodiment is not limited in this respect.
In some embodiments, the mixer 1006a for sending signal path can be configured as based on synthesizer electricity
The frequency synthesis that road 1006d is provided carries out up-conversion to input baseband signal, to generate the RF outputs for FEM circuits 1008
Signal.Baseband signal can be provided by baseband circuit 1004, and can be filtered by filter circuit 1006c.Filter circuit
1006c may include low-pass filter (LPF), but the range of embodiment is not limited in this respect.
In some embodiments, it receives the mixer 1006a of signal path and sends the frequency mixer electricity of signal path
Road 1006a may include two or more frequency mixers, and can be arranged to be respectively used to quadrature frequency conversion and/or upper change
Frequently.In some embodiments, it receives the mixer 1006a of signal path and sends the mixer of signal path
1006a may include two or more frequency mixers, and can be arranged to image and inhibit (for example, Hartley images press down
System).In some embodiments, it receives the mixer 1006a of signal path and sends the mixer of signal path
1006a can be arranged to be respectively used to Direct-conversion and/or Direct conversion.In some embodiments, signal road is received
The mixer 1006a of diameter and the mixer 1006a for sending signal path can be configured for superheterodyne operation.
In some embodiments, output baseband signal and input baseband signal can be analog baseband signals, but implement
The range of example is not limited in this respect.In some alternative embodiments, output baseband signal and input baseband signal can be
Digital baseband signal.In these alternate embodiments, RF circuits 1006 may include analog-digital converter (ADC) and digital analog converter
(DAC) circuit, and baseband circuit 1004 may include digital baseband interface to be communicated with RF circuits 1006.
In some bimodulus embodiments, individual radio IC circuits can be provided to handle the signal of each frequency spectrum, but
It is that the range of embodiment is not limited in this respect.
In some embodiments, condensating synthesizering circuit 1006d can be fractional N synthesizer or score N/N+6 synthesizers, still
The range of embodiment is not limited in this respect, because other kinds of frequency synthesizer may be suitable.For example, synthesizer
Circuit 1006d can be delta-sigma synthesizer, frequency multiplier or the synthesizer including having the phaselocked loop of frequency divider.
Condensating synthesizering circuit 1006d, which can be configured as, to be synthesized based on frequency input and frequency divider control input for RF circuits
The output frequency that 1006 mixer 1006a is used.In some embodiments, condensating synthesizering circuit 1006d can be score
N/N+6 synthesizers.
In some embodiments, frequency input can be provided by voltage controlled oscillator (VCO), but this is not required.Frequency dividing
Device control input can be provided by baseband circuit 1004 or application processor 1002 according to required output frequency.In some realities
It applies in example, can determine frequency divider control input (for example, N) from look-up table based on the channel indicated by application processor 1002.
The condensating synthesizering circuit 1006d of RF circuits 1006 may include frequency divider, delay lock loop (DLL), multiplexer and
Phase accumulator.In some embodiments, frequency divider can be dual-mode frequency divider (DMD), and phase accumulator can be several
Word phase accumulator (DPA).In some embodiments, DMD can be configured as input signal divided by N or N+6 (for example, base
In carry-out) to provide score division ratio.In some example embodiments, DLL may include one group cascade tunable
Delay element, phase detectors, charge pump and D flip-flop.In these embodiments, delay element can be configured as
The VCO periods are at most resolved into Nd equal phase groupings, wherein Nd is the number of the delay element in delay line.With this
Kind mode, it is a VCO period that DLL, which provides negative-feedback to assist in ensuring that the total delay by delay line,.
In some embodiments, condensating synthesizering circuit 1006d can be configured as the carrier frequency generated as output frequency,
And in other embodiments, output frequency can be the multiple of carrier frequency (for example, twice of carrier frequency, carrier frequency
Four times) and be used together with divider circuit with quadrature generator, there are multiple phases different from each other to be generated in carrier frequency
Multiple signals of position.In some embodiments, output frequency can be LO frequencies (fLO).In some embodiments, RF circuits
1006 may include IQ/ polarity switch.
FEM circuits 1008 may include receive signal path, the reception signal path may include be configured as operation from
Signal that RF signals that one or more antennas 1060 receive, amplification receive and by the enlarged version of received signal
Originally it is supplied to the circuit of RF circuits 1006 for further processing.FEM circuits 1008 can also include sending signal path, the hair
It may include being configured as the signal being used for transmission that amplification RF circuits 1006 are provided with by one or more to send signal path
The circuit of one or more of antenna 1060 antenna transmission.
In some embodiments, FEM circuits 1008 may include TX/RX switches, in sending mode and reception pattern behaviour
Switch between work.FEM circuits may include receiving signal path and transmission signal path.The reception signal path of FEM circuits can
To include low-noise amplifier (LNA) to amplify the RF signals received, and the enlarged RF signals received are provided and are made
For (for example, to RF circuits 1006) output.The transmission signal path of FEM circuits 1008 may include for amplifying input RF letters
The power amplifier (PA) of number (for example, being provided by RF circuits 1006) and for generating for subsequent transmission (for example, passing through
One or more of one or more antennas 1060 antenna) RF signals one or more filters.
In some embodiments, electronic equipment 1000 may include such as storage/memory, display, camera,
The add ons of sensor and/or input/output (I/O) interface etc.In some embodiments, the electronic equipment of Figure 10 can be with
Be configured as executing one or more methods, process, and/or technology, it is all as described herein those.
Next many examples related with the realization of above-mentioned technology will be provided.
In the first example, the device for being used for the baseband processor of user equipment (UE) may include for carrying out following grasp
The circuit of work：Input traffic is handled to obtain the input block of particular size；It is big to obtain that additional data is inserted into input block
The Virtual Agent code block of the small particular size more than input block；Virtual Agent code block is encoded to obtain using turbo coding techniques
Encoded code block is obtained, encoded code block includes components of system as directed and parity portion；From encoded code block
Additional data is removed in components of system as directed, to obtain the output for including the components of system as directed and parity portion that eliminate additional data
Data block；And output output block, to be handled and be transmitted by channel.
In example 2, the theme of example 1, wherein the circuit is additionally operable to：Additional data is generated as to the sequence of full zero-bit
The sequence of row or Quan Yiwei.
In example 3, any exemplary theme of example 1 or this paper, wherein the circuit is additionally operable to：By additional data
It is generated as pseudo-random bit sequence.
In example 4, any exemplary theme of example 1,2 or 3 or this paper, wherein additional data is inserted into input
Block is included in insertion additional data at the start or end of input block.
In example 5, any exemplary theme of example 1,2 or 3 or this paper, wherein additional data is inserted into input
Block includes that additional data is pseudorandomly inserted into input block.
In example 6, any exemplary theme of example 5 or this paper, wherein the pseudorandom insertion of additional data is to be based on
Index value based on subframe or frame index acquisition.
In example 7, any exemplary theme of example 2 or 3 or this paper, wherein additional data is inserted into input block
Include that additional data is inserted at the position of the equal intervals in input block.
In example 8, any exemplary theme of example 1,2 or 3 or this paper, wherein turbo coding techniques includes system
Convolution turbo codes.
In example 9, any exemplary theme of example 1,2 or 3 or this paper, wherein circuit is additionally operable to based on following interior
Hold the size for determining Virtual Agent code block：B=a* (1/R -1)/2, wherein b is the size of Virtual Agent code block, and a is the big of input block
It is small, and R is code rate.
In the tenth example, computer-readable medium can include for so that one associated with communication equipment or more
A processor carries out the following program instruction operated：Input traffic is handled to obtain the input block of particular size；By additional number
Virtual Agent code block of the size more than the particular size of input block is obtained according to input block is inserted into；Use turbo coding techniques pair
Virtual Agent code block is encoded to obtain encoded code block, and encoded code block includes components of system as directed and even-odd check portion
Point；Encoded code block is handled to obtain output block, which includes the encoded of not additional data
The components of system as directed and parity portion of code block.
In example 11, any exemplary theme of example 10 or this paper, wherein communication equipment includes user equipment (UE)
Equipment or evolved node B (eNB) equipment.
In example 12, any exemplary theme of example 10 or 11 or this paper, wherein program instruction also make one or
Multiple processors carry out following operation：Additional data is inserted by being inserted into additional data at the start or end of input block
To input block.
In example 13, any exemplary theme of example 10 or 11 or this paper, wherein program instruction also make one or
Multiple processors carry out following operation：Additional data is inserted by the way that additional data to be pseudorandomly inserted in input block
Input block.
In example 14, any exemplary theme of example 13 or this paper, wherein the pseudorandom insertion of additional data is base
In the index value based on subframe or frame index acquisition.
In example 15, any exemplary theme of example 10 or this paper, wherein turbo coding techniques include system convolution
Turbo codes.
In example 16, any exemplary theme of example 10 or 11 or this paper, wherein program instruction also make one or
Multiple processors determine the size of Virtual Agent code block based on the following contents：B=a* (1/R -1)/2, wherein b is virtual code
The size of block, a is the size of input block, and R is code rate.
In the 17th example, the communication equipment for cellular network can be used for carrying out following operate：Receive coding speed
The instruction of rate；The desired size of Virtual Agent code block is determined based on the instruction of code rate；Input traffic is handled to obtain spy
Determine the input block of size；Additional data is generated, the length of the additional data generated is the desired size based on Virtual Agent code block
It is determined with the particular size of input block；The additional data generated is inserted into input block to obtain with desired size
Virtual Agent code block；Virtual Agent code block is encoded using turbo coding techniques to obtain encoded code block, it is encoded
Code block include components of system as directed and parity portion；Virtual Agent code block is compressed with from the components of system as directed of encoded code block
Middle removal additional data sequence simultaneously obtains output block；And output output block by channel to be transmitted.
In example 18, any exemplary theme of example 17 or this paper, wherein communication equipment includes user equipment (UE)
Equipment or evolved node B (eNB) equipment.
In example 19, any exemplary theme of example 17 or this paper, wherein communication equipment is additionally operable to additional data
It is generated as the sequence of full zero-bit or the sequence of Quan Yiwei.
In example 20, any exemplary theme of example 17 or this paper, wherein communication equipment is additionally operable to additional data
It is generated as pseudo-random bit sequence.
In example 21, any exemplary theme of example 17-20 or this paper, wherein additional data is inserted into input
Block includes：Additional data is inserted at the start or end of input block；Or be based on scheduled intercalation model, in input block puppet with
It is inserted into additional data to machine.
In example 22, any exemplary theme of example 17-20 or this paper, wherein turbo coding techniques includes system
Convolution turbo codes.
In example 23, the theme of example 17, wherein the circuit is additionally operable to base the following contents to determine Virtual Agent code block
Size：B=a* (1/R -1)/2, wherein b is the size of Virtual Agent code block, and a is the size of input block, and R is coding speed
Rate.
In the 24th example, a kind of method of coded data, this method includes：Input traffic is handled to obtain spy
Determine the input block of size；Additional data is inserted into input block to obtain virtual code of the size more than the particular size of input block
Block；Virtual Agent code block is encoded using turbo coding techniques to obtain encoded code block, the encoded code
Block includes components of system as directed and parity portion；Additional data is removed from the components of system as directed of encoded code block to be wrapped
Include the output block of the components of system as directed and parity portion that eliminate additional data；And output output block is to pass through
Channel is transmitted.
In example 25, any exemplary theme of example 24 or this paper further include：Additional data is generated as full zero-bit
Or the sequence of Quan Yiwei.
In example 26, any exemplary theme of example 24 or this paper further include：Additional data is generated as pseudorandom
Bit sequence.
In example 27, any exemplary theme of example 24,25 or 26 or this paper, wherein be inserted into additional data
Input block is included in insertion additional data at the start or end of input block.
In example 28, any exemplary theme of example 24,25 or 26 or this paper, wherein be inserted into additional data
Input block includes that additional data is pseudorandomly inserted into input block.
In example 29, any exemplary theme of example 28 or this paper, wherein the pseudorandom insertion of additional data is base
In the index value based on subframe or frame index acquisition.
In example 30, any exemplary theme of example 24 or this paper, wherein additional data is inserted into input block packet
Include insertion additional data at the position of the equal intervals in input block.
In example 31, any exemplary theme of example 24 or this paper, wherein turbo coding techniques includes system volume
Product turbo codes.
In example 32, any exemplary theme of example 24 or this paper further include：It is determined based on the following contents virtual
The size of code block：B=a* (1/R -1)/2, wherein b is the size of Virtual Agent code block, and a is the size of input block, and R is
Code rate.
In example 33, equipment may include：For handling input traffic to obtain the dress of the input block of particular size
It sets；For additional data to be inserted into input block to obtain dress of the size more than the Virtual Agent code block of the particular size of input block
It sets；Virtual Agent code block is encoded to obtain the device of encoded code block for using turbo coding techniques, wherein
The encoded code block includes components of system as directed and parity portion；For from the components of system as directed of encoded code block
Except additional data to obtain the device of output block, which includes eliminating the components of system as directed of additional data and strange
Even parity check part；And the device for exporting output block to be transmitted by channel.
In example 34, any exemplary theme of example 33 or this paper further include：For additional data to be generated as entirely
The device of the sequence of zero-bit or the sequence of Quan Yiwei.
In example 35, any exemplary theme of example 33 or this paper further include：For additional data to be generated as puppet
The device of random bit sequences.
In example 36, any exemplary theme of example 33 or this paper, wherein additional data is inserted into input block packet
Include the insertion additional data at the start or end of input block.
In the 37th example, for evolved node B (eNB) baseband processor device may include for into
The following circuit operated of row：Input traffic is handled to obtain the input block of particular size；Additional data is inserted into input block
To obtain Virtual Agent code block of the size more than the particular size of input block；Using turbo coding techniques come to Virtual Agent code block into
For row coding to obtain encoded code block, which includes components of system as directed and parity portion；From warp knit
Removal additional data is to obtain components of system as directed and the odd even school including eliminating additional data in the components of system as directed of the code block of code
Test the output block of part；And output output block by channel to be handled and be transmitted.
In example 38, any exemplary theme of example 37 or this paper, wherein the circuit is additionally operable to give birth to additional data
As the sequence of full zero-bit or the sequence of Quan Yiwei.
In example 39, the theme in any example of example 37 or this paper, wherein the circuit is additionally operable to additional data
It is generated as pseudo-random bit sequence.
In example 40, any exemplary theme of any one of example 37,38 or 39 or this paper, wherein by additional number
It is included in insertion additional data at the start or end of input block according to input block is inserted into.
In example 41, any exemplary theme of any one of example 37,38 or 39 or this paper, wherein by additional number
Include that additional data is pseudorandomly inserted into input block according to input block is inserted into.
In specification in front, various embodiments are described by reference to attached drawing.It will be apparent, however, that can be with
It is carry out various modifications and is changed, and other embodiment may be implemented, without departing from such as explaining in the following claims
The wider range stated.Therefore, the description and the appended drawings are considered illustrative and not restrictive.
Although, can be in other realization methods for example, describe a series of signal and/or operation about Fig. 7 and 8
Change the sequence of signal.Furthermore, it is possible to execute non-dependent signal parallel.
It is readily apparent that exemplary aspect as described above can be in the shown realization method of figure with many not similar shapes
Software, firmware and the hardware of formula is realized.For realizing in terms of these actual software code or special control hardware should not be by
It is construed to restrictive.Therefore, the operation and behavior-that various aspects are described without reference to specific software code should be managed
Software and control hardware design can be to realize these aspects based on description herein by solution.
Even if describing and/or disclosing in the description the specific combination of feature in the claims, but these groups
Merging is not intended to restrictive.In fact, many features in these features can be recorded with not specific in the claims
And/or specifically disclosed mode does not combine in the description.
Unless explicitly described, otherwise element used herein, action or instruction are not necessarily to be construed as key or must
It wants.As it is used herein, to term " and " the example used not necessarily exclude it is expected phrase "and/or" in this example
Explanation.Similarly, as it is used herein, not necessarily excluding it is expected in this example to the example of term "or" used short
The explanation of language "and/or".In addition, as it is used herein, article " one (a) " is intended to include one or more project, and can
To be used interchangeably with phrase " one or more ".In the case where only it is expected a project, term " one (one) ", " list are used
It is a ", " only " or similar language.
Claims (23)
1. device of the one kind for the baseband processor of user equipment (UE), described device includes the electricity for being operated below
Road：
Input traffic is handled to obtain the input block of particular size；
Additional data is inserted into the input block to obtain Virtual Agent of the size more than the particular size of the input block
Code block；
The Virtual Agent code block is encoded using turbo coding techniques to obtain encoded code block, it is described encoded
Code block include components of system as directed and parity portion；
The additional data is removed from the components of system as directed of the encoded code block, it is described including eliminating to obtain
The output block of the components of system as directed and the parity portion of additional data；And
The output block is exported, to be handled and be transmitted by channel.
2. the apparatus according to claim 1, wherein the circuit is additionally operable to：
The additional data is generated as to the sequence of full zero-bit or the sequence of Quan Yiwei.
3. the apparatus according to claim 1, wherein the circuit is additionally operable to：
The additional data is generated as pseudo-random bit sequence.
4. according to the device described in any one of claim 1,2 or 3, wherein the additional data is inserted into the input
Block, which is included at the start or end of the input block, is inserted into the additional data.
5. according to the device described in any one of claim 1,2 or 3, wherein the additional data is inserted into the input
Block includes that the additional data is pseudorandomly inserted into the input block.
6. device according to claim 5, wherein the pseudorandom insertion of the additional data is to be based on subframe or frame
Index the index value obtained.
7. the device according to any one of Claims 2 or 3, wherein the additional data is inserted into the input block
Include that the additional data is inserted at the position of the equal intervals in the input block.
8. according to the device described in any one of claim 1,2 or 3, wherein the turbo coding techniques includes system convolution
Turbo codes.
9. according to the device described in any one of claim 1,2 or 3, wherein the circuit is additionally operable to：
The size of the Virtual Agent code block is determined based on the following contents：
B=a* (1/R -1)/2
Wherein, b is the size of the Virtual Agent code block, and a is the size of the input block, and R is code rate.
10. a kind of computer-readable medium, including for so that one or more processors associated with communication equipment carry out
The program instruction operated below：
Input traffic is handled to obtain the input block of particular size；
Additional data is inserted into the input block to obtain Virtual Agent of the size more than the particular size of the input block
Code block；
The Virtual Agent code block is encoded using turbo coding techniques to obtain encoded code block, it is described encoded
Code block include components of system as directed and parity portion；
The encoded code block is handled to obtain output block, the output block includes no additional data
The encoded code block the components of system as directed and the parity portion；And
The output block is exported, to be handled and be transmitted by channel.
11. computer-readable medium according to claim 10, wherein the communication equipment includes that user equipment (UE) is set
Standby or evolved node B (eNB) equipment.
12. the computer-readable medium according to claim 10 or 11, wherein described program instruction is also so that one
Or multiple processors carry out following operation：
It is inserted by being inserted into the additional data at the start or end of the input block by the additional data described
Input block.
13. the computer-readable medium according to claim 10 or 11, wherein described program instruction is also so that one
Or multiple processors carry out following operation：
By the additional data is pseudorandomly inserted in the input block additional data is inserted into it is described defeated
Enter block.
14. computer-readable medium according to claim 13, wherein the pseudorandom insertion of the additional data is to be based on
Index value based on subframe or frame index acquisition.
15. computer-readable medium according to claim 10, wherein the turbo coding techniques includes system convolution
Turbo codes.
16. according to the computer-readable medium described in any one of claim 10 or 11, wherein described program instruction also makes
One or more of processors carry out following operation：
The size of the Virtual Agent code block is determined based on the following contents：
B=a* (1/R -1)/2
Wherein, b is the size of the Virtual Agent code block, and a is the size of the input block, and R is code rate.
17. a kind of communication equipment for cellular network, the communication equipment is used for：
Receive the instruction of code rate；
The desired size of Virtual Agent code block is determined based on the instruction of the code rate；
Input traffic is handled to obtain the input block of particular size；
Additional data is generated, the length of the additional data generated is the desired size and institute based on the Virtual Agent code block
The particular size of input block is stated to determine；
The additional data generated is inserted into the input block to obtain the Virtual Agent code block with the desired size；
The Virtual Agent code block is encoded using turbo coding techniques to obtain encoded code block, the warp knit
The code block of code includes components of system as directed and parity portion；
The Virtual Agent code block is compressed to remove additional data sequence from the components of system as directed of the encoded code block
And obtain output block；And
The output block is exported to be transmitted by channel.
18. communication equipment according to claim 17, wherein the communication equipment includes user equipment (UE) equipment or drills
Into type node B (eNB) equipment.
19. communication equipment according to claim 17, wherein the communication equipment is additionally operable to：
The additional data is generated as to the sequence of full zero-bit or the sequence of Quan Yiwei.
20. communication equipment according to claim 17, wherein the communication equipment is additionally operable to：
The additional data is generated as pseudo-random bit sequence.
21. according to the communication equipment described in any one of claim 17-20, wherein be inserted into the additional data described
Input block includes：
The additional data is inserted at the start or end of the input block；Or
Based on scheduled intercalation model, the additional data is pseudorandomly inserted into the input block.
22. according to the communication equipment described in any one of claim 17-20, wherein the turbo coding techniques includes system
Convolution turbo codes.
23. communication equipment according to claim 17, wherein the circuit is additionally operable to：
The size of the Virtual Agent code block is determined based on the following contents：
B=a* (1/R -1)/2
Wherein, b is the size of the Virtual Agent code block, and a is the size of the input block, and R is code rate.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201662302038P | 2016-03-01 | 2016-03-01 | |
| US62/302,038 | 2016-03-01 | ||
| PCT/US2016/039077 WO2017151175A1 (en) | 2016-03-01 | 2016-06-23 | Turbo coding with support for low coding rates |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108604904A true CN108604904A (en) | 2018-09-28 |
Family
ID=56292980
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201680080815.2A Pending CN108604904A (en) | 2016-03-01 | 2016-06-23 | For supporting the TURBO of low code rate to encode |
Country Status (3)
| Country | Link |
|---|---|
| CN (1) | CN108604904A (en) |
| HK (1) | HK1258347A1 (en) |
| WO (1) | WO2017151175A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20220158760A1 (en) * | 2019-04-09 | 2022-05-19 | Lg Electronics Inc. | Interleaving for code block |
| CN112118012A (en) * | 2019-06-20 | 2020-12-22 | 中兴通讯股份有限公司 | Method and device for determining iteration times of decoder |
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| Publication number | Publication date |
|---|---|
| HK1258347A1 (en) | 2019-11-08 |
| WO2017151175A1 (en) | 2017-09-08 |
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