CN108604790B

CN108604790B - Delay circuit for circuit interrupting device

Info

Publication number: CN108604790B
Application number: CN201580085756.3A
Authority: CN
Inventors: S·P·西莫宁
Original assignee: Hubbell Inc
Current assignee: Hubbell Inc
Priority date: 2015-12-18
Filing date: 2015-12-18
Publication date: 2020-06-19
Anticipated expiration: 2035-12-18
Also published as: CN108604790A; WO2017105484A1; CA3009053A1; CA3009053C; MX2018007473A; CN111525506A

Abstract

A circuit interrupting device includes a line conductor, a load conductor, an interrupting device, a delay circuit, and a fault detection circuit. The interrupting device disconnects the line conductor from the load conductor when the circuit interrupting device is in a tripped condition. The delay circuit includes a first switch, a second switch, and a third switch, and delays the disconnection of the line conductor from the load conductor. The fault detection circuit detects a fault condition and generates a fault detection signal when the fault condition is detected. The fault detection circuit provides the fault detection signal to the first switch to trigger the first switch, and the delay circuit delays the triggering of the second switch and the third switch. After a certain amount of time has elapsed, triggering the second switch and the third switch to place the circuit interrupting device in the tripped condition.

Description

Delay circuit for circuit interrupting device

Technical Field

The present invention generally relates to electrical devices with switches. More particularly, the present invention relates to self-test circuit interrupting devices, such as ground fault circuit interrupter ("GFCI") devices, that switch from a "reset" or latched state to a "tripped" or unlatched state when one or more conditions are detected. Such devices consistent with the invention disclosed herein have more robust self-test capabilities than those provided in previously known GFCI devices.

Background

GFCI devices having contacts biased toward the open position require a latching mechanism for setting and maintaining the contacts in the closed position. As such, a switched electrical device having contacts biased toward the closed position requires a latching mechanism for setting and maintaining the contacts in the open position. Examples of conventional types of devices include circuit interrupting type devices such as circuit breakers, arc fault interrupters and GFCIs, to name a few.

For commercial sale in the united states, GFCI devices must meet standards established by the underwriter's laboratory ("UL") in conjunction with industry leading manufacturers and other industry members, such as various safety organizations. One UL Standard that covers GFCI devices is UL-943 entitled "Standard for Safety-ground fault Circuit Interrupters". UL-943 applies to class A monophasic andthree-phase GFCI devices are intended to protect workers and have minimal requirements for the function, construction, performance and labeling of such GFCI devices. UL-943, among other things, requires a specific fault current level and response timing requirements that the GFCI device should trip. Typically, GFCIs are required to trip when a ground fault having a level above 5 milliamps ("mA") is detected. In addition, when a high resistance ground fault is applied to the device, according to the equation T ═ 20/I)^1.43The present version of UL-943 specifies that the device should trip and prevent current from being delivered to the load, where T refers to time and is expressed in seconds and I refers to current and is expressed in milliamps. Thus, in the case of a 5mA fault, the device must detect the fault and trip in 7.26 seconds or less.

With such safety-related standards in place, and because GFCI devices were directly considered to save many lives due to their introduction in the early 70's of the 19 th century, they have become ubiquitous in residential and commercial power grids. However, like most electromechanical devices, GFCI devices are susceptible to faults. For example, one or more of the electronic components driving a mechanical current interrupter device may short circuit or otherwise become defective, as may components in the fault detector circuit or elsewhere within the device, thereby rendering the device unable to properly detect a ground fault and/or properly interrupt the flow of current. For this reason, it has long been desirable to have GFCI devices with monitoring circuits that enable the ability of the device to be manually tested to trip when a fault is encountered. Such monitoring circuits typically have a test button that, when pressed, actuates a simulated ground fault on the hot and neutral conductors. If the device is functioning properly, a simulated fault is detected and the device will trip, i.e., actuate a mechanical interrupter to disconnect the current path connecting the line side (e.g., in the case of AC power being supplied) and the load side of the device (where the user connects his appliance, etc., and where a downstream receptacle or additional GFCI device is connected).

Research conducted by industry safety organizations indicates that, generally speaking, the public does not regularly test their GFCI devices to determine proper operation, i.e., by pressing a test button. This study further reveals that some GFCI devices that have been in service for extended periods of time become inoperative and fail to properly detect fault conditions, thus rendering the device unsafe. Specifically, it has been found that after extended use, GFCI devices fail to trip when a fault occurs, thus making the device operable as an electrical outlet, but unsafe when a fault condition exists. This unsafe condition is exacerbated because the device is not being tested on a regular basis. That is, when in fact the device is a potentially life-threatening source of harm, one erroneously believes that the device is operating in view of the fact that it is delivering sufficient power.

Combined with the realization that GFCI devices will not be tested on a regular basis (although the clear instructions of the manufacturer are periodic tests), the discovery that GFCI devices deployed in the field are becoming increasingly inoperable and unsafe has led to the start of research into possible changes to the UL-943 standard to require the GFCI device to self-test itself (e.g., an automatic monitor) without human intervention. The expected changes to UL-943 further include a requirement to alert the consumer to the loss of protection and/or the device automatically removes itself from service (e.g., permanently trips). Furthermore, these additional self-test operations would have to be performed without disturbing the main function of the device, i.e. tripping when an actual fault is encountered.

The modified self-test functionality mentioned above is not yet a requirement for UL-943 certification, but is expected to be such a requirement soon. In preparation for this significant UL change, and in view of the seemingly unlimited reduction in the cost of integrated circuits, many GFCI manufacturers have moved to digital technologies (e.g., microprocessors and microcontrollers) that are advantageous to previous analog designs to provide both ground fault protection and self-monitoring functionality. However, the digital solutions provided have not heretofore been ideal. For example, several prior art GFCI designs, including those intended to provide self-test functionality, are subject to nuisance tripping, which is a situation in which an interrupter is actuated when neither a true ground fault, a manually generated simulated ground fault, nor an automatic self-test fault is present. This disadvantage is considered by many to be exacerbated by the additional requirement of automatic self-testing, which results in additional induced currents within the device.

It is therefore desirable to provide a GFCI device that provides some self-test capability, including those set forth in the next revision of UL-943, but which minimizes the risks associated with nuisance tripping.

Disclosure of Invention

In view of the problematic issues associated with prior art GFCI devices, including but not limited to the problematic issues discussed above, circuits in accordance with one or more exemplary embodiments of the present invention generally relate to automatic monitoring circuits that constantly monitor the performance of GFCI devices. More specifically, a processing device, such as a microcontroller or microprocessor, is configured to periodically execute an automatic monitoring routine based on a stored software program for testing and verifying the durability and functionality of the various sub-circuits within the GFCI device. To test the proper galvanic isolation of the GFCI device, a driver coupled to the microcontroller is operated to initiate a test signal indicative of a ground fault whenever an automatic monitoring routine is executed or run, and the different circuit nodes are monitored to confirm proper operation of the device.

An end-of-life indicator is also coupled to the microcontroller to indicate whether the GFCI device has failed to properly detect a test signal or some other fault that has occurred within the device. To avoid tripping the mechanical current interrupt device when a test signal is generated and to allow as many GFCI device circuits as possible to perform their intended functions, a unique watchdog circuit is provided that utilizes the various functionalities of the digital components (e.g., the GFCI integrated circuit device and the microcontroller). In particular, to provide an automatic test function that monitors the fault detection capability of a GFCI device under normal conditions without interfering with and causing false tripping, embodiments consistent with the present invention include specially selected filter capacitors associated with the interrupter drive outputs of the GFCI integrated circuit ("IC") device. Proper selection of capacitors and other related circuit components prevents an interrupter drive circuit (e.g., a silicon controlled rectifier ("SCR")) from starting or turning on until a real fault condition is encountered.

According to one aspect of the present invention, there is provided a circuit interruption device comprising one or more line conductors for electrical connection to an external power supply, one or more load conductors for electrical connection to an external load, and an interruption device connected to the line conductors and the load conductors. The interrupting device disconnects the line conductor from the load conductor when the circuit interrupting device is in a tripped condition and electrically connects the line conductor to the load conductor when the circuit interrupting device is not in a tripped condition. The circuit interrupting device also includes a delay circuit that delays the disconnection of the line conductor from the load conductor. The delay circuit includes a first switch, a second switch, and a third switch. A fault detection circuit detects a fault condition in the circuit interrupting device and generates a fault detection signal when the fault condition is detected. The fault detection circuit provides the fault detection signal to the first switch within the delay circuit to trigger the first switch, and the delay circuit delays the triggering of the second switch and the third switch by an amount of time. After the amount of time has elapsed, triggering the second switch and the third switch to place the circuit interrupting device in the tripped condition.

According to another aspect of the present invention, a wiring device is provided that includes an interrupter, a fault detection circuit, a solenoid, and a delay circuit. When activated, the interrupter places or maintains the wiring device in a tripped state to prevent current from flowing from the line side of the wiring device to the load side of the wiring device. The fault detection circuit is configured to detect one or more fault conditions in the wiring device and generate a fault detection signal when the one or more fault conditions meet a predetermined criterion. The solenoid is operable to activate the interrupter when conducting current. The delay circuit includes one or more switches electrically connected to the solenoid. The solenoid conducts current when one or more of the one or more switches are activated. The delay circuit delays activation of one or more of the one or more switches for an amount of time after generation of the fault detection signal. After the amount of time has elapsed, activating one or more of the one or more switches to place the wiring device in the trip condition.

Other aspects of the invention will become apparent by consideration of the detailed description and accompanying drawings.

Drawings

Exemplary embodiments of the invention are described in detail below with reference to the accompanying drawings by way of example.

Fig. 1 is a side elevational view of a self-testing GFCI receptacle unit in accordance with an exemplary embodiment of the invention.

Fig. 2 is a side elevational view of the self-testing GFCI receptacle of fig. 1 with the front cover of the housing removed.

Fig. 3 is a side elevational view of the core assembly of the self-testing GFCI receptacle apparatus shown in fig. 1.

Fig. 4A-4D are schematic diagrams of exemplary circuits consistent with exemplary embodiments of the present invention.

Figure 5 is an oscilloscope trace showing how delaying the opening of the contacts of an interrupting device reduces the power applied through the contacts of the interrupting device when the contacts open.

Detailed Description

Before the embodiments of the invention are explained in detail, it is to be understood that the invention is not limited in its application to the details of construction and the arrangement of components set forth in the following description or illustrated in the following drawings. The invention is capable of other embodiments and of being practiced or of being carried out in various ways.

Exemplary embodiments of devices consistent with the present invention include one or more of the novel mechanical and/or electrical features described in detail below. For example, one or more of the disclosed exemplary embodiments of the invention include an automatic monitoring or self-test feature. Some self-test features and capabilities with respect to GFCI devices have been previously disclosed, for example, in U.S. patent nos. 6,807,035, 6,807,036, 7,315,437, 7,443,309 and 7,791,848, filed on 3, 16, 2012, and in U.S. patent application No. 13/422,790, all of which are commonly assigned to the same assignee as the present application and the entire corresponding contents of which are incorporated herein by reference in their entirety. The automatic monitoring feature consistent with the invention disclosed herein is more robust than previously disclosed automatic monitoring features and reduces the probability of device false tripping or nuisance. For example, additional features are provided that relate to the determination of an end of life ("EOL") condition and the actions taken after such determination. Further exemplary novel electrical and mechanical features consistent with the present invention are described below with reference to the drawings.

Referring to fig. 1, a GFCI receptacle 10 according to an exemplary embodiment of the invention includes a front cover 12 having a dual wire seating surface 14 with phase 16, neutral 18 and ground 20 openings. Face 14 also has an opening 22 for receiving a reset button 24 adjacent an opening 26 for receiving a test button 28, and six corresponding circular openings 30 through 35. According to this exemplary embodiment,

openings

30, 33 accommodate two respective indicators, such as differently colored LEDs, openings 32, 34 accommodate respective bright LEDs, which function, for example, as a night light, opening 31 accommodates a light-conducting photocell, which functions, for example, as a control night light LED, and opening 35 provides access to a set screw for adjusting the photocell arrangement according to this and other exemplary embodiments. The rear cover 36 is secured to the front cover 12 by eight fasteners 38, four fasteners 38 being shown in fig. 1, and four additional fasteners are provided on the side of the receptacle 10 that is obscured from view in fig. 1. For example, each fastener 38 may include a barbed post 50 on the front cover 12 and a corresponding elastic cuff 52 on the back cover 36, similar to that described in detail in U.S. Pat. No. 6,398,594, which is incorporated herein by reference in its entirety. A ground yoke/bridge assembly 40 having standard mounting ears 42 extends from the ends of the receptacle 10.

Referring to fig. 2, the front cover 12 has been removed to expose the manifold 126, which provides support for the printed circuit board 390 and the yoke/bridge assembly 40. In accordance with the illustrated embodiment, the manifold 126 includes four dovetail interconnects 130 that mate with corresponding recesses 132 along the upper edge of the back cover 36. One dovetail-recess pair is provided on each of the four sides of the manifold 126 and back cover 36, respectively.

Fig. 3 is a side elevational view of the core assembly 80. The core assembly 80 includes a circuit board 82 that supports most of the working components of the receptacle, including the circuitry shown in fig. 4A-4D (which are collectively referred to herein as fig. 4), a sense transformer 84, and a grounded-neutral transformer 85 (not shown). The

line contact arms

94, 96 pass through the transformers 84, 85 with an insulating splitter 98 therebetween. The

line contact arms

94, 96 are cantilevered with their respective distal ends carrying phase and

neutral contacts

102, 104. The

load contact arms

98, 100 are also cantilevered with their respective distal ends carrying phase and neutral load contacts 101, 103. The resiliency of the cantilevered contact arms biases the

line contacts

102, 104 and the load contacts 101, 103 away from each other. The load contact arms 98, 103 rest on a movable contact carrier 106 made of an insulating (preferably thermoplastic) material.

Fig. 4 is a schematic diagram of the electrical and mechanical components of a GFCI receptacle device consistent with one or more of the exemplary embodiments of the invention. The circuit shown in fig. 4 may be used in a GFCI device as described above with respect to various embodiments of the invention. The circuit of FIG. 4 conforms to the mechanical operation of the exemplary embodiments described above; GFCI devices consistent with embodiments of the invention, however, need not use the precise circuit depicted in fig. 4, and those skilled in the art, upon viewing fig. 4 and/or reviewing the description set forth below, will be able to modify certain aspects of the circuit to achieve a similar overall result. Such modifications are contemplated and considered within the scope of the invention as set forth herein.

Fig. 4 is a schematic diagram of a circuit according to an exemplary embodiment of the invention. The circuit shown in fig. 4, or various sub-circuits thereof, may be implemented in a variety of electrical wiring devices, however for purposes of description the circuit of fig. 4 is discussed herein in connection with its use in the GFCI receptacle devices shown in fig. 1-3.

The circuit of fig. 4 includes a phase terminal 326 and a neutral terminal 328 for electrical connection to an AC power source (not shown), such as a 60hz, 120 volt rms power source used in the united states for household power. The circuitry of fig. 4, as well as the software resident thereon and implemented therewith, may be modified to accommodate other power transfer systems as well. Such modifications, as well as the resulting circuits and wiring devices in which the circuits and software will ultimately be used, are contemplated by the inventors and are considered to be within the spirit and scope of the invention described herein. For example, power transfer systems using different voltages and frequencies are within the scope of the present invention.

Referring to fig. 4, phase conductor 330 and neutral conductor 332 are connected to phase and neutral terminals, respectively, and each pass through a sense transformer 334 and a grounded-neutral transformer 336 as part of a detection circuit described below. For example, the phase and neutral line terminals correspond to the input terminal screws 326, 328 in fig. 1 above, and the phase and

neutral line conductors

330, 332 represent the

line contact arms

94, 96, respectively, as described above with respect to fig. 3. Each of the

line conductors

330, 332 has a respective fixed end that is connected to the phase and neutral line terminals and each includes a respective movable contact, such as

contacts

102, 104 from the embodiments described above. The face phase and face neutral conductors 338, 340 each include an electrical contact (not shown) secured thereto. The face conductors are electrically connected to, and in the illustrated embodiment are integral with,

respective face terminals

342, 344 to which blades from a load device (not shown), such as an appliance, will be connected when the electrical outlet device is in use.

The circuit shown in fig. 4 according to this embodiment also includes optional load phase and load

neutral terminals

346, 348, respectively, which are electrically connected to a downstream load (not shown), such as one or more additional outlet devices. The

load terminals

346, 348 are connected to cantilevered load conductors 277, 278, respectively, each of which includes a movable contact (not shown in fig. 4) at a distal end thereof. The load contacts are positioned below and coaxial with the respective phase and neutral line contacts and the phase and neutral plane contacts such that the three sets of contacts mate and electrically connect together as the line conductor moves toward the load and plane conductors. When a device is in this condition, it is said to be "reset" or in a reset state.

Detector circuit

With continued reference to fig. 4, detector circuit 352 includes

transformers

334, 336, and a GFCI integrated circuit device ("GFCIIC") 350. According to an embodiment of the present invention, the GFCI IC 350 is a well known 4141 device, such as the RV4141 device manufactured by Firmild Semiconductor Corporation. Other GFCI IC devices may also be used in the circuit of fig. 4 in place of 4141 and such modifications are within the spirit and scope of the present invention.

The GFCI IC apparatus 350 receives electrical signals from various other circuit components, including the

transformers

334, 336, and detects one or more faults, such as a real fault, a simulated fault, or a self-test ground fault, as well as a real or simulated grounded-neutral fault. For example, when sufficient current imbalance occurs in the

line conductors

330, 332, the net current through the

transformers

334, 336 results in a magnetic flux being generated at least around the transformer 334. This magnetic flux causes a current to be induced on conductor 333, which is wound around sensing transformer 334. Respective ends of conductor 333 are connected to the positive and negative inputs of the sense amplifier of GFCIIC device 350 at input ports V-REF and VFB, respectively. The induced current on conductor 333 causes a voltage difference at the input to the sense amplifier of GFCI IC 350. When the voltage difference exceeds a predetermined threshold, a detection signal is generated at one or more of the outputs of the GFCI IC 350, such as the SCR trigger signal output port (SCR _ OUT). The threshold used by the GFCI IC 350 is determined by the effective resistance connected between the operational amplifier output (OP _ OUT) and the positive input to the sense amplifier ("VFB").

The current imbalance on the

line conductors

330, 332 is caused by a real ground fault, a simulated ground fault, or a self-test ground fault. When the test switch 354 in fig. 4 is closed, which occurs when the test button 28 (fig. 1) is pressed, a simulated ground fault is generated. As described in further detail below, a self-test fault occurs when the auto-monitoring circuit 370 initiates an auto-monitoring test sequence that includes the generation of current on the isolated conductor 356.

According to an embodiment of the present invention, when test switch 354 is closed, some of the current flowing in

line conductors

330, 332 and load conductors 338, 340 is shunted away from phase plane conductor 338 (and phase load conductor 277 when the device is in a reset state) around sensing transformer 334 and through resistor 358 to neutral conductor 332. By shunting some of the current through resistor 358 in this manner, an imbalance is created in the current flowing through conductor 330 and the current flowing through conductor 332 in the opposite direction. When the current is unbalanced, i.e., the net current flowing through the conductors through the sensing transformer exceeds a threshold value (e.g., 4 to 5 milliamps), the detector circuit 352 detects this analog ground fault and activates the SCR output (SCR _ OUT) of the GFCI IC 350.

When the SCR output of the GFCI IC 350 is activated, the switch 360 (e.g., SCR) triggers to an ON state or condition, which allows current to flow from the phase conductor 330 through the resistor 500 and an opto-coupler 505. Opto-coupler 505 isolates the activation of switches 361 and 369 (e.g., SCRs) from the household power supply and solenoid (e.g., dual solenoid coil 362[ described below ]). Although the opto-coupler 505 is illustrated in fig. 4, in other configurations of the present invention, a different solid state relay may be substituted for the opto-coupler. For illustrative purposes, switches 360, 361, and 369 will be described herein with respect to embodiments of the invention in which each switch is an SCR. After SCR360 triggers to the on condition or state, opto coupler 505 is triggered or activated to the on condition or state and opto coupler 505 allows current to flow from pin 4 to pin 3 of opto coupler 505. A reverse biased zener diode 510 is connected across

pins

1 and 2 of the optocoupler 505 to protect the optocoupler 505 from surges and/or transient voltage spikes. For example, if a voltage greater than the breakdown voltage of the reverse bias of the zener diode 510 (e.g., 5V) is applied across the zener diode 510, the zener diode 510 will conduct current in the opposite direction. This operation diverts current away from the optocoupler 505.

The voltage supply output VS of GFCI IC 350 provides a voltage to resistor 515, which is connected to pin 4 of opto-coupler 505. The current flowing through resistor 515 and

pins

4 and 3 of opto-coupler 505 is operable to trigger or activate the gates of SCR361 and SCR369 to an on condition or state. However, resistor 515 is electrically connected to capacitors 520 and 525 through opto-coupler 505 to create a resistor-capacitor ("RC") circuit 530. The RC time delay introduced by RC circuit 530 causes the gate delay of

SCRs

361 and 369 to be triggered or activated to an on state and delays tripping the device for an amount of time. In some embodiments, one capacitor may be used in place of capacitors 520 and 525. In other embodiments, more than two capacitors may be used to provide the capacitors to the RC circuit 530.

Once the amount of delayed time from RC circuit 530 has elapsed, SCR361 and SCR369 are activated or triggered to an on state. When SCR361 is on, current flows from phase conductor 330 through secondary coil 363 of dual coil solenoid 362, fuse 365, diode 367, and SCR 361. Additionally, when SCR369 is turned on, current flows from phase conductor 330 through primary coil 364 of dual coil solenoid 362, fuse 372, diode 374 and SCR 369. In some embodiments, only one of SCR361 and SCR369 is implemented in a delay circuit, and solenoid 362 includes one coil. The current flowing through the two

coils

363, 364 generates a magnetic field that moves the armature within the solenoid 362. When the solenoid armature moves, it unlatches a contact carrier (e.g., 106 in fig. 3), which is part of the interrupting device 315, and which drops under the natural bias of the

line conductors

330, 332, that is, away from the face conductors 338, 340 and load conductors 277, 278. The device is now said to "trip" due to a successful manual simulated fault test sequence, and the device will not deliver power to the load until it is reset. The time it takes for the switch 354 of the present invention to close until the device trips and current no longer flows from the phase conductor 330 to either of the face and load conductors and through the solenoid coils 363, 364 is so short that the

fuses

365, 372 remain unbroken.

The delay introduced by the RC circuit 530 delays the opening of the

conductors

330, 332 so that when less power (e.g., less than 100% VCC) is present to provide through the contacts of the interrupting device 315, the conductors open. For example, the delay in the start of the SCR output of the GFCI IC 350 introduced by capacitor 307 (described below) causes the SCR360 to trigger at about the peak power point of the input power on conductors 330, 332 (i.e., at about 90 ° within the AC waveform). When this occurs, the load at the interrupting device 315 may generate a large amount of plasma when the contacts are open, which may burn the contacts of the interrupting device 315. The RC circuit 530 is operable to delay the opening of the contacts of the interrupting device 315 until less power is provided through the interrupting device 315. In some embodiments, the RC circuit introduces a delay that reduces the power being provided through the interrupting device 315 to between about 25% and about 100% VCC when the contacts are open. In some embodiments, the interrupt device 315 is triggered when between approximately 50% and 65% VCC is being provided through the interrupt device 315. This reduced power through the interruption device 315 reduces the amount of plasma generated when the contacts are opened. Thus, contacts containing reduced silver may be used (i.e., to reduce cost), and the lifetime of the contacts may be increased (e.g., by reducing plasma ignition of the contacts).

Fig. 5 illustrates an oscilloscope trace 600 that shows how delaying the opening of the contacts of the interrupting device 315 reduces the power through the interrupting device 315 when the contacts are open. Fig. 5 illustrates the beginning of the positive half cycle of the AC waveform used to trip the device at 605. In this illustrative example, resistor 515 has a value of 53 kilo-ohms and capacitors 520, 525 have a value of 0.23 μ F. The microcontroller 301 uses the voltage at the port GP3 of the microcontroller 301 to determine whether the GFCI IC device 350 is being supplied with power and whether the device is tripped or in a reset condition. At 610 in fig. 5, the leading edge of the voltage at port GP3 is illustrated. At 615, a delay in the start of the SCR output of the GFCI IC 350 introduced by the capacitor 307 causes the SCR360 to be triggered. As illustrated in fig. 5, the SCR360 triggers at about peak power (about 100% VCC). However, RC circuit 530 prevents SCR361 and SCR369 from being triggered for approximately 1mS until 620. After triggering SCR361 and SCR369, the mechanical delay in opening of the contacts of interrupting device 315 (described above) delays the opening of the contacts until 625. A total delay of 4.86mS from the leading edge of the voltage at GP3 is achieved (610) until the contacts of the interrupting device actually open (625). The voltage of the positive half cycle of the AC waveform is 120V (85 volts rms) or about 68% VCC.

The embodiment of the present invention illustrated graphically in fig. 5 is provided for illustrative purposes, and other values of resistor 515 and capacitors 520 and 525 may be used that will increase or decrease the RC time delay introduced by RC circuit 530. The RC delay from the RC circuit 530 may increase (e.g., greater than approximately l mS), but sufficient power must be present at the solenoid 362 to open the contacts of the interrupting device 315. The minimum power required to open the contacts of the interrupting device 315 occurs at approximately 25% VCC of the illustrated AC waveform.

Manual testing via reset operation

Referring again to fig. 4, closing reset switch 300, for example, by pressing reset button 24 (fig. 1) also initiates the test operation. Specifically, when the reset switch 300 is closed, the voltage supply output VS of the GFCI IC 350 is electrically connected to the gate of the SCR360 through conductor 308, thus turning on the SCR 360. When the SCR360 turns on, current is drawn from the line conductor 330 through the diode 359 and the SCR360, and finally to ground. Similarly as previously discussed, when SCR360 is turned on by pressing the test button, turning on SCR360 by pressing the reset button also causes SCR361 and SCR369 to turn on after an RC time delay and current flows through

solenoid coils

363, 364. The current flowing through the

coils

363, 364 of the solenoid 362 generates a magnetic field at the solenoid and the armature within the solenoid is actuated and moves. Under typical (e.g., non-test) conditions, the armature is actuated in this manner to trip the device, such as when an actual fault occurs.

However, when the reset switch 300 is closed, the device may already be in a tripped condition, i.e., the contacts of the line, plane and load conductors are electrically isolated. That is, after the device has tripped, the reset button is typically pressed to re-latch the contact carrier and bring the line, face and load contacts back into electrical contact. If the armature of the solenoid 362 fails to activate when the reset button is pressed, and after the reset button is released, the reset mechanism including the contact carrier fails to engage the reset plunger when it returns, the device will not reset. Thus, if, for example, a device has not been wired to an AC line, or it has been miswired, that is, the device has been wired with AC electrical connections that are not connected to the

line terminals

326, 328, no power is applied to the GFCI IC 350. If no power is applied to the GFCI IC 350, the gate of the SCR360 cannot be driven through the SCR output of the GFCI IC 350 or when the rest button is pressed. Under this condition, the device will not be able to reset. A miswiring condition is prevented according to a wiring device consistent with an embodiment of the present invention by ensuring that the device is shipped to a customer in a tripped condition. Since the device cannot be reset until AC power is properly applied to the line terminals, a miswiring condition is prevented.

Automatic monitoring circuit

With continued reference to the exemplary circuit schematic shown in fig. 4, the auto-monitoring circuit 370 includes a programmable device 301. Programmable device 301 may be any suitable programmable device, such as a microprocessor or microcontroller, which may be programmed to implement an automatic monitoring routine, as explained in detail below. For example, according to the embodiment shown in FIG. 4, programmable device 301 is composed of ATMEL from the ATtiny 10 family^TMA microcontroller. The programmable device may also be implemented by a microchip microcontroller (e.g., PIC10F 204/206).

According to one exemplary automatic monitoring or automatic self-test routine according to the embodiment shown in FIG. 4, the microcontroller 301 initiates the automatic monitoring routine approximately every three (3) seconds by setting a software automatic monitoring test flag. The auto-monitoring test flag initiates an auto-monitoring routine within the circuit interrupting device and confirms that the device is operating properly, or in some cases, that the circuit interrupting device has reached its end of life ("EOL"). When the auto-monitoring routine runs with a positive (i.e., successful) result, the auto-monitoring circuit enters a sleep state until the microcontroller 301 again sets the test flag and initiates another auto-monitoring routine.

If the auto-monitoring routine is running with a negative result, e.g., it cannot be determined that the circuit interrupting device is functioning properly, or that it is actually not operating properly, the fault counter is incremented and the microcontroller 301 initiates another auto-monitoring routine when instructed by a software program stored in memory within the device. In addition to the increment of the failure count, a temporary indication of failure is also provided. For example, according to an embodiment of the present invention, when such a fault occurs, the I/O port GP0 of the microcontroller 301 is controlled to be an output and the light emitting diode ("LED") 376 is controlled to flash, e.g., one or more times, to indicate the fault to a user. If the fault counter reaches a predetermined value, i.e., the auto-monitoring routine runs with a negative result a certain number of times, which is stored and implemented in software, the auto-monitoring routine calls an end of life ("EOL") sequence. The EOL sequence includes one or more of the following functions: (a) indicating that EOL has been reached, for example by constantly flashing or illuminating an indicator light and/or producing an audible sound, (b) attempting to trip the device, (c) preventing an attempt to reset the device, (d) storing an EOL event on a non-volatile memory, for example in the presence of a power failure, and (e) clearing an EOL condition when the device is powered down.

According to this embodiment, when the auto-monitoring software determines that the auto-monitoring routine is running, i.e., based on the car monitor timer, the stimulus signal 302 is turned on at the I/O port GP1 of the microcontroller 301. When the stimulus signal is turned on, current flows through resistor 303 and a voltage builds at the base of transistor 304, turning the transistor on. When transistor 304 is turned on, current flows from dc voltage supply 378 through resistor 305, which is, for example, a 3 kilo-ohm resistor, and on through electrical conductor 356 and transistor 304 to ground. With respect to dc voltage source 378, the value of this voltage source is designed to be between 4.1 volts dc to 4.5 volts dc, according to embodiments of the invention, but the value of this voltage supply can be any other suitable value as long as the value used is sufficient to take into account the other circuit functionality described below.

According to this exemplary embodiment, electrical conductors 356 are wires, but may also be conductive traces on a printed circuit board. Conductor 356 is connected to resistor 305 at one end, passes through sensing transformer 334, and wraps around the core of the transformer approximately ten (10) times and is connected to the collector of transistor 304 at its other end. Thus, when the software auto-monitoring test flag is set in microcontroller 301 and transistor 304 is turned on, current flows through conductor 356, which comprises a separate conductor from phase conductor 330 and neutral conductor 332, and current also passes through the center of sensing transformer 334.

If the circuit interrupting device according to an embodiment of the present invention is functioning properly, a magnetic flux is generated at the sensing transformer 334 as current flows through the conductor 356 and through the sensing transformer. The flux produces a signal on conductor 333 that is detected by detection circuit 352, which includes GFCI IC apparatus 350. According to this embodiment, when device 350 detects the flux generated at sensing transformer 334, the voltage level increases at one of the I/O ports of device 350, such as at the output port labeled CAP in fig. 4, increasing the voltage on conductor 306.

According to this embodiment, capacitor 307 is connected between the CAPI/O port of microcontroller 301 and ground. As is known in the art, attaching a capacitor right between the CAP output of the 4141GFCI IC device and ground causes the SCR trigger signal (SCR _ OUT) output from the GFCI IC device 350 to be delayed for a predetermined period of time. The amount of time to delay the trigger signal is typically determined by the value of the capacitor. However, according to embodiments of the present invention, the capacitor 307 is not connected exactly in the middle of the CAP output and ground. Instead, the capacitor 307 is also connected to the ADC I/O port GP0 of the microcontroller 301 via a circuit path that includes a diode 310 in series with a resistor 311 (e.g., 3 megaohms), which completes a voltage divider circuit with a resistor 312 (e.g., 1.5 megaohms). This additional circuit connected to the capacitor at the CAP output of the GFCI IC device 350 draws current from the delay capacitor.

By measuring the value of the signal at the ADC I/O port (GP0) and confirming that it is above a certain level, it can be determined whether the detection circuit 352 properly detected the self-test fault signal generated on conductor 356, and can further confirm whether the GFCI IC apparatus 350 is capable of generating the proper SCR trigger signal. Also, to avoid tripping the device during self-test auto-monitoring faults, the voltage at capacitor 307 is measured and proper self-test fault detection is confirmed before the drive signal is output at SCR _ OUT of the GFCI IC device 350.

If the current drawn on capacitor 307 is too high, the GFCI IC apparatus 350 may not operate properly. For example, if as little as 3-4 milliamps of current is drawn from the capacitor 307, then the grounded-neutral condition that is also intended to be detected by the GFCI IC device 350 cannot be accurately detected, such as per UL requirements, because the SCR trigger signal (SCR _ OUT) will not activate for the requisite amount of time. According to an embodiment of the present invention, the ADC I/O port GP0 of microcontroller 301 draws less than about 1.3 milliamps, or about 5% of the delay current specified for the GFCI IC apparatus 350. This small current drawn from the capacitor 307 has no effect on the device's ability to properly detect a true ground fault and/or a true grounded-neutral fault.

According to this embodiment, a current of about 50 nanoamps is drawn from the capacitor 307. The parallel resistors 311 and 312 connected to the ADCI/O port GP0 of the microcontroller 301 produce a drain of 4.5 megaohms that limits the current drawn from the capacitor 307 to a maximum of 1.0 microamperes. The GFCI IC apparatus 350 uses about 40 milliamps of current to generate the SCR trigger, but the microcontroller 301 only needs about 50 nanoamps to read the SCR trigger signal from the capacitor 307 before outputting the SCR trigger signal from SCR _ OUT. Thus, by selecting the proper value for capacitor 307, in combination with the proper value selection of resistors 311 and 312 and diode 310, it is possible to maintain the correct delay for the SCR trigger signal (SCR _ OUT) from the GFCI IC device 350 and measure the signal at the ADC input (GP0) using the ADC in the microcontroller 301 to determine if the test signal on conductor 356 has been properly detected by the detection circuit 352.

It should also be noted that in the embodiment shown in FIG. 4, LED376 is also connected to the ADC I/O port (GP0) of microcontroller 301. Thus, the drain on capacitor 307 is not affected regardless of whether LED376 is conducting, as well as the delay of the SCR trigger signal and the ability of microcontroller 301 to properly measure the signal output from the CAP I/O port of GFCI IC device 350. Thus, with respect to the circuit shown in fig. 4, the LED376 is selected so that it does not turn on and begins conducting during the time that the microcontroller 301 is measuring a signal from the CAP output of the GFCI IC apparatus 350. For example, LED376 is selected such that its turn-on voltage is about 1.64 volts or higher than 1.64 volts, which can be measured at I/O port GP0 in accordance with the circuit shown in FIG. 4. In addition, to prevent any signal from being added to the capacitor 307 when the LED376 is being driven, a diode 310 is provided.

According to this embodiment, the circuit path including the diode 310 and the voltage divider 311, 312 is connected to an I/O port GP0 of the microcontroller 301, which serves as an input to an analog-to-digital converter ("ADC") within the microcontroller 301. The ADC of the microcontroller 301 measures the increased voltage established by the charging action of the capacitor 307. When a predetermined voltage level is reached, microcontroller 301 turns off auto-monitoring stimulus signal 302, which in turn turns off transistor 304, thereby stopping the current on conductor 356 and thus stopping the flux generated at sensing transformer 334. When this occurs, the microcontroller 301 determines that the qualified auto-monitoring event has passed successfully, and decrements the auto-monitoring failure counter if the current count is greater than zero.

In other words, according to this embodiment, the microcontroller 301 repeats the automatic monitoring routine according to a predetermined schedule. The automatic monitoring routine is run as needed from every few seconds to any interval of every month, etc., based on a software program stored in a memory within the microcontroller 301. When the routine is initiated, the flux generated at the sensing transformer 334 occurs in a manner similar to the manner in which it would be generated if an actual ground fault had occurred or if a simulated ground fault had been generated manually, for example by pressing a test button as described above.

However, there is a difference between the automatic monitoring (self-test) fault generated by the automatic monitoring routine and the actual ground fault or simulated fault generated by pressing the test button. When an actual or simulated ground fault occurs, a difference in the currents flowing in the phase and

neutral conductors

330 and 332, respectively, should be created. That is, the current on conductor 330 should be different than the current on conductor 332. This differential current flowing through the sense transformer 334 is detected by the GFCI IC apparatus 350, which drives a signal on its SCR _ OUT I/O port to activate and turn on the gate of the SCR 360. When the SCR360 turns on, current is drawn through the

coils

363, 364 which causes the interrupting device 315 to trip, causing the contact carrier to descend, which in turn causes the line, face and load contacts to separate from each other. Thus, current is prevented from flowing through the phase and

neutral conductors

330, 332 to the phase and

neutral face terminals

342, 344, and the phase and

neutral load terminals

346, 348, respectively.

In contrast, when an automatic monitoring routine is executed in accordance with the present invention, no differential current is generated on the phase and

neutral conductors

330, 332 and the interrupting device 315 is not tripped. Instead, during the automatic monitoring routine, the flux generated at the sensing transformer 334 is a result of current flowing through the conductor 356, which is electrically isolated from the phase and

neutral conductors

330, 332. The current generated on conductor 356 exists for only a short period of time, such as less than the delay time established by capacitor 307 discussed previously.

If the voltage established at the input to the ADC input (GP0) of microcontroller 301 reaches the programmed threshold within this predetermined time period during the auto-monitoring routine, then it is determined that the detection circuit 352 successfully detected the current flowing through the core of the sense transformer 334 and the auto-monitoring event is deemed to have passed. Thus, the microcontroller 301 determines that the detection circuit 352 containing the GFCI IC apparatus 350 is operating properly. Because the current flowing through the sensing transformer 334 during the auto-monitoring routine is designed to be substantially similar in magnitude to the differential current (e.g., 4-6 milliamps) flowing through the transformer at the analog ground fault, the determination detection circuit 352 will be able to detect the actual ground fault and provide the appropriate drive signal to the SCR360 to trip the interrupter 315.

Alternatively, the auto-monitoring circuit 370 may determine that the auto-monitoring routine failed. For example, if the time it takes for the voltage at the ADC input at the GP0 of the microcontroller 301 to reach a given voltage during the auto-monitoring routine is longer than a predetermined period of time, then the auto-monitoring event is determined to have failed. If this occurs, the automated monitoring failure score is incremented and the failure is indicated visually or audibly. According to one embodiment, when an auto-monitoring event failure occurs, the ADC port (GP0) of microcontroller 301 is converted to an output port and a voltage is placed on conductor 309 via I/O port GP0, which the microcontroller first converts to an output port GP 0. This voltage at GP0 creates a current on conductor 309, which flows through indicator LED376 and resistor 380 to ground. The ADC I/O port (GP0) of the microcontroller 301 is then switched back to the input port and is kept ready for the next scheduled automatic monitoring event to occur.

According to this embodiment, indicator LED376 only illuminates the time period when the I/O port is switched to output and an output voltage is produced at that port when an automatic monitoring event failure occurs, otherwise LED376 remains dark or unlit. Thus, if an automatic monitoring routine is run, for example, every three (3) seconds, and event failures occur only once or sporadically, the event may not be noticed by the user. On the other hand, if the failure occurs periodically, as would occur if one or more of the components for the automatic monitoring routine were permanently disabled, the microcontroller 301 repeatedly turns the indicator LED 37610 on for milliseconds and turns it off for 100 milliseconds, drawing attention to the device and informing the user that the critical functionality of the device has been compromised. Conditions that cause the automatic monitoring routine to fail include one or more of: open differential transformer, closed differential transformer, no power to the GFCI IC, open solenoid, SCR trigger output of the GFCI IC is continuously high and SCR output of the GFCI IC is continuously low.

According to a further embodiment, if the automated monitoring failure score reaches a predetermined limit, such as seven (7) failures within one (1) minute, the microcontroller 301 determines that the device is no longer safe and has reached its end of life (EOL). If this occurs, a visual indicator is activated to alert the user that the circuit interrupting device has reached the end of its useful life. For example, when this EOL state is determined, the ADC I/O port (GP0) of microcontroller 301 is converted to an output port, similar to when a single fault is recorded as described above, and a signal is periodically placed on conductor 309 via GP0, even though LED376 blinks at a rate of, for example, 10 milliseconds on and 100 milliseconds off, or is continuously placed on conductor 309 to permanently illuminate LED 376. At this time, the automatic monitoring routine is also stopped.

In addition to flashing or continuously illuminating the LED376, according to another embodiment, an optional audible alarm circuit 382 on a printed circuit board ("PCB") 390 is activated when EOL is determined. In this case, the current through the LED376 establishes a voltage on the gate of the SCR 384 such that the SCR 384 turns on continuously or intermittently according to the output signal from the GP0 of the microcontroller 301. When SCR 384 is turned on, current is drawn from phase conductor 330 to activate audible alarm 386 (e.g., a buzzer), which provides an additional notification to the user of the device that the device has reached the end of its useful life (i.e., EOL). For example, with respect to embodiments of the present invention, audible alarm circuit 382 includes a parallel RC circuit that includes resistor 387 and capacitor 388. When current is drawn from phase conductor 330, capacitor 388 charges and discharges at a rate controlled by the value of resistor 387, causing buzzer 386 to issue the desired glitch alarm.

Another aspect of this embodiment includes a dimmable LED circuit 396. The circuit 396 includes a transistor 398;

LEDs

400, 402; a light sensor 404 (e.g., a photocell) and resistors 406-408. When ambient light, such as the amount of light near the circuit interrupting device according to embodiments of the present invention, is rising, the light sensor 404 reacts to the ambient light level to apply an increasing impedance to the base of the transistor 398 to cause the LED to dim as the ambient light increases. Alternatively, when the ambient light decreases, e.g., as night curtains begin to fall, the current flowing through sensor 404 increases accordingly. As the ambient light level decreases,

LEDs

400 and 402 are illuminated more and more brightly, providing a controlled light level in the vicinity of the device.

Another embodiment of the invention shown in fig. 4 includes a mechanism for providing data to microcontroller 301 regarding whether the device is tripped or in a reset condition. As shown in fig. 4, opto-coupler 392 is connected between phase and neutral load conductors 277, 278 and the I/O port (GP3) of microcontroller 301. The microcontroller 301 uses the value of the signal (voltage) at port GP3 to determine whether the GFCI IC apparatus 350 is supplied with power and whether the apparatus is tripped or in a reset condition. When the GFCI IC apparatus 350 is powered, for example, via its voltage input port (LINE), which occurs when the AC is electrically connected to the

LINE terminals

326, 328, a voltage is generated at the output port (VS). This voltage is reduced across a zener diode 394, which is provided to maintain the voltage supplied to the microcontroller within acceptable levels. Diodes 366, 368 connected between the phase conductor and the power supply input port (LINE) of the GFCI IC 350 ensure that the voltage level supplied to the GFCI IC and VS outputs remains below about 30 volts. The reduced voltage signal on the zener diode 394 is connected to the input port GP3 of the microcontroller 301. If the microcontroller 301 does not measure a voltage at the GP3, it is determined that the GFCI IC device 350 is not supplying power and an EOL is declared.

Alternatively, if the microcontroller 301 measures a voltage at the GP3, then based on the value of the voltage, it is determined whether the device is tripped or in a reset state. For example, according to the circuit in fig. 4, if the voltage at GP3 is measured to be between 3.2 volts and 4.0 volts, such as between 76% of VCC and 100% of VCC, then it is determined that there is no power at the face (342, 344) and load (346, 348) contacts, and thus the device is in a tripped state. If the voltage at the GP3 is between 2.4 and 2.9 volts, such as between 51% of VCC and 74% of VCC, then it is determined that power is present at the face and load contacts and the device is in a reset state.

According to another embodiment, when EOL is determined, the microcontroller 301 trips the interrupting device 315 in one or both of the following ways: (a) by maintaining the stimulation signal on the third conductor 356 into the initiation half-cycle of the AC wave, and/or (b) by generating a voltage at the EOL port (GP2) of the microcontroller 301. When EOL has been declared, the microcontroller 301 generates a voltage at the EOL port (GP2), for example, because the automatic monitoring routine failed the necessary number of times and/or no power is being supplied from the supply voltage output (VS) of the GFCI IC apparatus 350. Optionally, the microcontroller 301 may also use the value of the input signal at GP3, as described above, to further determine whether the device is already in a tripped state. For example, if the microcontroller 301 determines that the device is tripped, e.g., the load and face contacts are not electrically connected to the line contacts, the microcontroller 301 may determine that it is not necessary to drive the SCR369 and/or the SCR361 in an attempt to open the contacts and trip the device, and thus not drive the SCR369 and the SCR361 via the GP 2.

The voltage at GP2 directly drives the gates of SCR369 and/or SCR361 to turn SCR369 and/or SCR361 on, thus enabling it to conduct current and activate solenoid 362. More specifically, when SCR369 and/or SCR361 are turned on, current is drawn through coil 364 of dual coil solenoid 362. For example, the dual coil solenoid 362 includes: an inner primary coil 364 comprising an 800 turn, 18 ohm, 35AWG coil; and an outer secondary coil 363 comprising a 950 turn, 16.9 ohm, 33AWG coil. Further details of the construction and functionality of the dual coils 362 may be found in U.S. patent application No. 13/422,797, which is assigned to the same assignee as the present application and is incorporated herein by reference in its entirety.

As described above, when it is determined via the auto-monitoring routine that the detection circuit 352 has not successfully detected a ground fault, e.g., it has not detected flux due to current flowing in the conductor 356, or has not otherwise generated a drive signal at the SCR _ OUT output port of the GFCI IC device 350 to drive the gate of the SCR360 immediately following such detection, the microcontroller 301 determines the EOL and attempts to trip the interrupting device 315 by the method described above. Specifically, the microcontroller 301 attempts to directly trip the primary coil 364 directly through the backup path GP2 to the

SCRs

369 and 361. However, there is at least one difference between the signal on conductor 356 when the auto-monitoring routine is not operating normally and the signal on conductor 356 that is generated when EOL is determined. That is, under EOL conditions, the GP2 energizes both the SCR361 and the SCR369 to be triggered and the coil 362 and the coil 363 to function, thereby activating the

solenoids

362 and 369 to trip the interrupting device 315.

The power on indicator circuit 321 will turn off if the interrupting device 315 turns off, or if the interrupting device 315 has been turned off otherwise. For example, in the embodiment shown in fig. 4, power on indicator circuit 321 includes an LED 322 in series with a resistor 323 and a diode 324. The cathode of LED 322 is connected to neutral load conductor 278 and the anode of diode 324 is connected to phase load conductor 277. Thus, when power is available at the load conductor, that is, the device is powered and in a reset state, current is drawn through the energized circuit at each alternating half cycle of AC power, thereby illuminating the LEDs 322. On the other hand, if power is not available at the load conductors 277, 278, for example because the interrupting device 315 is open or tripped, or the device is reset, but power is not being applied, the LED 322 will be dark or not lit.

Additional embodiments and aspects thereof relating to automated monitoring functionality consistent with the present invention are provided below, as well as further discussion of some of the aspects that have been described.

The sinusoidal AC waveform discussed herein is connected to the phase and

neutral line terminals

326, 328 when the self-testing GFCI device is properly installed. According to one embodiment, the AC waveform is a 60Hz signal containing two half cycles, a positive 8.333 ms half cycle and a negative 8.333 ms half cycle. The so-called "activation" half cycle refers to a particular half cycle, positive or negative, during which a gate trigger signal to SCR360 causes the respective gates of SCR361 and SCR369 to be driven, and the corresponding respective solenoid coils 363, 364 conduct current, thus "activating" solenoid 362 and causing the armature of the solenoid to displace. The "inactive" half cycle refers to the alternate half cycle of the AC waveform, i.e., negative or positive, during which current does not flow through the SCR or its corresponding solenoid coil, regardless of whether the SCR gate is triggered. According to an embodiment of the invention, whether a positive or negative half cycle is an activation half cycle is determined by a diode or some other switching device placed in series with the respective solenoid coil. For example, in fig. 4,

diodes

359, 374, and 367 are configured so that the positive half-cycles are "start-up" half-cycles relative to

SCRs

360, 369, and 361, respectively.

According to another embodiment of a circuit interrupting device consistent with the present invention, the microcontroller 301 optionally monitors the AC power input to the device. For example, the 60Hz AC input electrically connected to the phase and

neutral line terminals

326, 328 is monitored.

More specifically, a complete 60Hz AC cycle takes approximately 16.333 milliseconds to complete. Thus, to monitor and confirm the receipt and stabilization of the AC waveform, a timer/counter within microcontroller 301 is implemented. For example, within three (3) second automatic monitoring windows, the 60Hz input signal is sampled once every millisecond to identify the leading edge, i.e., where the signal changes from a negative value to a positive value. When a leading edge is detected, a flag is set in the software and the count is incremented. When the three (3) second test periods end, the count result is divided by 180 to determine whether the frequency is within the specified range. For example, if the frequency settles at 60Hz, the result of dividing by 180 will be 1.0, since there are 180 positive edges and 180 cycles within three (3) seconds worth of the 60Hz signal. If it is determined that the frequency is not within a given range, e.g., 50Hz to 70Hz, the automatic monitoring self-test fault test stops, but the monitoring of the GP3 continues. Thus, when the circuit interrupting device of the present invention is connected to a variable power source, such as a portable generator, and the power source exhibits a lower frequency at start-up and requires a stabilization period before an optimum frequency (e.g., 60Hz) is achieved, premature or false power failure determinations are avoided.

If the frequency is not stable at the optimum frequency, or at least not within an acceptable range, then the start of the automatic monitoring routine is delayed until the frequency stabilizes. If the frequency does not achieve the optimal frequency, or a frequency within an acceptable range, within a predetermined time, the failure score is incremented. Similar to the failure score discussed previously with respect to the automatic monitoring routine, if the score reaches a given threshold, the microcontroller 301 declares EOL.

As described above, according to at least one exemplary embodiment, the programmable device 301 is implemented in a microcontroller. Because some microcontrollers include non-volatile memory, such as for storing various data in the event of a power interruption, etc., according to another embodiment, upon power-up of the device, all events, timers, scores and/or states within the non-volatile memory are cleared. Thus, if a failure score or other condition is generated by improper device installation, insufficient or improper power, or some other non-severe condition relative to the circuit interrupting device itself, the failure score resets at power-up when the score increment event may no longer exist. Another way to avoid this potential problem in accordance with the present invention is to utilize programmable devices that do not include non-volatile memory.

While various embodiments have been chosen to illustrate the invention, it will be understood by those skilled in the art that other modifications can be made without departing from the scope of the invention as defined in the appended claims.

Claims

1. A circuit interrupting device, comprising:

one or more line conductors for electrical connection to an external power supply;

one or more load conductors for electrical connection to an external load;

an interrupting device connected to the line conductor and the load conductor, the interrupting device disconnecting the line conductor from the load conductor when the circuit interrupting device is in a tripped condition and electrically connecting the line conductor to the load conductor when the circuit interrupting device is not in the tripped condition;

a delay circuit that delays the disconnection of the line conductor from the load conductor, the delay circuit including a first switch, a resistor, a first capacitor, a second switch, a third switch, and a solid state relay; and

a fault detection circuit that detects a fault condition in the circuit interrupting device, the fault detection circuit generating a fault detection signal when the fault condition is detected and providing the fault detection signal to the first switch to trigger the first switch,

wherein the delay circuit delays the triggering of the second switch and the third switch by an amount of time and, after the amount of time has elapsed, triggers the second switch and the third switch to place the circuit interrupting device in the tripped condition.

2. The circuit interrupting device recited in claim 1 wherein said fault detection signal is provided to said first switch to trigger said first switch into a conducting state, said first switch triggering said solid state relay into a conducting state and electrically connecting said resistor to said first capacitor and said second capacitor, said resistor, said first capacitor and said second capacitor forming a resistor-capacitor "RC" circuit having an RC time delay associated with said amount of time said second switch and said third switch have been delayed from being triggered.

3. The circuit interrupting device recited in claim 2 wherein said second switch and said third switch are connected to a solenoid that causes said interrupting device to place said circuit interrupting device in said tripped condition.

4. The circuit interrupting device recited in claim 1 wherein said first switch is a first silicon controlled rectifier, said second switch is a second silicon controlled rectifier, said third switch is a third silicon controlled rectifier, and said solid state relay is a photo coupler.

5. The circuit interruption device of claim 4, wherein the fault detection signal is provided to a gate of the first silicon controlled rectifier to trigger the first silicon controlled rectifier into a conductive state, the first silicon controlled rectifier to trigger the opto-coupler into a conductive state, and the resistor is electrically connected to the first capacitor and the second capacitor, the resistor, the first capacitor, and the second capacitor forming a resistive-capacitive "RC" circuit having an RC time delay associated with the amount of time that the second silicon controlled rectifier and the third silicon controlled rectifier have been delayed from being triggered.

6. The circuit interrupting device recited in claim 5 wherein said second silicon controlled rectifier and said third silicon controlled rectifier are connected to a solenoid that causes said interrupting device to place said circuit interrupting device in said tripped condition.

7. The circuit interrupting device recited in claim 1 wherein said fault detection circuit detects a net current flowing from said line conductor to said load conductor and generates said fault detection signal when said net current exceeds a predetermined threshold.

8. The circuit interrupting device recited in claim 7 wherein said fault detection circuit includes a sensing transformer through which said line conductor is disposed.

9. The circuit interruption device of claim 1, wherein the delay circuit further comprises a resistor-capacitor "RC" circuit having an RC time constant associated with the amount of time the second switch and the third switch are delayed from being triggered.

10. A wiring device, comprising:

an interrupter that, when activated, places or maintains the wiring device in a tripped state to prevent current from flowing from a line side of the wiring device to a load side of the wiring device;

a fault detection circuit configured to detect one or more fault conditions in the wiring device and generate a fault detection signal when the one or more fault conditions meet a predetermined criterion;

a solenoid operable to activate the interrupter when conducting current; and

a delay circuit including one or more switches electrically connected to the solenoid, wherein the solenoid conducts current when one or more of the one or more switches are activated, the delay circuit delays the activation of the one or more switches for an amount of time after the generation of the fault detection signal, and activates the one or more of the one or more switches after the amount of time has elapsed to place the wiring device in the tripped state,

wherein the delay circuit includes a first switch, a resistor, a first capacitor, a second switch, a third switch, and a solid state relay.

11. The wiring device recited in claim 10 wherein said fault detection signal is provided to said first switch to trigger said first switch into a conductive state, said first switch triggering said solid state relay into a conductive state and electrically connecting said resistor to said first capacitor and said second capacitor, said resistor, said first capacitor and said second capacitor forming a resistor-capacitor "RC" circuit having an RC time delay associated with said amount of time said second switch and said third switch have been delayed from being triggered.

12. The wiring device recited in claim 11 wherein said second switch and said third switch are electrically connected to said solenoid.

13. The wiring device according to claim 10, wherein the first switch is a first silicon controlled rectifier, the second switch is a second silicon controlled rectifier, the third switch is a third silicon controlled rectifier, and the solid state relay is a photocoupler.

14. The wiring device recited in claim 13 wherein said fault detection signal is provided to a gate of said first silicon controlled rectifier to trigger said first silicon controlled rectifier into a conductive state, said first silicon controlled rectifier triggering said opto-coupler into a conductive state and electrically connecting said resistor to said first capacitor and said second capacitor, said resistor, said first capacitor and said second capacitor forming a resistor-capacitor "RC" circuit having an RC time delay associated with said amount of time said second silicon controlled rectifier and said third silicon controlled rectifier have been delayed from being triggered.

15. The wiring device recited in claim 14 wherein said second silicon controlled rectifier and said third silicon controlled rectifier are electrically connected to said solenoid.

16. The wiring device recited in claim 10 wherein said fault detection circuit detects a net current flowing from the line side of the wiring device to the load side of the wiring device and generates said fault detection signal when said net current exceeds a predetermined threshold for a predetermined amount of time.

17. The wiring device recited in claim 16 wherein said fault detection circuit includes a sensing transformer through which said line conductor is disposed.

18. The wiring device recited in claim 10 wherein said delay circuit includes a resistance-capacitance "RC" circuit having an RC time constant associated with said amount of time said one or more of said one or more switches has been delayed from being triggered.