CN108599800A - Internet of Things radio circuit and terminal based on PIFA antennas and lumped parameter matching type - Google Patents
Internet of Things radio circuit and terminal based on PIFA antennas and lumped parameter matching type Download PDFInfo
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- CN108599800A CN108599800A CN201810292621.XA CN201810292621A CN108599800A CN 108599800 A CN108599800 A CN 108599800A CN 201810292621 A CN201810292621 A CN 201810292621A CN 108599800 A CN108599800 A CN 108599800A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/005—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges
- H04B1/0053—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges with common antenna for more than one band
- H04B1/006—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges with common antenna for more than one band using switches for selecting the desired band
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
- H04B1/401—Circuits for selecting or indicating operating mode
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- Computer Networks & Wireless Communication (AREA)
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Abstract
The present invention relates to a kind of Internet of Things radio circuit and terminal based on PIFA antennas and lumped parameter matching type, embodiment disclose a kind of signal processing circuit, are applied to internet-of-things terminal, which includes：PIFA antennas, filter, switching circuit, the first filter network, low noise amplifier circuit, the second filter network and mixting circuit；PIFA antennas, filter, switching circuit, the first filter network, low noise amplifier circuit, the second filter network and mixting circuit are sequentially connected；PIFA antennas include radiation patch, feed element and the first capacitance, and the first capacitance is between radiation patch and feed element, the input impedance for adjusting PIFA antennas；Low noise amplifier circuit includes the first optimization circuit and the second optimization circuit, first optimization circuit is used to adjust the stability of low noise amplifier circuit, with this, the performance that antenna and low noise amplifier circuit can be improved to a certain extent, so as to improve the processing capacity of the signal processing circuit docking collection of letters number to a certain extent.
Description
Technical field
The present invention relates to circuit structure technical fields more particularly to a kind of based on PIFA antennas and lumped parameter matching type
Internet of Things radio circuit and terminal.
Background technology
With the fast development of technology of Internet of things, the various terminals product of Internet of Things gradually spreads to daily life
In, the every aspect in life is applied, is brought great convenience to daily life.While Internet of Things is quickly popularized,
Since internet-of-things terminal products application is in complex environment so that communication is also faced with huge challenge between each other for it,
In internet-of-things terminal, the performance of antenna and frequency mixer has a very big impact the design of radio circuit, if its design is unreasonable,
The performance of antenna and frequency mixer can be caused poor, be unfavorable for the reception and processing of radiofrequency signal.
Invention content
An embodiment of the present invention provides a kind of Internet of Things radio circuit based on PIFA antennas and lumped parameter matching type and
Terminal improves the performance of antenna and low noise amplifier circuit to a certain extent, so as to radio circuit to a certain extent
The processing capacity of the docking collection of letters number.
The first aspect of the embodiment of the present invention provides a kind of signal processing circuit, is applied to internet-of-things terminal, the circuit
Including：
PIFA antennas, filter, switching circuit, the first filter network, low noise amplifier circuit, the second filter network and mixed
Frequency circuit；
The output end of the PIFA antennas is connected with the input terminal of the filter, the output end of the filter and institute
The input terminal for stating switching circuit is connected, and the output end of the switching circuit is connected with the input terminal of first filter network
It connects, the output end of first filter network is connected with the input terminal of the low noise amplifier circuit, the low noise amplification
The output end of circuit is connected with the input terminal of second filter network, and the output end of second filter network is mixed with described
The input terminal of frequency circuit is connected；
The PIFA antennas include radiation patch, feed element and the first capacitance, and first capacitance is located at the radiation
Between patch and the feed element, the input impedance for adjusting the PIFA antennas；
The low noise amplifier circuit includes the first optimization circuit and the second optimization circuit, and the first optimization circuit is used for
The stability of the low noise amplifier circuit is adjusted, the second optimization circuit is used to adjust of the low noise amplifier circuit
With degree.
In conjunction with the embodiment of the present invention in a first aspect, in the first possible realization method of first aspect, described
One filter network includes：First filter part, second filter part, third filtering device, the 4th filtering device, the 5th filter
Part, the 6th filtering device, the 7th filtering device, the 8th filtering device, the 9th filtering device, the tenth filtering device, the 11st filter
Wave device and the 12nd filtering device；
The first end of the first filter part is connected with the first end of the second filter part, first filtering
The second end of device and the 4th filtering device, the 5th filtering device, the tenth filtering device, the 12nd filter
The second end of wave device is connected, the second end of the second filter part and the third filtering device, the 7th filtering
Device, the 8th filtering device first end be connected, the second end of the third filtering device and the 4th filter
The first end of part, the first end of the 5th filtering device, the first end of the 6th filtering device are connected, the 7th filter
The second end, the second end of the 9th filtering device, the tenth filter of the second end of wave device and the 6th filtering device
The first end of wave device is connected, the second end of the 8th filtering device and the first end of the 9th filtering device, described
The first end of 11st filtering device is connected, second end and the 12nd filtering device of the 11st filtering device
First end is connected.
In conjunction with the first aspect of the embodiment of the present invention and the first possible realization method of first aspect, in first aspect
Second of possible realization method in, it is described first optimization circuit includes：Second capacitance, third capacitance, the first inductance, second
Inductance, first resistor and the first MCU；
The output end of first inductance is connected with the input terminal of the input terminal of second inductance, second capacitance
It connects, the output end of second capacitance is connected with the second end of the output end of the third capacitance, the first resistor, described
The output end of second inductance is connected with the input terminal of the input terminal of the third capacitance, the first resistor, and the MCU is used for
Control the optimization degree of the first optimization circuit.
In conjunction with the first aspect of the embodiment of the present invention and the first possible realization method of first aspect, in first aspect
The third possible realization method in, it is described second optimization circuit includes：4th capacitance, third inductance, second resistance, third
Resistance and the 2nd MCU；
The first end of the second resistance is connected with the first end of the first end of the third inductance, the 4th capacitance
It connects, the second end of the second resistance is connected with the second end of the third inductance, the second end of the 3rd resistor, described
The second end of 4th capacitance is connected with the first end of the 3rd resistor, and the 2nd MCU is for controlling second optimization
The matching degree of circuit.
In conjunction with the embodiment of the present invention first aspect and above-mentioned first aspect the first to the third possible realization side
Any one of formula, in the 4th kind of possible realization method of first aspect, the mixting circuit includes：The first transistor,
Second transistor, third transistor, the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor, the 8th transistor,
4th inductance, the 5th capacitance, the 6th capacitance, the 7th capacitance, the 8th capacitance, the 4th resistance, the 5th resistance, the 6th resistance, the 7th
Resistance, the first power supply and second source；
The source electrode of the first transistor and the source electrode of the second transistor, be connected, the first transistor
Drain electrode be connected with the source electrode of the source electrode of the third transistor, the 4th transistor, the drain electrode of the third transistor and
The drain electrode of the first end, the 5th transistor of 4th inductance is connected, the grid of the third transistor and described the
The grid of six transistors is connected, the draining of the second end of the 4th inductance and the 7th transistor, the 5th capacitance
Second end, the second end of the 4th resistance, the first end of the 7th capacitance, the first end of the 7th resistance be connected
It connects, the second end ground connection of the 7th capacitance and the 7th resistance, source electrode and first power supply of the 7th transistor
Output end, the first end of the 5th capacitance, the first end of the 4th resistance be connected, the drain electrode of the second transistor
Be connected with the source electrode of the source electrode of the 5th transistor, the 6th transistor, the grid of the 5th transistor with it is described
The grid of 4th transistor is connected, the drain electrode of the 6th transistor and the draining of the 4th transistor, the described 8th brilliant
The drain electrode of body pipe is connected, the first end of the source electrode of the 8th transistor and the 6th capacitance, the 5th resistance the
One end, the second source output end be connected, the second end of the 6th capacitance and the second end of the 5th resistance, institute
The first end of the first end, the 8th capacitance of stating the 6th resistance is connected, and the of the 6th resistance and the 8th capacitance
Two ends are grounded.
It is described to open in conjunction with the embodiment of the present invention in a first aspect, in the 5th kind of possible realization method of first aspect
Powered-down road includes：2 road transmission circuits and 4 tunnel receiving circuits are supported to connect in the transmission circuit of 2 road per transmission circuit all the way
It receives and emits signal, reception signal is only supported per receiving circuit all the way in the receiving circuit of 4 tunnel.
In conjunction with the embodiment of the present invention first aspect and above-mentioned first aspect the first to the 5th kind of possible realization side
Any one of formula, in the 6th kind of possible realization method of first aspect, the circuit further includes protection circuit, the guarantor
Protection circuit for the circuit when the antenna is by predeterminated voltage for providing protection.
The second aspect of the embodiment of the present invention provides a kind of chip, which includes processor, power circuit and above-mentioned
The signal processing circuit for appointing any possible realization method of first aspect or first aspect to be provided.
The third aspect of the embodiment of the present invention provides a kind of circuit board, which includes modem, at signal
The chip of device and the offer of second aspect of the embodiment of the present invention is provided.
The fourth aspect of the embodiment of the present invention provides a kind of internet-of-things terminal, which includes shell and Ben Fa
The circuit board that the bright embodiment third aspect provides.
The embodiment of the present invention has the advantages that：
As can be seen that through the embodiment of the present invention, PIFA antennas include radiation patch, feed element and the first capacitance, the
One capacitance is between radiation patch and feed element, the input impedance for adjusting antenna and low noise amplifier circuit packet
Including the first optimization circuit and the second optimization circuit, the first optimization circuit is used to adjust the stability of low noise amplifier circuit, and second
Optimization circuit is used to adjust the matching degree of low noise amplifier circuit, with this, by being arranged between radiation patch and feed element
The capacitance of antenna feed impedance can be adjusted, the input impedance of antenna can be improved to a certain extent, put on the matching degree of antenna,
The first optimization circuit of setting and the second optimization circuit in low noise amplifier circuit, so as to promote low noise to a certain extent
The stability and matching degree of amplifying circuit, and then the performance of circuit entirety can be promoted to a certain extent, it is promoted to radiofrequency signal
Reception with processing performance.
Description of the drawings
Technical solution in order to illustrate the embodiments of the present invention more clearly, below will be to needed in embodiment description
Attached drawing is briefly described.
Fig. 1 is that an embodiment of the present invention provides a kind of structural schematic diagrams of signal processing circuit；
Fig. 2 is that an embodiment of the present invention provides a kind of structural schematic diagrams of PIFA antennas；
Fig. 3 is that an embodiment of the present invention provides a kind of structural schematic diagrams of PIFA antennas；
Fig. 4 is that an embodiment of the present invention provides a kind of structural schematic diagrams of first filter network；
Fig. 5 A are that an embodiment of the present invention provides a kind of structural schematic diagrams of low noise amplifier circuit；
Fig. 5 B are that an embodiment of the present invention provides a kind of structural schematic diagrams of first optimization circuit；
Fig. 6 is that an embodiment of the present invention provides a kind of structural schematic diagrams of second optimization circuit；
Fig. 7 is that an embodiment of the present invention provides a kind of structural schematic diagrams of possible mixting circuit；
Fig. 8 is that an embodiment of the present invention provides a kind of possible structural schematic diagrams of protection circuit；
Fig. 9 is that an embodiment of the present invention provides a kind of possible structural schematic diagrams of chip；
Figure 10 is that an embodiment of the present invention provides a kind of possible structural schematic diagrams of circuit board.
Specific implementation mode
Below in conjunction with the attached drawing in embodiment of the present invention, the technical solution in embodiment of the present invention is carried out clear
Chu is fully described by, it is clear that described embodiment is only some embodiments of the invention, rather than whole realities
Apply mode.Based on the embodiment in the present invention, those of ordinary skill in the art institute without making creative work
The every other embodiment obtained, shall fall within the protection scope of the present invention.
Term " first ", " second " in description and claims of this specification and above-mentioned attached drawing etc. are for distinguishing
Different objects, rather than for describing particular order.In addition, term " comprising " and " having " and their any deformations, it is intended that
It is to cover and non-exclusive includes.Such as process, method, system, product or the equipment for containing series of steps or unit do not have
It is defined in the step of having listed or unit, but further includes the steps that optionally not listing or unit, or optionally also wrap
It includes for other intrinsic steps of these processes, method, product or equipment or unit.
" embodiment " is referred in the present invention it is meant that a particular feature, structure, or characteristic described can be in conjunction with the embodiments
It is included at least one embodiment of the present invention.The phrase, which occurs, in each position in the description might not each mean phase
Same embodiment, nor the independent or alternative embodiment with other embodiments mutual exclusion.Those skilled in the art are explicitly
Implicitly understand, embodiment described in the invention can be combined with other embodiments.
Referring to Fig. 1, Fig. 1 is that an embodiment of the present invention provides a kind of structural schematic diagrams of signal processing circuit.Such as Fig. 1 institutes
Show, signal processing circuit is applied to internet-of-things terminal, which includes：PIFA antennas 101, filter 102, switching circuit 103,
First filter network 104, low noise amplifier circuit 105, the second filter network 106 and mixting circuit 107；
The output end of PIFA antennas 101 is connected with the input terminal of filter 102, the output end and switch of filter 102
The input terminal of circuit 103 is connected, and the output end of switching circuit 103 is connected with the input terminal of the first filter network 104, and first
The output end of filter network 104 is connected with the input terminal of low noise amplifier circuit 105, the output of low noise amplifier circuit 105
End is connected with the input terminal of the second filter network 106, the input of the output end and mixting circuit 107 of the second filter network 106
End is connected；
PIFA antennas 101 include radiation patch, feed element and the first capacitance, and the first capacitance is located at radiation patch and feed
Between unit, the input impedance for adjusting PIFA antennas 101；
Low noise amplifier circuit 105 includes the first optimization circuit and the second optimization circuit, and the first optimization circuit is for adjusting
The stability of low noise amplifier circuit 105, the second optimization circuit are used to adjust the matching degree of low noise amplifier circuit 105.
As can be seen that through the embodiment of the present invention, PIFA antennas include radiation patch, feed element and the first capacitance, the
One capacitance is between radiation patch and feed element, the input impedance for adjusting antenna and low noise amplifier circuit packet
Including the first optimization circuit and the second optimization circuit, the first optimization circuit is used to adjust the stability of low noise amplifier circuit, and second
Optimization circuit is used to adjust the matching degree of low noise amplifier circuit, with this, by being arranged between radiation patch and feed element
The capacitance of antenna feed impedance can be adjusted, the input impedance of antenna can be improved to a certain extent, put on the matching degree of antenna,
The first optimization circuit of setting and the second optimization circuit in low noise amplifier circuit, so as to promote low noise to a certain extent
The stability and matching degree of amplifying circuit, and then the performance of circuit entirety can be promoted to a certain extent, it is promoted to radiofrequency signal
Reception with processing performance.
Fig. 2 and Fig. 3 are please referred to, Fig. 2 and Fig. 3 are that an embodiment of the present invention provides a kind of structural schematic diagrams of PIFA antennas.
As described in Fig. 2 and Fig. 3, which includes：Radiation patch 201, feed element 202 and the first capacitance 203, the first capacitance 203
Between radiation patch 201 and feed element 202.
Optionally, feed element 202 can be feed probes etc., be not specifically limited herein, and feed element 202 passes through the
One capacitance 203 be radiation patch fed, while the first capacitance 203 be variable capacitance, can according to the difference of actual environment,
Adjust its capacitance so that the matching degree of antenna is optimal value.
Optionally, filtering device for example can be acoustic surface wave filter device, and signal is passed through electricity by SAW filter
Signal is converted into acoustic signals, then converts acoustic signals to electric signal again, to be filtered out with good selecting frequency characteristic
Noise signal in signal, enhances filter effect to a certain extent, so as to inhibit to a certain extent by sound table
Out-of-band noise after surface wave filter circuit in signal.
Referring to Fig. 4, Fig. 4 is that an embodiment of the present invention provides a kind of structural schematic diagrams of first filter network.Such as Fig. 4 institutes
Show, filter network includes：First filter part 401, second filter part 402, third filtering device 403, the 4th filtering device
404, the 5th filtering device 405, the 6th filtering device 406, the 7th filtering device 407, the filtering of the 8th filtering device the 408, the 9th
Device 409, the tenth filtering device 410, the 11st filtering device 411 and the 12nd filtering device 412；
The first end of first filter part 401 is connected with the first end of second filter part 402, first filter part
401 second end and the 4th filtering device 404, the 5th filtering device 405, the tenth filtering device 410, the 12nd filtering device
412 second end is connected, the second end of second filter part 402 and third filtering device 403, the 7th filtering device 407, the
The first end of eight filtering devices 408 is connected, the first end of the second end of third filtering device 403 and the 4th filtering device 404,
The first end of 5th filtering device 405, the first end of the 6th filtering device 406 are connected, the second end of the 7th filtering device 407
It is connected with the second end of the 6th filtering device 406, the second end of the 9th filtering device 409, the first end of the tenth filtering device 410
It connects, the second end of the 8th filtering device 408 and the first end of the 9th filtering device 409, the first end of the 11st filtering device 411
It is connected, the second end of the 11st filtering device 411 is connected with the first end of the 12nd filtering device 412.
Fig. 5 A are please referred to, Fig. 5 A are that an embodiment of the present invention provides a kind of structural schematic diagrams of low noise amplifier circuit.Such as
Shown in Fig. 5 A, low noise amplifier circuit includes that amplifying circuit 501, first optimizes the optimization circuit 503 of circuit 502 and second, amplification
The output end of circuit 501 is connected with the input terminal of the first optimization circuit 501, the output end and second of the first optimization circuit 501
The input terminal of optimization circuit 503 is connected, and the output end of the second optimization circuit 503 is connected with the output end of low noise amplifier circuit
It connects.
Fig. 5 B are please referred to, Fig. 5 B are that an embodiment of the present invention provides a kind of structural schematic diagrams of first optimization circuit.Such as figure
Shown in 5B, which includes：Second capacitance C2, third capacitance C3, the first inductance L1, the second inductance L2, first resistor R1 and
One MCU501；
The output end of first inductance L1 is connected with the input terminal of the input terminal of the second inductance L2, the second capacitance C2, and second
The output end of capacitance C2 is connected with the second end of the output end of third capacitance C3, first resistor R1, the output of the second inductance L2
End is connected with the input terminal of the input terminal of third capacitance C3, first resistor R1, and the first MCU501 is for controlling the first optimization electricity
The optimization degree on road.
Optionally, the first MCU 501 can periodically detect the impedance of inspection optimization circuit, wherein MCU is microcontroller list
First (Microcontroller Unit) adjusts optimization when the impedance for optimizing circuit low noise amplifier circuit mismatches
The value of capacitance, inductance and resistance in circuit, to achieve the effect that the impedance matching so that low noise amplifier circuit, to be promoted
The optimization degree of first optimization circuit, wherein the detection cycle can specifically be set according to the environment difference of signal processing circuit
Fixed, for example, signal processing circuit is larger (thunderstorm weather etc.) affected by environment, then detection cycle can be shorter, such as 2 minutes, 5 points
Clock etc., signal processing circuit is affected by environment smaller, then detection cycle can be longer, such as 60 minutes, 5 hours.
Referring to Fig. 6, Fig. 6 is that an embodiment of the present invention provides a kind of structural schematic diagrams of second optimization circuit.Such as Fig. 6 institutes
Show, which includes：4th capacitance C4, third inductance L3, second resistance R2,3rd resistor R3 and the 2nd MCU601；
The first end of second resistance R2 is connected with the first end of third inductance L3, the first end of the 4th capacitance C4, second
The second end of resistance R2 is connected with the second end of third inductance L3, the second end of 3rd resistor R3, and the second of the 4th capacitance C4
End is connected with the first end of 3rd resistor R3, and the 2nd MCU601 is used to control the matching degree of the second optimization circuit.
Optionally, the 2nd MCU601 can periodically detect the matching degree of the second optimization circuit, in the second optimization circuit
Matching degree is reduced to when cannot make signal processing circuit cisco unity malfunction, regulation resistance, the value of capacitance and inductance so that low noise
The matching degree of sound amplifying circuit is promoted, to reach the matching degree of signal processing circuit normal work, wherein signal processing circuit
Normal work is：Signal processing circuit can be handled received signal, can be reached and be referred specifically in specific environment
Mark, which can be by user's sets itself, can also be by systemic presupposition, wherein the detection cycle can be according to signal processing
The environment of circuit is different and specifically sets, for example, signal processing circuit is larger (thunderstorm weather etc.) affected by environment, then detects week
Phase can be shorter, such as 2 minutes, 5 minutes, and signal processing circuit is affected by environment smaller, then detection cycle can be longer, and such as 60
Minute, 5 hours etc..
Referring to Fig. 7, Fig. 7 is that an embodiment of the present invention provides a kind of structural schematic diagrams of possible mixting circuit.Such as Fig. 7
Shown, mixting circuit includes：The first transistor T1, second transistor T2, third transistor T3, the 4th transistor T4, the 5th crystalline substance
Body pipe T5, the 6th transistor T6, the 7th transistor T7, the 8th transistor T8, the 4th inductance L4, the 5th capacitance C5, the 6th capacitance
C6, the 7th capacitance C7, the 8th capacitance C8, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6, the 7th resistance R7, the first power supply
701 and second source 702；
The source electrode of the first transistor T1 and the source electrode of second transistor T2, be connected, the drain electrode of the first transistor T1 with
The source electrode of third transistor T3, the 4th transistor T4 source electrode be connected, the drain electrode of third transistor T3 is with the 4th inductance K4
The drain electrode of first end, the 5th transistor T5 is connected, and the grid of third transistor T3 is connected with the grid of the 6th transistor T6,
The second end of 4th inductance L4 and the drain electrode of the 7th transistor T7, the second end of the 5th capacitance C5, the second end of the 4th resistance R4,
The first end of 7th capacitance C7, the first end of the 7th resistance R7 are connected, the second termination of the 7th capacitance C7 and the 7th resistance R7
The of the output end of ground, the source electrode of the 7th transistor T7 and the first power supply 701, the first end of the 5th capacitance C5, the 4th resistance R4
One end is connected, and the drain electrode of second transistor T2 is connected with the source electrode of the source electrode of the 5th transistor T5, the 6th transistor T6, the
The grid of five transistor T5 is connected with the grid of the 4th transistor T4, and the drain electrode of the 6th transistor T6 is with the 4th transistor T4's
Drain electrode, the drain electrode of the 8th transistor T8 are connected, the source electrode of the 8th transistor T8 and first end, the 5th resistance of the 6th capacitance C6
The first end of R5, the output end of second source 702 are connected, the second end of the 6th capacitance C6 and the second end of the 5th resistance R5,
The first end of 6th resistance R6, the first end of the 8th capacitance C8 are connected, the second termination of the 6th resistance R6 and the 8th capacitance C8
Ground.
In one possible example, switching circuit includes：2 road transmission circuits and 4 tunnel receiving circuits, in 2 road transmission circuits
Supports to receive per transmission circuit all the way and only supports to receive with transmitting signal, every receiving circuit all the way in 4 tunnel receiving circuits
Signal, per road transmission circuit and receiving circuit supports Internet of Things frequency range, e.g., the frequency ranges such as 2.4GHz.
In one possible example, signal processing circuit further includes protection circuit, and protection circuit is used to meet in the antenna
By when predeterminated voltage protection is provided for the circuit.
In one possible example, referring to Fig. 8, Fig. 8 is that an embodiment of the present invention provides a kind of protection circuit is possible
Structural schematic diagram.As shown in figure 8, circuit further includes protection circuit, protection circuit is used for when antenna is by predeterminated voltage as electricity
Road provides protection, and protection circuit includes：8th resistance R8, the 9th resistance R9, the tenth resistance R10, eleventh resistor R11, the tenth
Two resistance R12, thirteenth resistor R13, the first voltage-stabiliser tube D1, the second voltage-stabiliser tube D2, third voltage-stabiliser tube D3, the 4th voltage-stabiliser tube D4,
5th voltage-stabiliser tube D5, silicon-controlled D6, the 8th capacitance C8, the 9th capacitance C9, the tenth capacitance C10, the 5th inductance L5, the 6th inductance
L6, the 7th inductance L7, the 8th inductance L8, the 9th inductance L9, the tenth inductance L10, bandstop filter 808, electrostatic detection unit
811, vent unit 810 and transistor T；
The first end of 8th resistance R8 is connected by bandstop filter 808 with the output end of antenna 801, the 8th resistance R8
Second end be connected with the first end of the anode D1 of the first voltage-stabiliser tube, the 9th resistance R9, the minus earth of the first voltage-stabiliser tube D1,
The second end of 9th resistance R9 is connected with the anode of the second voltage-stabiliser tube D2, the minus earth of the second voltage-stabiliser tube D2, the tenth resistance
The first end of R10 is connected by bandstop filter 808 with the output end of antenna 801, the second end and the tenth of the tenth resistance R10
The first end of one resistance R11, the anode of the 4th voltage-stabiliser tube D4 are connected, the minus earth of the 4th voltage-stabiliser tube D4, eleventh resistor
The second end of R11 is connected with the anode of third voltage-stabiliser tube D3, the minus earth of third voltage-stabiliser tube D3, and the first of the 9th inductance L9
End is connected with the output end of antenna 801, and the second end of the 9th inductance L9 is connected with the anode of the 5th voltage-stabiliser tube D5, and the 5th is steady
The cathode of pressure pipe D5 is connected with the first end of twelfth resistor R12, and the second end of twelfth resistor R12 is with the 5th inductance L5's
First end, the first end of thirteenth resistor R13 are connected, the second end ground connection of thirteenth resistor R13, and the second of the 5th inductance L5
Hold first end, the first end of the 9th capacitance C9, the first end of the 6th inductance L6, the grid phase of transistor T with the 8th capacitance C8
Connection, the second end ground connection of the 8th capacitance C8, the second end of the 9th capacitance C9 are connected with the second end of the 6th inductance L6, MCU,
The drain electrode of transistor T is connected with the second end of the tenth inductance L10, the output end of the first end and power supply 809 of the tenth inductance L10
It is connected, the source electrode of transistor T is connected with the control pole of silicon-controlled D6, and the second of the anode of silicon-controlled D6 and the 8th inductance L8
End is connected, and the first end of the 8th inductance L8 is connected with switching circuit 803, the minus earth of silicon-controlled D6, and MCU is hindered by band
Filter 808 and electrostatic detection unit 811 are connected with the output end of filter circuit 802, and MCU passes through the tenth capacitance C10 and
The filter circuit of seven inductance L7 compositions is connected with switching circuit 803, and MCU passes through electrostatic detection unit 811, bandstop filter
808 with the output end of switching circuit 803, the output end of low noise amplifier circuit 804, the output end of mixting circuit 805, PGA
806 output end is connected, and the first end of vent unit 810 is connected with signal processing circuit, the second end of vent unit 810
Ground connection, MCU are connected with vent unit 810.
The operation principle of above-mentioned protection circuit is that, when signal receiving circuit is encountered higher than predeterminated voltage, predeterminated voltage is
The maximum voltage that the signal receiving circuit can be born, the voltage are determined by the circuit of signal receiving circuit itself, protect circuit
In the blanking voltage of D1 be less than the predeterminated voltage, the band of bandstop filter hinders the signal that can be handled for signal processing circuit
Frequency range is arranged this bandstop filter and is mainly used for preventing from the transmitting of signal processing circuit or receive signal to pass through from the branch, from
And the performance of signal processing circuit is reduced, when the voltage of antenna output end is higher than predeterminated voltage in a processing circuit, which makes
D1, D2, D3, D4 and D5 conducting make protection to releasing to the voltage to signal processing circuit, while pass through by
D1, D2 and D3, D4 are arranged in parallel, and release effect of the circuit to the electric current can be promoted when circuit is by heavy current, is provided
The first order is protected, and avoids the power on R8, R9, R10, R11 excessive, and high exoergic phenomenon occurs, to damage protection circuit.
It is considered that possible aforementioned leadage circuit fails to release completely to voltage, there is portion of electrical current to puncture filter circuit, arrive
Up to switching circuit, the second level is set herein and is protected, after D5 conductings, MCU is detected at the grid of transistor there are when voltage, directly
It connects control switching circuit to be fully disconnected, be fully disconnected to be disconnected with all transmitting path and receiving path, while voltage is logical
After crossing the filter network that L5 and C8 is constituted, bias voltage is provided for transistor T so that the conducting of transistor T, to transistor
Source electrode provides control voltage for silicon-controlled D6 and makes controlled silicon conducting, releases to electric current, to realize that the second level is protected.
The also controllable electrostatic detection units of MCU are detected the electrostatic in signal processing circuit, reach pre- in the electrostatic
If when voltage, the predeterminated voltage be electrostatic can discharge voltage, control vent unit the electrostatic in signal processing circuit is let out
It puts, to reach the protection to signal processing circuit.
MCU can also be detected the charge in the environment residing for internet-of-things terminal by charge detection sensor, and inspection is worked as
When measuring intensive charge, it can determine whether out that the region may have highfield or will will appear thunder-strike phenomenon, then directly control out
Powered-down road is fully disconnected, and can avoid the presence damage to the component after switching circuit after strong voltage enters circuit to a certain degree
Bad possibility, to achieve the purpose that protect to internet-of-things terminal.
A kind of chip is provided in another embodiment of the present invention, which includes signal processing as described in Figure 1 electricity
Road, power circuit and processor.Referring to Fig. 9, Fig. 9 is that an embodiment of the present invention provides a kind of possible structural representations of chip
Figure.As shown in figure 9, chip includes：Power circuit 901, processor 902 and rf signal reception circuit 903.Above-mentioned power circuit
901 its major function to provide power supply to the chip, above-mentioned processor 902 for example can be for example can be central processing unit
(Central Processing Unit, CPU), general processor, digital signal processor (Digital Signal
Processor, DSP), application-specific integrated circuit (Application-Specific Integrated Circuit, ASIC) is existing
Field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic device, hardware
Component or its arbitrary combination, rf signal reception circuit 903 are the either circuit described in above-described embodiment.
Another embodiment of the embodiment of the present invention provides a kind of circuit board, which includes modem, base band
The chip provided in signal processor and above-described embodiment.Referring to Fig. 10, Figure 10 is that an embodiment of the present invention provides circuit boards
A kind of possible structural schematic diagram.As shown in Figure 10, which includes：Modem 110, signal processor 120, core
Piece 130 and bus 140.Modem 110, signal processor 120, chip 130 are connected by bus 140.Modem
110 mainly for the treatment of wireless signal by treated the baseband signal of chip 130, signal processor 120 mainly for the treatment of
Signal after the demodulation of modem 110, chip 130 are mainly used for being handled radio frequency signal to obtain base band letter
Number.
A kind of internet-of-things terminal is provided in another embodiment of the present invention, the internet-of-things terminal include foregoing circuit plate and
Shell.
Above specific implementation mode has carried out into one the purpose, technical solution and advantageous effect of the embodiment of the present invention
Step is described in detail, it should be understood that these are only the specific implementation mode of the embodiment of the present invention, is not used to limit this
The protection domain of inventive embodiments, all any modifications on the basis of the technical solution of the embodiment of the present invention, made are equal
Replace, improve etc., it should all be included within the protection domain of the embodiment of the present invention.
Claims (10)
1. a kind of signal processing circuit, which is characterized in that be applied to internet-of-things terminal, the circuit includes：PIFA antennas, filtering
Device, switching circuit, the first filter network, low noise amplifier circuit, the second filter network and mixting circuit；
The output end of the PIFA antennas is connected with the input terminal of the filter, and the output end of the filter is opened with described
The input terminal on powered-down road is connected, and the output end of the switching circuit is connected with the input terminal of first filter network, institute
The output end for stating the first filter network is connected with the input terminal of the low noise amplifier circuit, the low noise amplifier circuit
Output end is connected with the input terminal of second filter network, output end and the mixting circuit of second filter network
Input terminal be connected；
The PIFA antennas include radiation patch, feed element and the first capacitance, and first capacitance is located at the radiation patch
Between the feed element, the input impedance for adjusting the PIFA antennas；
The low noise amplifier circuit includes the first optimization circuit and the second optimization circuit, and the first optimization circuit is for adjusting
The stability of the low noise amplifier circuit, the second optimization circuit are used to adjust the matching of the low noise amplifier circuit
Degree.
2. circuit according to claim 1, which is characterized in that first filter network includes：First filter part,
Two filtering devices, third filtering device, the 4th filtering device, the 5th filtering device, the 6th filtering device, the 7th filtering device,
8th filtering device, the 9th filtering device, the tenth filtering device, the 11st filtering device and the 12nd filtering device；
The first end of the first filter part is connected with the first end of the second filter part, the first filter part
Second end and the 4th filtering device, the 5th filtering device, the tenth filtering device, the 12nd filter
The second end of part is connected, the second end of the second filter part and the third filtering device, the 7th filtering device,
The first end of 8th filtering device is connected, and the of the second end of the third filtering device and the 4th filtering device
One end, the first end of the 5th filtering device, the first end of the 6th filtering device are connected, the 7th filtering device
The second end of second end and the 6th filtering device, the second end of the 9th filtering device, the tenth filtering device
First end be connected, the second end of the 8th filtering device and the first end of the 9th filtering device, the described 11st
The first end of filtering device is connected, the first end of the second end and the 12nd filtering device of the 11st filtering device
It is connected.
3. circuit according to claim 1 or 2, which is characterized in that described first, which optimizes circuit, includes：Second capacitance,
Three capacitances, the first inductance, the second inductance, first resistor and the first MCU；
The output end of first inductance is connected with the input terminal of the input terminal of second inductance, second capacitance, institute
The output end for stating the second capacitance is connected with the second end of the output end of the third capacitance, the first resistor, and described second
The output end of inductance is connected with the input terminal of the input terminal of the third capacitance, the first resistor, and the first MCU is used for
Control the optimization degree of the first optimization circuit.
4. circuit according to any one of claims 1 to 3, which is characterized in that described second, which optimizes circuit, includes：4th electricity
Appearance, third inductance, second resistance, 3rd resistor and the 2nd MCU；
The first end of the second resistance is connected with the first end of the first end of the third inductance, the 4th capacitance, institute
The second end for stating second resistance is connected with the second end of the third inductance, the second end of the 3rd resistor, and the described 4th
The second end of capacitance is connected with the first end of the 3rd resistor, and the 2nd MCU is for controlling the second optimization circuit
Matching degree.
5. circuit according to any one of claims 1 to 4, which is characterized in that the mixting circuit includes：First crystal
Pipe, second transistor, third transistor, the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor, the 8th crystal
Pipe, the 4th inductance, the 5th capacitance, the 6th capacitance, the 7th capacitance, the 8th capacitance, the 4th resistance, the 5th resistance, the 6th resistance,
Seven resistance, the first power supply and second source；
The source electrode of the first transistor and the source electrode of the second transistor, be connected, the drain electrode of the first transistor
Be connected with the source electrode of the source electrode of the third transistor, the 4th transistor, the drain electrode of the third transistor with it is described
The drain electrode of the first end of 4th inductance, the 5th transistor is connected, and the grid of the third transistor is brilliant with the described 6th
The grid of body pipe is connected, the draining of the second end of the 4th inductance and the 7th transistor, the 5th capacitance the
Two ends, the second end of the 4th resistance, the first end of the 7th capacitance, the first end of the 7th resistance are connected, institute
State the second end ground connection of the 7th capacitance and the 7th resistance, the output of the source electrode and first power supply of the 7th transistor
End, the first end of the 5th capacitance, the first end of the 4th resistance are connected, the drain electrode of the second transistor with it is described
The source electrode of 5th transistor, the 6th transistor source electrode be connected, the grid of the 5th transistor and the described 4th brilliant
The grid of body pipe is connected, the drain electrode of the 6th transistor and the draining of the 4th transistor, the 8th transistor
Drain electrode is connected, the source electrode of the 8th transistor and the first end of the 6th capacitance, the first end of the 5th resistance, institute
The output end for stating second source is connected, the second end of the 6th capacitance and the second end of the 5th resistance, the described 6th
The first end of resistance, the first end of the 8th capacitance are connected, the second termination of the 6th resistance and the 8th capacitance
Ground.
6. circuit according to claim 1, which is characterized in that the switching circuit includes：2 road transmission circuits and 4 tunnels receive
Circuit, supporting to receive per transmission circuit all the way and emits signal in the transmission circuit of 2 road, in the receiving circuit of 4 tunnel
Only supports reception signal per receiving circuit all the way.
7. according to claim 1-6 any one of them circuits, which is characterized in that the circuit further includes protection circuit, described
Protection circuit for the circuit when the antenna is by predeterminated voltage for providing protection.
8. a kind of chip, which is characterized in that the chip includes described in processor, power circuit and claim any one of 1-7
Signal processing circuit.
9. a kind of circuit board, which is characterized in that the circuit board includes modem, signal processor and claim 8 institute
The chip stated.
10. a kind of internet-of-things terminal, which is characterized in that the internet-of-things terminal includes the circuit described in shell and claim 9
Plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810292621.XA CN108599800A (en) | 2018-03-30 | 2018-03-30 | Internet of Things radio circuit and terminal based on PIFA antennas and lumped parameter matching type |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810292621.XA CN108599800A (en) | 2018-03-30 | 2018-03-30 | Internet of Things radio circuit and terminal based on PIFA antennas and lumped parameter matching type |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108599800A true CN108599800A (en) | 2018-09-28 |
Family
ID=63624360
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810292621.XA Pending CN108599800A (en) | 2018-03-30 | 2018-03-30 | Internet of Things radio circuit and terminal based on PIFA antennas and lumped parameter matching type |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108599800A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101378248A (en) * | 2007-08-29 | 2009-03-04 | 宏观微电子股份有限公司 | Low noise amplifier and tuner including the same |
| CN102291157A (en) * | 2011-05-13 | 2011-12-21 | 京信通信系统（中国）有限公司 | Multi-system channel multiplex circuit |
| CN102932017A (en) * | 2011-08-08 | 2013-02-13 | 中国科学院微电子研究所 | Radio frequency receiver |
| CN103765674A (en) * | 2011-08-31 | 2014-04-30 | 高通股份有限公司 | Wireless device with 3-D antenna system |
-
2018
- 2018-03-30 CN CN201810292621.XA patent/CN108599800A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101378248A (en) * | 2007-08-29 | 2009-03-04 | 宏观微电子股份有限公司 | Low noise amplifier and tuner including the same |
| CN102291157A (en) * | 2011-05-13 | 2011-12-21 | 京信通信系统（中国）有限公司 | Multi-system channel multiplex circuit |
| CN102932017A (en) * | 2011-08-08 | 2013-02-13 | 中国科学院微电子研究所 | Radio frequency receiver |
| CN103765674A (en) * | 2011-08-31 | 2014-04-30 | 高通股份有限公司 | Wireless device with 3-D antenna system |
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Application publication date: 20180928 |