CN108573968B - Method for alternately wiring source and grid in hole based on elliptical orbit - Google Patents
Method for alternately wiring source and grid in hole based on elliptical orbit Download PDFInfo
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- CN108573968B CN108573968B CN201810442081.9A CN201810442081A CN108573968B CN 108573968 B CN108573968 B CN 108573968B CN 201810442081 A CN201810442081 A CN 201810442081A CN 108573968 B CN108573968 B CN 108573968B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
Abstract
An in-hole source and gate alternative wiring method based on an elliptical orbit comprises the following steps: defining a port; determining a guide fold line; sequencing the ports; determining the center line of a group of matched Data port pairs; determining a set of matched Gate port pairs; a wiring profile is generated. The wiring technical scheme can successfully solve the problem of alternative wiring of TFT source electrodes and grid electrodes in the pixel area holes of the special-shaped panel, meets the geometric constraint of design, is compact in wiring and saves space.
Description
Technical Field
The invention relates to the field of EDA (electronic design automation) design tools for flat panel displays, in particular to an in-hole source electrode grid alternative wiring method based on an elliptical track.
Background
In the design of the special-shaped panel, many manufacturers wish to leave a hole in the active pixel region for the subsequent differential design, for example, reserve a circular hole in the display screen of a mobile phone for placing a front camera, as shown in fig. 1 and 2. The pixels (TFT) at the edge of the circular hole are separated due to the existence of the hole in the pixel area of the display screen. In order to complete wiring between TFTs at the edge of a circular hole, there is a single-layer wiring method of connecting a source electrode or a gate electrode based on an elliptical orbit in the hole.
In order to help engineers to complete the wiring of two kinds of ports of a source electrode (DATA) and a grid electrode (GATE) simultaneously and quickly, the wiring is compact, and the space of a panel is saved. The invention provides an in-hole source electrode grid electrode alternate wiring method based on an elliptical orbit.
Disclosure of Invention
In order to solve the defects of the prior art, the invention aims to provide an in-hole source electrode and grid electrode alternative wiring method based on an elliptical orbit.
In order to achieve the above object, the present invention provides an elliptical orbit-based method for alternately wiring source and gate electrodes in a hole, comprising the following steps:
1) defining a port;
2) determining a guide fold line;
3) sequencing the ports;
4) determining the center line of a group of matched Data port pairs;
5) determining a set of matched Gate port pairs;
6) a wiring profile is generated.
Further, the defining of the ports refers to defining the upper half Data port of the AA region reserved hole as StartData, the lower half Data port as End Data, the left half Gate port as Start Gate, and the right half Gate port as End Gate.
Further, the guide folding line is a closed ellipse.
Further, the step 3) of sorting the ports means that the Start Data and the End Data are sorted from small to large according to the abscissa, and the Start Gate and the End Gate are sorted from small to large according to the ordinate.
Further, the step 4) further comprises the following steps:
51) expanding the guide folding line outwards by a wiring interval to obtain an elliptical track;
52) selecting two pairs of ports in the middle from Start Data and End Data which are not wired;
53) respectively leading four rays in the vertical direction from the middle points of the four DATA ports and the ellipse to calculate intersection points, and cutting the ellipse into a left part, a middle part and a right part by the four intersection points;
54) the two pairs of DATA ports are assigned left and right semi-elliptical orbits.
Further, the step 5) further comprises the following steps:
61) expanding the elliptical orbit obtained in the last wiring step outwards by a wiring interval;
62) selecting two pairs of ports which are positioned at the middle from Start Gate and End Gate which are not wired;
63) respectively leading four rays in the horizontal direction from the middle points of the four ports and the ellipse to calculate intersection points, and cutting the ellipse track into an upper part, a middle part and a lower part by the four intersection points;
64) upper and lower elliptical orbits are assigned to the ports.
Further, the principle of determining the wiring pitch is as follows: if the current wiring is the first wiring, the distance is half of the minimum line width of the wiring, otherwise, the distance is half of the sum of the minimum line widths of the current wiring and the last wiring of the two wiring process layers.
Furthermore, in the wiring process for generating the wiring outline, if the last remaining non-wiring port is a DATA port, the central line of a group of matched DATA port pairs is determined for wiring, and if the last remaining non-wiring port is a GATE port, the central line of a group of matched GATE port pairs is determined for wiring.
The wiring technical scheme can successfully solve the problem of alternative wiring of TFT source electrodes and grid electrodes in the pixel area holes of the special-shaped panel, meets the geometric constraint of design, is compact in wiring and saves space.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a flowchart of the source-gate alternative wiring method in a hole based on an elliptical orbit according to the present invention;
FIG. 2 is a schematic diagram of a mobile phone display screen with a circular hole reserved therein according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of the distribution of ports at the reserved circular holes in FIG. 2;
FIG. 4 is a schematic diagram of guided polyline generation, according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a first set of Data port pairs after routing, according to an embodiment of the invention;
FIG. 6 is a schematic diagram of a first set of Gate port pairs after routing, according to an embodiment of the invention;
FIG. 7 is a schematic view of a wiring process layer arrangement according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of setting the minimum line spacing of two routing process layers according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a port selection page according to an embodiment of the invention;
FIG. 10 is a schematic diagram of pre-wiring between ports according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of a highlighted guide fold line according to an embodiment of the present invention;
fig. 12 is a schematic diagram of wiring results according to an embodiment of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
Fig. 1 is a flowchart of the method for alternately wiring source and gate electrodes in a hole based on an elliptical orbit according to the present invention. An elliptical orbit-based in-hole source-gate alternative wiring method of the present invention will be described with reference to fig. 1.
First, in step 101, a port is defined.
In this step, the upper half Data port of the (active pixel region) reserved hole is referred to as Start Data, the lower half Data port is referred to as End Data, the left half Gate port is referred to as Start Gate, and the right half Gate port is referred to as End Gate.
At step 102, a guide polyline is determined.
In this step, a closed ellipse, called a Guide Line (Guide Line), is drawn in the middle of the hole, as shown in fig. 4. In an EDA tool, the guide polyline is approximated by an N-polygon. The value of N can be adjusted, and the larger N is, the smoother the whole ellipse is.
In step 103, the ports are sorted.
In the step, the Start Data port, the End Data port, the Start Gate port and the End Gate port are respectively sorted, wherein the Start Data port and the End Data port are respectively sorted from small to large according to an abscissa, and the Start Gate port and the End Gate port are respectively sorted from small to large according to an ordinate.
At step 104, the centerlines of a set of matching Data port pairs are determined.
In this step, the guiding broken Line (Guide Line) is extended outward by one wiring pitch to obtain an elliptical orbit, and the two central pairs of ports are selected from Start Data and End Data which are not wired yet. Four vertical rays are respectively led from the middle points of the four DATA ports to find intersection points with the ellipse, the ellipse is cut into a left part, a middle part and a right part by the four intersection points, and left and right semi-ellipse tracks are distributed for the two pairs of DATA ports, as shown in figure 5.
Wherein, the selection of the wiring pitch follows the following principle: when the wiring is the first wiring, the distance is half of the minimum line width of the wiring, otherwise, the distance is half of the sum of the minimum line width and the minimum line width of the wiring process layers of the wiring.
At step 105, the centerlines of a set of matching Gate port pairs are determined.
In this step, the elliptical orbit obtained in the previous step is expanded outward by a wiring interval, two pairs of ports located at the middlemost are selected from Start Gate and End Gate which are not wired yet, four rays in the horizontal direction are respectively led from the midpoints of the four ports to find intersection points with the ellipse, and the elliptical orbit is cut into an upper part, a middle part and a lower part by the four intersection points to allocate an upper elliptical orbit and a lower elliptical orbit to the ports, as shown in fig. 6.
Wherein, the selection of the wiring pitch follows the following principle: when the wiring is the first wiring, the distance is half of the minimum line width of the wiring, otherwise, the distance is half of the sum of the minimum line width and the minimum line width of the wiring process layers of the wiring.
In step 106, steps 104, 105 are repeated.
In this step, steps 104, 105 are repeated, completing the DATA and GATE alternate wiring.
Finally, if there are DATA ports that are not wired, step 104 is repeated, and if there are GATEs that are not wired, step 105 is repeated.
The following describes in detail the application of the method for source-gate alternative wiring in holes based on elliptical orbits according to the present invention with reference to the specific embodiments.
(1) Starting a track wiring command and setting wiring parameters;
a Rail Routing command is initiated in the Aether FPD tool, setting parameters in the corresponding page. FIG. 7 is a schematic diagram of a wiring process layer arrangement according to an embodiment of the present invention, as shown in FIG. 7, with wiring geometry constraints for DATA and GATE. Fig. 8 is a schematic diagram of setting the minimum line pitch of two wiring process layers according to an embodiment of the present invention, and as shown in fig. 8, the minimum line pitch of two wiring process layers is set. Fig. 9 is a schematic diagram of a port selection page according to an embodiment of the present invention, as shown in fig. 9, for performing port selection.
(2) Selecting two groups of ports needing wiring operation;
FIG. 10 is a diagram of pre-wiring between ports according to an embodiment of the invention, where the pre-wiring between the ports is pre-wiring between DATA- > DATA and GATE- > GATE ports.
(3) Selecting a Guide Line (Guide Line);
after the port is selected, a pre-drawn Guide polyline (Guide Line) graphic is designated, and the corresponding Guide polyline (Guide Line) graphic is highlighted, as shown in fig. 11.
(4) Finishing wiring according to design requirements;
fig. 12 is a schematic diagram of wiring results according to an embodiment of the present invention. And if the wiring result meets the design requirement, clicking a button for generating wiring to finish wiring.
The invention simultaneously completes the wiring of the source electrode and the grid electrode in the pixel area hole by using two wiring process layers based on the elliptical orbit. The wiring is formed by alternately wiring the source and the gate. The source electrode and the grid electrode are compactly wired, the minimum wire distance between the two wiring process layers is adjustable, and the space of a panel is saved.
Those of ordinary skill in the art will understand that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. An in-hole source and gate alternative wiring method based on an elliptical orbit is characterized by comprising the following steps:
1) defining a port;
2) determining a guide fold line;
3) sequencing the ports;
4) determining the center line of a group of matched Data port pairs;
the step 4) further comprises the following steps:
41) expanding the guide folding line outwards by a wiring interval to obtain an elliptical track;
42) selecting two pairs of ports in the middle from Start Data and End Data which are not wired;
43) respectively leading four rays in the vertical direction from the middle points of the four DATA ports and the ellipse to calculate intersection points, and cutting the ellipse into a left part, a middle part and a right part by the four intersection points;
44) assigning left and right semi-elliptical orbits for the two pairs of DATA ports;
5) determining a set of matched Gate port pairs;
6) a wiring profile is generated.
2. The method as claimed in claim 1, wherein the defining of the ports is defined as defining the upper half Data port of the reserved hole as Start Data, the lower half Data port as End Data, the left half Gate port as Start Gate, and the right half Gate port as End Gate.
3. The elliptical orbit based intra-hole source-gate alternative wiring method of claim 1, wherein the guiding meander line is a closed ellipse.
4. The method for alternately wiring the source electrode and the Gate electrode in the hole based on the elliptical orbit, according to the claim 1 or 2, the step 3) is used for sorting the ports, namely, the Start Data and the End Data are respectively sorted from small to large according to the abscissa, and the Start Gate and the End Gate are respectively sorted from small to large according to the ordinate.
5. The elliptical orbit based intra-hole source-gate alternative wiring method as claimed in claim 1, wherein said step 5) further comprises the steps of:
61) expanding the elliptical orbit obtained in the last wiring step outwards by a wiring interval;
62) selecting two pairs of ports which are positioned at the middle from Start Gate and End Gate which are not wired;
63) respectively leading four rays in the horizontal direction from the middle points of the four ports and the ellipse to calculate intersection points, and cutting the ellipse track into an upper part, a middle part and a lower part by the four intersection points;
64) and upper and lower elliptical orbits are allocated to the two pairs of Gate ports.
6. The elliptical orbit based intra-hole source-gate alternative wiring method as claimed in claim 5, wherein the wiring pitch is determined by the following principle: if the current wiring is the first wiring, the distance is half of the minimum line width of the wiring, otherwise, the distance is half of the sum of the minimum line widths of the current wiring and the last wiring of the two wiring process layers.
7. The method as claimed in claim 1, wherein during the wiring process of generating the wiring profile, if the last remaining non-wiring port is a DATA port, the central line of a group of matched DATA port pairs is determined for wiring, and if the last remaining non-wiring port is a GATE port, the central line of a group of matched GATE port pairs is determined for wiring.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810442081.9A CN108573968B (en) | 2018-05-10 | 2018-05-10 | Method for alternately wiring source and grid in hole based on elliptical orbit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810442081.9A CN108573968B (en) | 2018-05-10 | 2018-05-10 | Method for alternately wiring source and grid in hole based on elliptical orbit |
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| CN108573968A CN108573968A (en) | 2018-09-25 |
| CN108573968B true CN108573968B (en) | 2020-04-07 |
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| CN109684754B (en) * | 2018-12-28 | 2020-07-10 | 北京华大九天软件有限公司 | Inclined port wiring method based on track in special-shaped layout |
| CN112800702B (en) * | 2021-02-03 | 2022-04-15 | 北京华大九天科技股份有限公司 | R-corner automatic layout and wiring method and device and storage medium |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106611086A (en) * | 2016-12-26 | 2017-05-03 | 北京华大九天软件有限公司 | Method for wiring between two sets of ports in layout |
| US9853096B1 (en) * | 2015-09-18 | 2017-12-26 | Apple Inc. | Display with inactive area surrounded by active area |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP4178090B2 (en) * | 2003-09-19 | 2008-11-12 | シャープ株式会社 | Electrode wiring board and display device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9853096B1 (en) * | 2015-09-18 | 2017-12-26 | Apple Inc. | Display with inactive area surrounded by active area |
| CN106611086A (en) * | 2016-12-26 | 2017-05-03 | 北京华大九天软件有限公司 | Method for wiring between two sets of ports in layout |
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| CN108573968A (en) | 2018-09-25 |
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Address after: 100102 floor 2, block a, No.2, lizezhong 2nd Road, Chaoyang District, Beijing Patentee after: Beijing Huada Jiutian Technology Co.,Ltd. Address before: 100102 floor 2, block a, No.2, lizezhong 2nd Road, Chaoyang District, Beijing Patentee before: HUADA EMPYREAN SOFTWARE Co.,Ltd. |
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